Hi Tomas,
On Thu, 19 Nov 2020 at 20:28, Tomas Pilar <tomas@nuviainc.com> wrote:
> Fix the PCD numbering for PcdPciExpressBarLimit to be sequential.
>
> Cc: Leif Lindholm <leif@nuviainc.com>
> Cc: Ard Biesheuvel <ard.biesheuvel@arm.com>
> Cc: Tanmay Jagdale <tanmay.jagdale@linaro.org>
> Signed-off-by: Tomas Pilar <tomas@nuviainc.com>
>
Tested this patch series and didn't face any issues.
Tested-by: Tanmay Jagdale <tanmay.jagdale@linaro.org>
> ---
> Silicon/Qemu/SbsaQemu/SbsaQemu.dec | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/Silicon/Qemu/SbsaQemu/SbsaQemu.dec
> b/Silicon/Qemu/SbsaQemu/SbsaQemu.dec
> index 1bc3e35b9b..2831781c4e 100644
> --- a/Silicon/Qemu/SbsaQemu/SbsaQemu.dec
> +++ b/Silicon/Qemu/SbsaQemu/SbsaQemu.dec
> @@ -45,7 +45,7 @@
> # PCDs complementing gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress
> # BarLimit = BaseAddress + Size - 1
>
> gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPciExpressBarSize|0x10000000|UINT64|0x00000009
> -
> gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPciExpressBarLimit|0xFFFFFFFF|UINT64|0x00000010
> +
> gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPciExpressBarLimit|0xFFFFFFFF|UINT64|0x000000a
>
> [PcdsDynamic.common]
>
> gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdCoreCount|0x1|UINT32|0x00000100
> --
> 2.25.1
>
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