BIOS uses TE with a null root entry table to block VT-d engine access
to block any DMA traffic in pre-memory phase.

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2867

Cc: Ray Ni <ray.ni@intel.com>
Cc: Rangasai V Chaganty <rangasai.v.chaganty@intel.com>
Signed-off-by: Sheng Wei <w.sheng@intel.com>
---
 .../PlatformVTdInfoSamplePei/PlatformVTdInfoSamplePei.c  | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSamplePei/PlatformVTdInfoSamplePei.c b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSamplePei/PlatformVTdInfoSamplePei.c
index 6f6c14f7a9..1399f4238d 100644
--- a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSamplePei/PlatformVTdInfoSamplePei.c
+++ b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSamplePei/PlatformVTdInfoSamplePei.c
@@ -164,6 +164,17 @@ EFI_PEI_PPI_DESCRIPTOR mPlatformVTdNoIgdInfoSampleDesc = {
   &mPlatformVTdNoIgdSample
 };
 
+EFI_GUID gVTdNullRootEntryTableGuid = { 0x3de0593f, 0x6e3e, 0x4542, { 0xa1, 0xcb, 0xcb, 0xb2, 0xdb, 0xeb, 0xd8, 0xff }};
+
+// BIOS uses TE with a null root entry table to block VT-d engine access to block any DMA traffic in pre-memory phase.
+UINT64 mNullRootEntryTable = 0xFED20000;
+
+EFI_PEI_PPI_DESCRIPTOR mPlatformNullRootEntryTableDesc = {
+  (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
+  &gVTdNullRootEntryTableGuid,
+  &mNullRootEntryTable
+};
+
 /**
   Initialize VTd register.
   Initialize the VTd hardware unit which has INCLUDE_PCI_ALL set
@@ -349,6 +360,11 @@ PlatformVTdInfoSampleInitialize (
     Status = PeiServicesNotifyPpi (&mSiliconInitializedNotifyList);
     InitGlobalVtd ();
 
+    Status = PeiServicesInstallPpi (&mPlatformNullRootEntryTableDesc);
+    if (EFI_ERROR (Status)) {
+      DEBUG ((DEBUG_ERROR , "Failed to install the NullRootEntryTable ppi - %r\n", Status));
+    }
+
     Status = PeiServicesInstallPpi (&mPlatformVTdNoIgdInfoSampleDesc);
     ASSERT_EFI_ERROR (Status);
   } else {
-- 
2.16.2.windows.1


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