SbsaQemu: Initial support for static ACPI tables

[edk2-devel] SbsaQemu: Initial support for static ACPI tables

Posted by Tanmay Jagdale 3 years, 11 months ago

Add the following static ACPI tables for the SBSA Qemu platform
  - DSDT
  - FADT
  - GTDT
  - MADT
  - MCFG
  - SPCR

Currently we support 4 CPUs.

Co-authored-by: Graeme Gregory <graeme.gregory@linaro.org>
Co-authored-by: Jonathan Cameron <jonathan.cameron@huawei.com>
Co-authored-by: Tanmay Jagdale <tanmay.jagdale@linaro.org>
Signed-off-by: Tanmay Jagdale <tanmay.jagdale@linaro.org>
---
 Platform/Qemu/SbsaQemu/SbsaQemu.dsc           |   11 +-
 Platform/Qemu/SbsaQemu/SbsaQemu.fdf           |   14 +
 Silicon/Qemu/SbsaQemu/Acpi.dsc.inc            |   42 +
 Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.h |   61 +
 .../Qemu/SbsaQemu/AcpiTables/AcpiTables.inf   |   47 +
 Silicon/Qemu/SbsaQemu/AcpiTables/Dsdt.asl     | 1400 +++++++++++++++++
 Silicon/Qemu/SbsaQemu/AcpiTables/Fadt.aslc    |   85 +
 Silicon/Qemu/SbsaQemu/AcpiTables/Gtdt.aslc    |   71 +
 Silicon/Qemu/SbsaQemu/AcpiTables/Madt.aslc    |   85 +
 Silicon/Qemu/SbsaQemu/AcpiTables/Mcfg.aslc    |   50 +
 Silicon/Qemu/SbsaQemu/AcpiTables/Spcr.aslc    |  122 ++
 .../SbsaQemuPlatformDxe/SbsaQemuPlatformDxe.c |    6 +
 .../SbsaQemuPlatformDxe.inf                   |   10 +
 13 files changed, 2003 insertions(+), 1 deletion(-)
 create mode 100644 Silicon/Qemu/SbsaQemu/Acpi.dsc.inc
 create mode 100644 Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.h
 create mode 100644 Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf
 create mode 100644 Silicon/Qemu/SbsaQemu/AcpiTables/Dsdt.asl
 create mode 100644 Silicon/Qemu/SbsaQemu/AcpiTables/Fadt.aslc
 create mode 100644 Silicon/Qemu/SbsaQemu/AcpiTables/Gtdt.aslc
 create mode 100644 Silicon/Qemu/SbsaQemu/AcpiTables/Madt.aslc
 create mode 100644 Silicon/Qemu/SbsaQemu/AcpiTables/Mcfg.aslc
 create mode 100644 Silicon/Qemu/SbsaQemu/AcpiTables/Spcr.aslc

diff --git a/Platform/Qemu/SbsaQemu/SbsaQemu.dsc b/Platform/Qemu/SbsaQemu/SbsaQemu.dsc
index 4db3ab4651..ac1398af8f 100644
--- a/Platform/Qemu/SbsaQemu/SbsaQemu.dsc
+++ b/Platform/Qemu/SbsaQemu/SbsaQemu.dsc
@@ -300,6 +300,10 @@ DEFINE NETWORK_HTTP_BOOT_ENABLE       = FALSE
   gEfiMdePkgTokenSpaceGuid.PcdPostCodePropertyMask|0
   gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|320
 
+  # Core and Cluster Count
+  gArmPlatformTokenSpaceGuid.PcdCoreCount|4
+  gArmPlatformTokenSpaceGuid.PcdClusterCount|1
+
   # DEBUG_ASSERT_ENABLED       0x01
   # DEBUG_PRINT_ENABLED        0x02
   # DEBUG_CODE_ENABLED         0x04
@@ -376,7 +380,6 @@ DEFINE NETWORK_HTTP_BOOT_ENABLE       = FALSE
   #
   gEfiMdeModulePkgTokenSpaceGuid.PcdSetNxForStack|TRUE
 
-  gArmPlatformTokenSpaceGuid.PcdCoreCount|1
   gArmTokenSpaceGuid.PcdVFPEnabled|1
 
   # System Memory Base -- fixed
@@ -516,6 +519,7 @@ DEFINE NETWORK_HTTP_BOOT_ENABLE       = FALSE
   ShellPkg/Application/Shell/Shell.inf {
     <LibraryClasses>
       ShellCommandLib|ShellPkg/Library/UefiShellCommandLib/UefiShellCommandLib.inf
+      NULL|ShellPkg/Library/UefiShellAcpiViewCommandLib/UefiShellAcpiViewCommandLib.inf
       NULL|ShellPkg/Library/UefiShellLevel2CommandsLib/UefiShellLevel2CommandsLib.inf
       NULL|ShellPkg/Library/UefiShellLevel1CommandsLib/UefiShellLevel1CommandsLib.inf
       NULL|ShellPkg/Library/UefiShellLevel3CommandsLib/UefiShellLevel3CommandsLib.inf
@@ -675,3 +679,8 @@ DEFINE NETWORK_HTTP_BOOT_ENABLE       = FALSE
   MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf
   MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf
   MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf
+
+  #
+  # ACPI Support
+!include Silicon/Qemu/SbsaQemu/Acpi.dsc.inc
+  MdeModulePkg/Universal/Acpi/BootGraphicsResourceTableDxe/BootGraphicsResourceTableDxe.inf
diff --git a/Platform/Qemu/SbsaQemu/SbsaQemu.fdf b/Platform/Qemu/SbsaQemu/SbsaQemu.fdf
index be7c78aceb..7f1a60e3ee 100644
--- a/Platform/Qemu/SbsaQemu/SbsaQemu.fdf
+++ b/Platform/Qemu/SbsaQemu/SbsaQemu.fdf
@@ -227,6 +227,14 @@ READ_LOCK_STATUS   = TRUE
   INF MdeModulePkg/Bus/Scsi/ScsiBusDxe/ScsiBusDxe.inf
   INF MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDiskDxe.inf
 
+  #
+  # ACPI support
+  #
+  INF MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf
+  INF MdeModulePkg/Universal/Acpi/AcpiPlatformDxe/AcpiPlatformDxe.inf
+  INF RuleOverride = ACPITABLE Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf
+  INF MdeModulePkg/Universal/Acpi/BootGraphicsResourceTableDxe/BootGraphicsResourceTableDxe.inf
+
   #
   # PCI support
   #
@@ -301,3 +309,9 @@ READ_LOCK_STATUS   = TRUE
   }
 
 !include ArmVirtPkg/ArmVirtRules.fdf.inc
+
+[Rule.Common.USER_DEFINED.ACPITABLE]
+  FILE FREEFORM = $(NAMED_GUID) {
+    RAW ACPI               |.acpi
+    RAW ASL                |.aml
+  }
diff --git a/Silicon/Qemu/SbsaQemu/Acpi.dsc.inc b/Silicon/Qemu/SbsaQemu/Acpi.dsc.inc
new file mode 100644
index 0000000000..76d0fac079
--- /dev/null
+++ b/Silicon/Qemu/SbsaQemu/Acpi.dsc.inc
@@ -0,0 +1,42 @@
+#
+#  Copyright (c) 2018, Linaro Limited. All rights reserved.
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+
+################################################################################
+#
+# Pcd Section - list of all EDK II PCD Entries defined by this Platform
+#
+################################################################################
+
+[PcdsFeatureFlag]
+  gEfiMdeModulePkgTokenSpaceGuid.PcdInstallAcpiSdtProtocol|TRUE
+
+[PcdsFixedAtBuild.common]
+  gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemId|"LNRO  "
+  gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemTableId|0x4153425341534253 # SBSA
+  gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemRevision|0x20190910
+  gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultCreatorId|0x4f524e4c # LNRO
+  gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultCreatorRevision|1
+
+################################################################################
+#
+# Components Section - list of all EDK II Modules needed by this Platform
+#
+################################################################################
+
+[Components.common]
+  #
+  # ACPI support
+  #
+  MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf {
+    <LibraryClasses>
+      NULL|EmbeddedPkg/Library/PlatformHasAcpiLib/PlatformHasAcpiLib.inf
+
+    <PcdsFixedAtBuild>
+      # support ACPI v5.0 or later
+      gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiExposedTableVersions|0x20
+  }
+  MdeModulePkg/Universal/Acpi/AcpiPlatformDxe/AcpiPlatformDxe.inf
+  Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf
diff --git a/Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.h b/Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.h
new file mode 100644
index 0000000000..a30ade5a92
--- /dev/null
+++ b/Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.h
@@ -0,0 +1,61 @@
+/** @file
+*
+*  Copyright (c) 2013-2014, ARM Limited. All rights reserved.
+*  Copyright (c) 2018, Linaro Limited. All rights reserved.
+*
+*  SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+**/
+
+#ifndef __ACPITABLES_H__
+#define __ACPITABLES_H__
+
+//
+// ACPI table information used to initialize tables.
+//
+#define EFI_ACPI_OEM_ID           'L','N','R','O',' ',' '
+#define EFI_ACPI_OEM_TABLE_ID     SIGNATURE_64('S','B','S','A','S','B','S','A')
+#define EFI_ACPI_OEM_REVISION     FixedPcdGet32 (PcdAcpiDefaultOemRevision)
+#define EFI_ACPI_CREATOR_ID       SIGNATURE_32('L','N','R','O')
+#define EFI_ACPI_CREATOR_REVISION FixedPcdGet32 (PcdAcpiDefaultCreatorRevision)
+
+// A macro to initialise the common header part of EFI ACPI tables as defined by
+// EFI_ACPI_DESCRIPTION_HEADER structure.
+#define __ACPI_HEADER(Signature, Type, Revision) {                \
+    Signature,                      /* UINT32  Signature */       \
+    sizeof (Type),                  /* UINT32  Length */          \
+    Revision,                       /* UINT8   Revision */        \
+    0,                              /* UINT8   Checksum */        \
+    { EFI_ACPI_OEM_ID },            /* UINT8   OemId[6] */        \
+    EFI_ACPI_OEM_TABLE_ID,          /* UINT64  OemTableId */      \
+    EFI_ACPI_OEM_REVISION,          /* UINT32  OemRevision */     \
+    EFI_ACPI_CREATOR_ID,            /* UINT32  CreatorId */       \
+    EFI_ACPI_CREATOR_REVISION       /* UINT32  CreatorRevision */ \
+  }
+
+#define EFI_ACPI_6_0_GIC_REDISTRIBUTOR_INIT(RedisRegionAddr, RedisDiscLength) \
+  {                                                                           \
+    EFI_ACPI_6_0_GICR,                                                        \
+    sizeof (EFI_ACPI_6_0_GICR_STRUCTURE),                                     \
+    0,                                                                        \
+    RedisRegionAddr,                                                          \
+    RedisDiscLength                                                           \
+  }
+
+#define EFI_ACPI_6_0_GIC_ITS_FRAME_INIT(Id, PhysAddress)                      \
+  {                                                                           \
+    EFI_ACPI_6_0_GIC_ITS,                                                     \
+    sizeof (EFI_ACPI_6_0_GIC_ITS_STRUCTURE),                                  \
+    0,                                                                        \
+    Id,                                                                       \
+    PhysAddress,                                                              \
+    0                                                                         \
+  }
+
+#define SBSAQEMU_UART0_BASE              0x60000000
+
+#define SBSAQEMU_PCI_SEG0_CONFIG_BASE    0xf0000000
+#define SBSAQEMU_PCI_SEG0_BUSNUM_MIN     0x00
+#define SBSAQEMU_PCI_SEG0_BUSNUM_MAX     0xFF
+
+#endif
diff --git a/Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf b/Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf
new file mode 100644
index 0000000000..63d5754e16
--- /dev/null
+++ b/Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf
@@ -0,0 +1,47 @@
+## @file
+#
+#  ACPI table data and ASL sources required to boot the platform.
+#
+#  Copyright (c) 2014-2016, ARM Ltd. All rights reserved.
+#  Copyright (c) 2018, Linaro Ltd. All rights reserved.
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+  INF_VERSION                    = 0x0001001A
+  BASE_NAME                      = SbsaAcpiTables
+  FILE_GUID                      = 7E374E25-8E01-4FEE-87F2-390C23C606CD
+  MODULE_TYPE                    = USER_DEFINED
+  VERSION_STRING                 = 1.0
+
+[Sources]
+  AcpiTables.h
+  Dsdt.asl
+  Fadt.aslc
+  Madt.aslc
+  Gtdt.aslc
+  Spcr.aslc
+  Mcfg.aslc
+
+[Packages]
+  ArmPlatformPkg/ArmPlatformPkg.dec
+  ArmPkg/ArmPkg.dec
+  EmbeddedPkg/EmbeddedPkg.dec
+  MdePkg/MdePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+
+[FixedPcd]
+  gArmPlatformTokenSpaceGuid.PcdClusterCount
+  gArmPlatformTokenSpaceGuid.PcdCoreCount
+  gArmTokenSpaceGuid.PcdGicDistributorBase
+  gArmTokenSpaceGuid.PcdGicRedistributorsBase
+
+  gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum
+  gArmTokenSpaceGuid.PcdArmArchTimerIntrNum
+  gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum
+  gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum
+
+  gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemRevision
+  gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultCreatorRevision
diff --git a/Silicon/Qemu/SbsaQemu/AcpiTables/Dsdt.asl b/Silicon/Qemu/SbsaQemu/AcpiTables/Dsdt.asl
new file mode 100644
index 0000000000..d63e22dd6b
--- /dev/null
+++ b/Silicon/Qemu/SbsaQemu/AcpiTables/Dsdt.asl
@@ -0,0 +1,1400 @@
+/** @file
+  Differentiated System Description Table Fields (DSDT)
+
+  Copyright (c) 2014-2016, ARM Ltd. All rights reserved.<BR>
+  Copyright (c) 2018, Linaro Ltd. All rights reserved.<BR>
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "AcpiTables.h"
+
+DefinitionBlock ("DsdtTable.aml", "DSDT", 1, "LNRO", "SBSA",
+                 EFI_ACPI_OEM_REVISION) {
+  Scope (_SB) {
+    //
+    // A53x4 Processor declaration
+    //
+    Device (CP00) { // A53-0: Cluster 0, Cpu 0
+      Name (_HID, "ACPI0007")
+      Name (_UID, 0)
+    }
+
+    // UART PL011
+    Device (COM0) {
+      Name (_HID, "ARMH0011")
+      Name (_UID, Zero)
+      Name (_CRS, ResourceTemplate () {
+        Memory32Fixed (ReadWrite, 0x60000000, 0x00001000)
+        Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { 33 }
+      })
+    }
+
+    Device(AHC0) {
+      Name(_HID, "LNRO001E")
+      Name(_CLS, Package (3) {
+        0x01,
+        0x06,
+        0x01,
+      })
+      Name(_CCA, 1)
+      Name(_CRS, ResourceTemplate() {
+        Memory32Fixed(ReadWrite, 0x60100000, 0x1000)
+        Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 42 }
+      })
+    }
+
+    //
+    // USB EHCI Host Controller
+    //
+    Device(USB0){
+        Name(_HID, "LNRO0D20")
+        Name(_CID, "PNP0D20")
+
+        Method(_CRS, 0x0, Serialized){
+            Name(RBUF, ResourceTemplate(){
+                Memory32Fixed(ReadWrite, 0x60110000, 0x00010000)
+                Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 43 }
+            })
+            Return(RBUF)
+        }
+
+        //
+        // Root Hub
+        //
+        Device(RHUB){
+            Name(_ADR, 0x00000000)  // Address of Root Hub should be 0 as per ACPI 5.0 spec
+
+            //
+            // Ports connected to Root Hub
+            //
+            Device(HUB1){
+                Name(_ADR, 0x00000001)
+                Name(_UPC, Package(){
+                    0x00,       // Port is NOT connectable
+                    0xFF,       // Don't care
+                    0x00000000, // Reserved 0 must be zero
+                    0x00000000  // Reserved 1 must be zero
+                })
+
+                Device(PRT1){
+                    Name(_ADR, 0x00000001)
+                    Name(_UPC, Package(){
+                        0xFF,        // Port is connectable
+                        0x00,        // Port connector is A
+                        0x00000000,
+                        0x00000000
+                    })
+                    Name(_PLD, Package(){
+                        Buffer(0x10){
+                            0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+                            0x31, 0x1C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+                        }
+                    })
+                } // USB0_RHUB_HUB1_PRT1
+                Device(PRT2){
+                    Name(_ADR, 0x00000002)
+                    Name(_UPC, Package(){
+                        0xFF,        // Port is connectable
+                        0x00,        // Port connector is A
+                        0x00000000,
+                        0x00000000
+                    })
+                    Name(_PLD, Package(){
+                        Buffer(0x10){
+                            0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+                            0x31, 0x1C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+                        }
+                    })
+                } // USB0_RHUB_HUB1_PRT2
+
+                Device(PRT3){
+                    Name(_ADR, 0x00000003)
+                    Name(_UPC, Package(){
+                        0xFF,        // Port is connectable
+                        0x00,        // Port connector is A
+                        0x00000000,
+                        0x00000000
+                    })
+                    Name(_PLD, Package(){
+                        Buffer(0x10){
+                            0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+                            0x31, 0x1C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+                        }
+                    })
+                } // USB0_RHUB_HUB1_PRT3
+
+                Device(PRT4){
+                    Name(_ADR, 0x00000004)
+                    Name(_UPC, Package(){
+                        0xFF,        // Port is connectable
+                        0x00,        // Port connector is A
+                        0x00000000,
+                        0x00000000
+                    })
+                    Name(_PLD, Package(){
+                        Buffer(0x10){
+                            0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+                            0x31, 0x1C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+                        }
+                    })
+                } // USB0_RHUB_HUB1_PRT4
+            } // USB0_RHUB_HUB1
+        } // USB0_RHUB
+    } // USB0
+
+    Device(PCI0)
+    {
+      Name(_HID, EISAID("PNP0A08")) // PCI Express Root Bridge
+      Name(_CID, EISAID("PNP0A03")) // Compatible PCI Root Bridge
+      Name(_SEG, Zero) // PCI Segment Group number
+      Name(_BBN, Zero) // PCI Base Bus Number
+      Name(_ADR, Zero)
+      Name(_UID, "PCI0")
+      Name(_CCA, One)    // Initially mark the PCI coherent (for JunoR1)
+
+      Method(_CBA, 0, NotSerialized) {
+          return (0xf0000000)
+      }
+
+      Device (GSI0)
+      {
+        Name (_HID, "PNP0C0F" /* PCI Interrupt Link Device */)  // _HID: Hardware ID
+        Name (_UID, Zero)  // _UID: Unique ID
+        Name (_PRS, ResourceTemplate ()  // _PRS: Possible Resource Settings
+        {
+          Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+          {
+            0x00000023,
+          }
+        })
+        Name (_CRS, ResourceTemplate ()  // _CRS: Current Resource Settings
+        {
+          Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+          {
+            0x00000023,
+          }
+        })
+        Method (_SRS, 1, NotSerialized)  // _SRS: Set Resource Settings
+        {
+        }
+      }
+
+      Device (GSI1)
+      {
+        Name (_HID, "PNP0C0F" /* PCI Interrupt Link Device */)  // _HID: Hardware ID
+        Name (_UID, Zero)  // _UID: Unique ID
+        Name (_PRS, ResourceTemplate ()  // _PRS: Possible Resource Settings
+        {
+          Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+          {
+            0x00000024,
+          }
+        })
+        Name (_CRS, ResourceTemplate ()  // _CRS: Current Resource Settings
+        {
+          Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+          {
+            0x00000024,
+          }
+        })
+        Method (_SRS, 1, NotSerialized)  // _SRS: Set Resource Settings
+        {
+        }
+      }
+
+      Device (GSI2)
+      {
+        Name (_HID, "PNP0C0F" /* PCI Interrupt Link Device */)  // _HID: Hardware ID
+        Name (_UID, Zero)  // _UID: Unique ID
+        Name (_PRS, ResourceTemplate ()  // _PRS: Possible Resource Settings
+        {
+          Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+          {
+            0x00000025,
+          }
+        })
+        Name (_CRS, ResourceTemplate ()  // _CRS: Current Resource Settings
+        {
+          Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+          {
+            0x00000025,
+          }
+        })
+        Method (_SRS, 1, NotSerialized)  // _SRS: Set Resource Settings
+        {
+        }
+      }
+
+      Device (GSI3)
+      {
+        Name (_HID, "PNP0C0F" /* PCI Interrupt Link Device */)  // _HID: Hardware ID
+        Name (_UID, Zero)  // _UID: Unique ID
+        Name (_PRS, ResourceTemplate ()  // _PRS: Possible Resource Settings
+        {
+          Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+          {
+            0x00000026,
+          }
+        })
+        Name (_CRS, ResourceTemplate ()  // _CRS: Current Resource Settings
+        {
+          Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+          {
+            0x00000026,
+          }
+        })
+        Method (_SRS, 1, NotSerialized)  // _SRS: Set Resource Settings
+        {
+        }
+      }
+
+      Name (_PRT, Package ()  // _PRT: PCI Routing Table
+      {
+        Package ()
+        {
+            0x0000FFFF,
+            Zero,
+            GSI0,
+            Zero
+        },
+
+        Package ()
+        {
+            0x0000FFFF,
+            Zero,
+            GSI1,
+            Zero
+        },
+
+        Package ()
+        {
+            0x0000FFFF,
+            Zero,
+            GSI2,
+            Zero
+        },
+
+        Package ()
+        {
+            0x0000FFFF,
+            Zero,
+            GSI3,
+            Zero
+        },
+
+        Package (0x04)
+        {
+            0x0001FFFF,
+            Zero,
+            GSI1,
+            Zero
+        },
+
+        Package (0x04)
+        {
+            0x0001FFFF,
+            One,
+            GSI2,
+            Zero
+        },
+
+        Package (0x04)
+        {
+            0x0001FFFF,
+            0x02,
+            GSI3,
+            Zero
+        },
+
+        Package (0x04)
+        {
+            0x0001FFFF,
+            0x03,
+            GSI0,
+            Zero
+        },
+
+        Package (0x04)
+        {
+            0x0002FFFF,
+            Zero,
+            GSI2,
+            Zero
+        },
+
+        Package (0x04)
+        {
+            0x0002FFFF,
+            One,
+            GSI3,
+            Zero
+        },
+
+        Package (0x04)
+        {
+            0x0002FFFF,
+            0x02,
+            GSI0,
+            Zero
+        },
+
+        Package (0x04)
+        {
+            0x0002FFFF,
+            0x03,
+            GSI1,
+            Zero
+        },
+
+        Package (0x04)
+        {
+            0x0003FFFF,
+            Zero,
+            GSI3,
+            Zero
+        },
+
+        Package (0x04)
+        {
+            0x0003FFFF,
+            One,
+            GSI0,
+            Zero
+        },
+
+        Package (0x04)
+        {
+            0x0003FFFF,
+            0x02,
+            GSI1,
+            Zero
+        },
+
+        Package (0x04)
+        {
+            0x0003FFFF,
+            0x03,
+            GSI2,
+            Zero
+        },
+
+        Package (0x04)
+        {
+            0x0004FFFF,
+            Zero,
+            GSI0,
+            Zero
+        },
+
+        Package (0x04)
+        {
+            0x0004FFFF,
+            One,
+            GSI1,
+            Zero
+        },
+
+        Package (0x04)
+        {
+            0x0004FFFF,
+            0x02,
+            GSI2,
+            Zero
+        },
+
+        Package (0x04)
+        {
+            0x0004FFFF,
+            0x03,
+            GSI3,
+            Zero
+        },
+
+        Package (0x04)
+        {
+            0x0005FFFF,
+            Zero,
+            GSI1,
+            Zero
+        },
+
+        Package (0x04)
+        {
+            0x0005FFFF,
+            One,
+            GSI2,
+            Zero
+        },
+
+        Package (0x04)
+        {
+            0x0005FFFF,
+            0x02,
+            GSI3,
+            Zero
+        },
+
+        Package (0x04)
+        {
+            0x0005FFFF,
+            0x03,
+            GSI0,
+            Zero
+        },
+
+        Package (0x04)
+        {
+            0x0006FFFF,
+            Zero,
+            GSI2,
+            Zero
+        },
+
+        Package (0x04)
+        {
+            0x0006FFFF,
+            One,
+            GSI3,
+            Zero
+        },
+
+        Package (0x04)
+        {
+            0x0006FFFF,
+            0x02,
+            GSI0,
+            Zero
+        },
+
+        Package (0x04)
+        {
+            0x0006FFFF,
+            0x03,
+            GSI1,
+            Zero
+        },
+
+        Package (0x04)
+        {
+            0x0007FFFF,
+            Zero,
+            GSI3,
+            Zero
+        },
+
+        Package (0x04)
+        {
+            0x0007FFFF,
+            One,
+            GSI0,
+            Zero
+        },
+
+        Package (0x04)
+        {
+            0x0007FFFF,
+            0x02,
+            GSI1,
+            Zero
+        },
+
+        Package (0x04)
+        {
+            0x0007FFFF,
+            0x03,
+            GSI2,
+            Zero
+        },
+
+        Package (0x04)
+        {
+            0x0008FFFF,
+            Zero,
+            GSI0,
+            Zero
+        },
+
+        Package (0x04)
+        {
+            0x0008FFFF,
+            One,
+            GSI1,
+            Zero
+        },
+
+        Package (0x04)
+        {
+            0x0008FFFF,
+            0x02,
+            GSI2,
+            Zero
+        },
+
+        Package (0x04)
+        {
+            0x0008FFFF,
+            0x03,
+            GSI3,
+            Zero
+        },
+
+        Package (0x04)
+        {
+            0x0009FFFF,
+            Zero,
+            GSI1,
+            Zero
+        },
+
+        Package (0x04)
+        {
+            0x0009FFFF,
+            One,
+            GSI2,
+            Zero
+        },
+
+        Package (0x04)
+        {
+            0x0009FFFF,
+            0x02,
+            GSI3,
+            Zero
+        },
+
+        Package (0x04)
+        {
+            0x0009FFFF,
+            0x03,
+            GSI0,
+            Zero
+        },
+
+        Package (0x04)
+        {
+            0x000AFFFF,
+            Zero,
+            GSI2,
+            Zero
+        },
+
+        Package (0x04)
+        {
+            0x000AFFFF,
+            One,
+            GSI3,
+            Zero
+        },
+
+        Package (0x04)
+        {
+            0x000AFFFF,
+            0x02,
+            GSI0,
+            Zero
+        },
+
+        Package (0x04)
+        {
+            0x000AFFFF,
+            0x03,
+            GSI1,
+            Zero
+        },
+
+        Package (0x04)
+        {
+            0x000BFFFF,
+            Zero,
+            GSI3,
+            Zero
+        },
+
+        Package (0x04)
+        {
+            0x000BFFFF,
+            One,
+            GSI0,
+            Zero
+        },
+
+        Package (0x04)
+        {
+            0x000BFFFF,
+            0x02,
+            GSI1,
+            Zero
+        },
+
+        Package (0x04)
+        {
+            0x000BFFFF,
+            0x03,
+            GSI2,
+            Zero
+        },
+
+        Package (0x04)
+        {
+            0x000CFFFF,
+            Zero,
+            GSI0,
+            Zero
+        },
+
+        Package (0x04)
+        {
+            0x000CFFFF,
+            One,
+            GSI1,
+            Zero
+        },
+
+        Package (0x04)
+        {
+            0x000CFFFF,
+            0x02,
+            GSI2,
+            Zero
+        },
+
+        Package (0x04)
+        {
+            0x000CFFFF,
+            0x03,
+            GSI3,
+            Zero
+        },
+
+        Package (0x04)
+        {
+            0x000DFFFF,
+            Zero,
+            GSI1,
+            Zero
+        },
+
+        Package (0x04)
+        {
+            0x000DFFFF,
+            One,
+            GSI2,
+            Zero
+        },
+
+        Package (0x04)
+        {
+            0x000DFFFF,
+            0x02,
+            GSI3,
+            Zero
+        },
+
+        Package (0x04)
+        {
+            0x000DFFFF,
+            0x03,
+            GSI0,
+            Zero
+        },
+
+        Package (0x04)
+        {
+            0x000EFFFF,
+            Zero,
+            GSI2,
+            Zero
+        },
+
+        Package (0x04)
+        {
+            0x000EFFFF,
+            One,
+            GSI3,
+            Zero
+        },
+
+        Package (0x04)
+        {
+            0x000EFFFF,
+            0x02,
+            GSI0,
+            Zero
+        },
+
+        Package (0x04)
+        {
+            0x000EFFFF,
+            0x03,
+            GSI1,
+            Zero
+        },
+
+        Package (0x04)
+        {
+            0x000FFFFF,
+            Zero,
+            GSI3,
+            Zero
+        },
+
+        Package (0x04)
+        {
+            0x000FFFFF,
+            One,
+            GSI0,
+            Zero
+        },
+
+        Package (0x04)
+        {
+            0x000FFFFF,
+            0x02,
+            GSI1,
+            Zero
+        },
+
+        Package (0x04)
+        {
+            0x000FFFFF,
+            0x03,
+            GSI2,
+            Zero
+        },
+
+        Package (0x04)
+        {
+            0x0010FFFF,
+            Zero,
+            GSI0,
+            Zero
+        },
+
+        Package (0x04)
+        {
+            0x0010FFFF,
+            One,
+            GSI1,
+            Zero
+        },
+
+        Package (0x04)
+        {
+            0x0010FFFF,
+            0x02,
+            GSI2,
+            Zero
+        },
+
+        Package (0x04)
+        {
+            0x0010FFFF,
+            0x03,
+            GSI3,
+            Zero
+        },
+
+        Package (0x04)
+        {
+            0x0011FFFF,
+            Zero,
+            GSI1,
+            Zero
+        },
+
+        Package (0x04)
+        {
+            0x0011FFFF,
+            One,
+            GSI2,
+            Zero
+        },
+
+        Package (0x04)
+        {
+            0x0011FFFF,
+            0x02,
+            GSI3,
+            Zero
+        },
+
+        Package (0x04)
+        {
+            0x0011FFFF,
+            0x03,
+            GSI0,
+            Zero
+        },
+
+        Package (0x04)
+        {
+            0x0012FFFF,
+            Zero,
+            GSI2,
+            Zero
+        },
+
+        Package (0x04)
+        {
+            0x0012FFFF,
+            One,
+            GSI3,
+            Zero
+        },
+
+        Package (0x04)
+        {
+            0x0012FFFF,
+            0x02,
+            GSI0,
+            Zero
+        },
+
+        Package (0x04)
+        {
+            0x0012FFFF,
+            0x03,
+            GSI1,
+            Zero
+        },
+
+        Package (0x04)
+        {
+            0x0013FFFF,
+            Zero,
+            GSI3,
+            Zero
+        },
+
+        Package (0x04)
+        {
+            0x0013FFFF,
+            One,
+            GSI0,
+            Zero
+        },
+
+        Package (0x04)
+        {
+            0x0013FFFF,
+            0x02,
+            GSI1,
+            Zero
+        },
+
+        Package (0x04)
+        {
+            0x0013FFFF,
+            0x03,
+            GSI2,
+            Zero
+        },
+
+        Package (0x04)
+        {
+            0x0014FFFF,
+            Zero,
+            GSI0,
+            Zero
+        },
+
+        Package (0x04)
+        {
+            0x0014FFFF,
+            One,
+            GSI1,
+            Zero
+        },
+
+        Package (0x04)
+        {
+            0x0014FFFF,
+            0x02,
+            GSI2,
+            Zero
+        },
+
+        Package (0x04)
+        {
+            0x0014FFFF,
+            0x03,
+            GSI3,
+            Zero
+        },
+
+        Package (0x04)
+        {
+            0x0015FFFF,
+            Zero,
+            GSI1,
+            Zero
+        },
+
+        Package (0x04)
+        {
+            0x0015FFFF,
+            One,
+            GSI2,
+            Zero
+        },
+
+        Package (0x04)
+        {
+            0x0015FFFF,
+            0x02,
+            GSI3,
+            Zero
+        },
+
+        Package (0x04)
+        {
+            0x0015FFFF,
+            0x03,
+            GSI0,
+            Zero
+        },
+
+        Package (0x04)
+        {
+            0x0016FFFF,
+            Zero,
+            GSI2,
+            Zero
+        },
+
+        Package (0x04)
+        {
+            0x0016FFFF,
+            One,
+            GSI3,
+            Zero
+        },
+
+        Package (0x04)
+        {
+            0x0016FFFF,
+            0x02,
+            GSI0,
+            Zero
+        },
+
+        Package (0x04)
+        {
+            0x0016FFFF,
+            0x03,
+            GSI1,
+            Zero
+        },
+
+        Package (0x04)
+        {
+            0x0017FFFF,
+            Zero,
+            GSI3,
+            Zero
+        },
+
+        Package (0x04)
+        {
+            0x0017FFFF,
+            One,
+            GSI0,
+            Zero
+        },
+
+        Package (0x04)
+        {
+            0x0017FFFF,
+            0x02,
+            GSI1,
+            Zero
+        },
+
+        Package (0x04)
+        {
+            0x0017FFFF,
+            0x03,
+            GSI2,
+            Zero
+        },
+
+        Package (0x04)
+        {
+            0x0018FFFF,
+            Zero,
+            GSI0,
+            Zero
+        },
+
+        Package (0x04)
+        {
+            0x0018FFFF,
+            One,
+            GSI1,
+            Zero
+        },
+
+        Package (0x04)
+        {
+            0x0018FFFF,
+            0x02,
+            GSI2,
+            Zero
+        },
+
+        Package (0x04)
+        {
+            0x0018FFFF,
+            0x03,
+            GSI3,
+            Zero
+        },
+
+        Package (0x04)
+        {
+            0x0019FFFF,
+            Zero,
+            GSI1,
+            Zero
+        },
+
+        Package (0x04)
+        {
+            0x0019FFFF,
+            One,
+            GSI2,
+            Zero
+        },
+
+        Package (0x04)
+        {
+            0x0019FFFF,
+            0x02,
+            GSI3,
+            Zero
+        },
+
+        Package (0x04)
+        {
+            0x0019FFFF,
+            0x03,
+            GSI0,
+            Zero
+        },
+
+        Package (0x04)
+        {
+            0x001AFFFF,
+            Zero,
+            GSI2,
+            Zero
+        },
+
+        Package (0x04)
+        {
+            0x001AFFFF,
+            One,
+            GSI3,
+            Zero
+        },
+
+        Package (0x04)
+        {
+            0x001AFFFF,
+            0x02,
+            GSI0,
+            Zero
+        },
+
+        Package (0x04)
+        {
+            0x001AFFFF,
+            0x03,
+            GSI1,
+            Zero
+        },
+
+        Package (0x04)
+        {
+            0x001BFFFF,
+            Zero,
+            GSI3,
+            Zero
+        },
+
+        Package (0x04)
+        {
+            0x001BFFFF,
+            One,
+            GSI0,
+            Zero
+        },
+
+        Package (0x04)
+        {
+            0x001BFFFF,
+            0x02,
+            GSI1,
+            Zero
+        },
+
+        Package (0x04)
+        {
+            0x001BFFFF,
+            0x03,
+            GSI2,
+            Zero
+        },
+
+        Package (0x04)
+        {
+            0x001CFFFF,
+            Zero,
+            GSI0,
+            Zero
+        },
+
+        Package (0x04)
+        {
+            0x001CFFFF,
+            One,
+            GSI1,
+            Zero
+        },
+
+        Package (0x04)
+        {
+            0x001CFFFF,
+            0x02,
+            GSI2,
+            Zero
+        },
+
+        Package (0x04)
+        {
+            0x001CFFFF,
+            0x03,
+            GSI3,
+            Zero
+        },
+
+        Package (0x04)
+        {
+            0x001DFFFF,
+            Zero,
+            GSI1,
+            Zero
+        },
+
+        Package (0x04)
+        {
+            0x001DFFFF,
+            One,
+            GSI2,
+            Zero
+        },
+
+        Package (0x04)
+        {
+            0x001DFFFF,
+            0x02,
+            GSI3,
+            Zero
+        },
+
+        Package (0x04)
+        {
+            0x001DFFFF,
+            0x03,
+            GSI0,
+            Zero
+        },
+
+        Package (0x04)
+        {
+            0x001EFFFF,
+            Zero,
+            GSI2,
+            Zero
+        },
+
+        Package (0x04)
+        {
+            0x001EFFFF,
+            One,
+            GSI3,
+            Zero
+        },
+
+        Package (0x04)
+        {
+            0x001EFFFF,
+            0x02,
+            GSI0,
+            Zero
+        },
+
+        Package (0x04)
+        {
+            0x001EFFFF,
+            0x03,
+            GSI1,
+            Zero
+        },
+
+        Package (0x04)
+        {
+            0x001FFFFF,
+            Zero,
+            GSI3,
+            Zero
+        },
+
+        Package (0x04)
+        {
+            0x001FFFFF,
+            One,
+            GSI0,
+            Zero
+        },
+
+        Package (0x04)
+        {
+            0x001FFFFF,
+            0x02,
+            GSI1,
+            Zero
+        },
+
+        Package (0x04)
+        {
+            0x001FFFFF,
+            0x03,
+            GSI2,
+            Zero
+        },
+      })
+
+      // Root complex resources
+      Method (_CRS, 0, Serialized) {
+      Name (RBUF, ResourceTemplate () {
+        WordBusNumber ( // Bus numbers assigned to this root
+        ResourceProducer,
+        MinFixed, MaxFixed, PosDecode,
+        0,   // AddressGranularity
+        0,   // AddressMinimum - Minimum Bus Number
+        255, // AddressMaximum - Maximum Bus Number
+        0,   // AddressTranslation - Set to 0
+        256  // RangeLength - Number of Busses
+        )
+
+        DWordMemory ( // 32-bit BAR Windows
+          ResourceProducer, PosDecode,
+          MinFixed, MaxFixed,
+          Cacheable, ReadWrite,
+          0x00000000,                          // Granularity
+          0x80000000,                          // Min Base Address
+          0xEFFFFFFF,                          // Max Base Address
+          0x00000000,                          // Translate
+          0x70000000                           // Length
+          )
+
+        QWordMemory ( // 64-bit BAR Windows
+          ResourceProducer, PosDecode,
+          MinFixed, MaxFixed,
+          Cacheable, ReadWrite,
+          0x00000000,                          // Granularity
+          0x100000000,                        // Min Base Address
+          0xFFFFFFFFFF,                        // Max Base Address
+          0x00000000,                          // Translate
+          0xFF00000000                          // Length
+          )
+
+        DWordIo ( // IO window
+          ResourceProducer,
+          MinFixed,
+          MaxFixed,
+          PosDecode,
+          EntireRange,
+          0x00000000,                          // Granularity
+          0x00000000,                          // Min Base Address
+          0x0000ffff,                          // Max Base Address
+          0x7fff0000,                          // Translate
+          0x00010000,                          // Length
+          ,,,TypeTranslation
+          )
+        }) // Name(RBUF)
+
+        Return (RBUF)
+      } // Method(_CRS)
+
+      Device (RES0)
+      {
+        Name (_HID, "PNP0C02" /* PNP Motherboard Resources */)  // _HID: Hardware ID
+        Name (_CRS, ResourceTemplate ()  // _CRS: Current Resource Settings
+        {
+           QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
+           0x0000000000000000, // Granularity
+           0x00000000F0000000, // Range Minimum
+           0x00000000FFFFFFFF, // Range Maximum
+           0x0000000000000000, // Translation Offset
+           0x0000000010000000, // Length
+           ,, , AddressRangeMemory, TypeStatic)
+        })
+      }
+
+      //
+      // OS Control Handoff
+      //
+      Name(SUPP, Zero) // PCI _OSC Support Field value
+      Name(CTRL, Zero) // PCI _OSC Control Field value
+
+      /*
+        See [1] 6.2.10, [2] 4.5
+      */
+      Method(_OSC,4) {
+        // Check for proper UUID
+        If(LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) {
+          // Create DWord-adressable fields from the Capabilities Buffer
+          CreateDWordField(Arg3,0,CDW1)
+          CreateDWordField(Arg3,4,CDW2)
+          CreateDWordField(Arg3,8,CDW3)
+
+          // Save Capabilities DWord2 & 3
+          Store(CDW2,SUPP)
+          Store(CDW3,CTRL)
+
+          // Only allow native hot plug control if OS supports:
+          // * ASPM
+          // * Clock PM
+          // * MSI/MSI-X
+          If(LNotEqual(And(SUPP, 0x16), 0x16)) {
+            And(CTRL,0x1E,CTRL) // Mask bit 0 (and undefined bits)
+          }
+
+          // Always allow native PME, AER (no dependencies)
+
+          // Never allow SHPC (no SHPC controller in this system)
+          And(CTRL,0x1D,CTRL)
+
+          If(LNotEqual(Arg1,One)) {        // Unknown revision
+            Or(CDW1,0x08,CDW1)
+          }
+
+          If(LNotEqual(CDW3,CTRL)) {        // Capabilities bits were masked
+            Or(CDW1,0x10,CDW1)
+          }
+
+          // Update DWORD3 in the buffer
+          Store(CTRL,CDW3)
+          Return(Arg3)
+        } Else {
+          Or(CDW1,4,CDW1) // Unrecognized UUID
+          Return(Arg3)
+        }
+      } // End _OSC
+    }
+  } // Scope (_SB)
+}
diff --git a/Silicon/Qemu/SbsaQemu/AcpiTables/Fadt.aslc b/Silicon/Qemu/SbsaQemu/AcpiTables/Fadt.aslc
new file mode 100644
index 0000000000..a0ec22abce
--- /dev/null
+++ b/Silicon/Qemu/SbsaQemu/AcpiTables/Fadt.aslc
@@ -0,0 +1,85 @@
+/** @file
+*  Fixed ACPI Description Table (FADT)
+*
+*  Copyright (c) 2012 - 2016, ARM Limited. All rights reserved.
+*  Copyright (c) 2018, Linaro Limited. All rights reserved.
+*
+*  SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+**/
+
+#include <Library/AcpiLib.h>
+#include <IndustryStandard/Acpi.h>
+
+#include "AcpiTables.h"
+
+EFI_ACPI_6_0_FIXED_ACPI_DESCRIPTION_TABLE Fadt = {
+  __ACPI_HEADER (
+    EFI_ACPI_6_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE,
+    EFI_ACPI_6_0_FIXED_ACPI_DESCRIPTION_TABLE,
+    EFI_ACPI_6_0_FIXED_ACPI_DESCRIPTION_TABLE_REVISION
+  ),
+  0,                                            // UINT32     FirmwareCtrl
+  0,                                            // UINT32     Dsdt
+  EFI_ACPI_RESERVED_BYTE,                       // UINT8      Reserved0
+  EFI_ACPI_6_0_PM_PROFILE_ENTERPRISE_SERVER,    // UINT8      PreferredPmProfile
+  0,                                            // UINT16     SciInt
+  0,                                            // UINT32     SmiCmd
+  0,                                            // UINT8      AcpiEnable
+  0,                                            // UINT8      AcpiDisable
+  0,                                            // UINT8      S4BiosReq
+  0,                                            // UINT8      PstateCnt
+  0,                                            // UINT32     Pm1aEvtBlk
+  0,                                            // UINT32     Pm1bEvtBlk
+  0,                                            // UINT32     Pm1aCntBlk
+  0,                                            // UINT32     Pm1bCntBlk
+  0,                                            // UINT32     Pm2CntBlk
+  0,                                            // UINT32     PmTmrBlk
+  0,                                            // UINT32     Gpe0Blk
+  0,                                            // UINT32     Gpe1Blk
+  0,                                            // UINT8      Pm1EvtLen
+  0,                                            // UINT8      Pm1CntLen
+  0,                                            // UINT8      Pm2CntLen
+  0,                                            // UINT8      PmTmrLen
+  0,                                            // UINT8      Gpe0BlkLen
+  0,                                            // UINT8      Gpe1BlkLen
+  0,                                            // UINT8      Gpe1Base
+  0,                                            // UINT8      CstCnt
+  0,                                            // UINT16     PLvl2Lat
+  0,                                            // UINT16     PLvl3Lat
+  0,                                            // UINT16     FlushSize
+  0,                                            // UINT16     FlushStride
+  0,                                            // UINT8      DutyOffset
+  0,                                            // UINT8      DutyWidth
+  0,                                            // UINT8      DayAlrm
+  0,                                            // UINT8      MonAlrm
+  0,                                            // UINT8      Century
+  0,                                            // UINT16     IaPcBootArch
+  0,                                            // UINT8      Reserved1
+  EFI_ACPI_6_0_HW_REDUCED_ACPI |
+  EFI_ACPI_6_0_LOW_POWER_S0_IDLE_CAPABLE,       // UINT32     Flags
+  NULL_GAS,                                     // GAS        ResetReg
+  0,                                            // UINT8      ResetValue
+  EFI_ACPI_6_0_ARM_PSCI_COMPLIANT,              // UINT16     ArmBootArchFlags
+  EFI_ACPI_6_0_FIXED_ACPI_DESCRIPTION_TABLE_MINOR_REVISION,
+                                                // UINT8      MinorRevision
+  0,                                            // UINT64     XFirmwareCtrl
+  0,                                            // UINT64     XDsdt
+  NULL_GAS,                                     // GAS        XPm1aEvtBlk
+  NULL_GAS,                                     // GAS        XPm1bEvtBlk
+  NULL_GAS,                                     // GAS        XPm1aCntBlk
+  NULL_GAS,                                     // GAS        XPm1bCntBlk
+  NULL_GAS,                                     // GAS        XPm2CntBlk
+  NULL_GAS,                                     // GAS        XPmTmrBlk
+  NULL_GAS,                                     // GAS        XGpe0Blk
+  NULL_GAS,                                     // GAS        XGpe1Blk
+  NULL_GAS,                                     // GAS        SleepControlReg
+  NULL_GAS,                                     // GAS        SleepStatusReg
+  0                                             // UINT64     HypervisorVendorId
+};
+
+//
+// Reference the table being generated to prevent the optimizer
+// from removing the data structure from the executable
+//
+VOID* CONST ReferenceAcpiTable = &Fadt;
diff --git a/Silicon/Qemu/SbsaQemu/AcpiTables/Gtdt.aslc b/Silicon/Qemu/SbsaQemu/AcpiTables/Gtdt.aslc
new file mode 100644
index 0000000000..0053363d11
--- /dev/null
+++ b/Silicon/Qemu/SbsaQemu/AcpiTables/Gtdt.aslc
@@ -0,0 +1,71 @@
+/** @file
+*  Generic Timer Description Table (GTDT)
+*
+*  Copyright (c) 2012 - 2017, ARM Limited. All rights reserved.
+*  Copyrignt (c) 2020, Linaro Limited. All rights reserved.
+*
+*  SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+**/
+
+#include "AcpiTables.h"
+#include <Library/AcpiLib.h>
+#include <Library/PcdLib.h>
+#include <IndustryStandard/Acpi.h>
+
+#define GTDT_GLOBAL_FLAGS_MAPPED      EFI_ACPI_5_0_GTDT_GLOBAL_FLAG_MEMORY_MAPPED_BLOCK_PRESENT
+#define GTDT_GLOBAL_FLAGS_NOT_MAPPED  0
+#define GTDT_GLOBAL_FLAGS_EDGE        EFI_ACPI_5_0_GTDT_GLOBAL_FLAG_INTERRUPT_MODE
+#define GTDT_GLOBAL_FLAGS_LEVEL       0
+
+// Note: We could have a build flag that switches between memory mapped/non-memory mapped timer
+#ifdef SYSTEM_TIMER_BASE_ADDRESS
+  #define GTDT_GLOBAL_FLAGS             (GTDT_GLOBAL_FLAGS_MAPPED | GTDT_GLOBAL_FLAGS_LEVEL)
+#else
+  #define GTDT_GLOBAL_FLAGS             (GTDT_GLOBAL_FLAGS_NOT_MAPPED | GTDT_GLOBAL_FLAGS_LEVEL)
+  #define SYSTEM_TIMER_BASE_ADDRESS     0xFFFFFFFFFFFFFFFF
+#endif
+
+#define GTDT_TIMER_EDGE_TRIGGERED   EFI_ACPI_5_0_GTDT_TIMER_FLAG_TIMER_INTERRUPT_MODE
+#define GTDT_TIMER_LEVEL_TRIGGERED  0
+#define GTDT_TIMER_ACTIVE_LOW       EFI_ACPI_5_0_GTDT_TIMER_FLAG_TIMER_INTERRUPT_POLARITY
+#define GTDT_TIMER_ACTIVE_HIGH      0
+
+#define GTDT_GTIMER_FLAGS           (GTDT_TIMER_ACTIVE_LOW | GTDT_TIMER_LEVEL_TRIGGERED)
+
+  #pragma pack (1)
+
+  typedef struct {
+    EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE          Gtdt;
+  } GENERIC_TIMER_DESCRIPTION_TABLE;
+
+  #pragma pack ()
+
+  GENERIC_TIMER_DESCRIPTION_TABLE Gtdt = {
+    {
+      __ACPI_HEADER(
+        EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE_SIGNATURE,
+        GENERIC_TIMER_DESCRIPTION_TABLE,
+        EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE_REVISION
+      ),
+      SYSTEM_TIMER_BASE_ADDRESS,                    // UINT64  PhysicalAddress
+      0,                                            // UINT32  Reserved
+      FixedPcdGet32 (PcdArmArchTimerSecIntrNum),    // UINT32  SecurePL1TimerGSIV
+      GTDT_GTIMER_FLAGS,                            // UINT32  SecurePL1TimerFlags
+      FixedPcdGet32 (PcdArmArchTimerIntrNum),       // UINT32  NonSecurePL1TimerGSIV
+      GTDT_GTIMER_FLAGS,                            // UINT32  NonSecurePL1TimerFlags
+      FixedPcdGet32 (PcdArmArchTimerVirtIntrNum),   // UINT32  VirtualTimerGSIV
+      GTDT_GTIMER_FLAGS,                            // UINT32  VirtualTimerFlags
+      FixedPcdGet32 (PcdArmArchTimerHypIntrNum),    // UINT32  NonSecurePL2TimerGSIV
+      GTDT_GTIMER_FLAGS,                            // UINT32  NonSecurePL2TimerFlags
+      0xFFFFFFFFFFFFFFFF,                           // UINT64  CntReadBasePhysicalAddress
+      0,                                            // UINT32  PlatformTimerCount
+      0
+    },
+  };
+
+//
+// Reference the table being generated to prevent the optimizer from removing the
+// data structure from the executable
+//
+VOID* CONST ReferenceAcpiTable = &Gtdt;
diff --git a/Silicon/Qemu/SbsaQemu/AcpiTables/Madt.aslc b/Silicon/Qemu/SbsaQemu/AcpiTables/Madt.aslc
new file mode 100644
index 0000000000..7bec2d4ef3
--- /dev/null
+++ b/Silicon/Qemu/SbsaQemu/AcpiTables/Madt.aslc
@@ -0,0 +1,85 @@
+/** @file
+*  Multiple APIC Description Table (MADT)
+*
+*  Copyright (c) 2012 - 2016, ARM Limited. All rights reserved.
+*  Copyright (c) 2018, Linaro Limited. All rights reserved.
+*
+*  SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+**/
+
+#include <Library/AcpiLib.h>
+#include <Library/ArmLib.h>
+#include <Library/PcdLib.h>
+#include <IndustryStandard/Acpi.h>
+
+#include "AcpiTables.h"
+
+#define CORES           (FixedPcdGet32 (PcdClusterCount) * \
+                         FixedPcdGet32 (PcdCoreCount))
+//
+// Multiple APIC Description Table
+//
+#pragma pack (1)
+
+typedef struct {
+  EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER   Header;
+  EFI_ACPI_6_0_GIC_STRUCTURE                            GicInterfaces[CORES];
+  EFI_ACPI_6_0_GIC_DISTRIBUTOR_STRUCTURE                GicDistributor;
+  EFI_ACPI_6_0_GICR_STRUCTURE                           GicRedistributor;
+  EFI_ACPI_6_0_GIC_ITS_STRUCTURE                        GicIts;
+} EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE;
+
+#pragma pack ()
+
+EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = {
+  {
+    __ACPI_HEADER (
+      EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE,
+      EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE,
+      EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION
+    ),
+    //
+    // MADT specific fields
+    //
+    0, // LocalApicAddress
+    0, // Flags
+  },
+  {
+    // Format: EFI_ACPI_6_0_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Mpidr, Flags,
+    //                                          PmuIrq, GicBase, GicVBase,
+    //                                          GicHBase, GsivId, GicRBase)
+    // Note: The GIC Structure of the primary CPU must be the first entry
+    // (see note in 5.2.12.14 GICC Structure of ACPI v6.0).
+    EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A53-0
+        0, 0, GET_MPID(0, 0), EFI_ACPI_6_0_GIC_ENABLED, 23,
+        FixedPcdGet32 (PcdGicDistributorBase),
+        0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
+    EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A53-0
+        1, 1, GET_MPID(0, 1), EFI_ACPI_6_0_GIC_ENABLED, 23,
+        FixedPcdGet32 (PcdGicDistributorBase),
+        0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
+    EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A53-0
+        2, 2, GET_MPID(0, 2), EFI_ACPI_6_0_GIC_ENABLED, 23,
+        FixedPcdGet32 (PcdGicDistributorBase),
+        0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
+    EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A53-0
+        3, 3, GET_MPID(0, 3), EFI_ACPI_6_0_GIC_ENABLED, 23,
+        FixedPcdGet32 (PcdGicDistributorBase),
+        0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
+  },
+  // GIC Distributor Entry
+  EFI_ACPI_6_0_GIC_DISTRIBUTOR_INIT (0, FixedPcdGet32 (PcdGicDistributorBase),
+                                     0, 3),
+  // GIC Redistributor
+  EFI_ACPI_6_0_GIC_REDISTRIBUTOR_INIT (FixedPcdGet32 (PcdGicRedistributorsBase),
+                                       0x300000),
+  // GIC ITS
+  EFI_ACPI_6_0_GIC_ITS_FRAME_INIT(0, 0x30020000)
+};
+
+//
+// Reference the table being generated to prevent the optimizer
+// from removing the data structure from the executable
+//
+VOID* CONST ReferenceAcpiTable = &Madt;
diff --git a/Silicon/Qemu/SbsaQemu/AcpiTables/Mcfg.aslc b/Silicon/Qemu/SbsaQemu/AcpiTables/Mcfg.aslc
new file mode 100644
index 0000000000..26e1fd3bfe
--- /dev/null
+++ b/Silicon/Qemu/SbsaQemu/AcpiTables/Mcfg.aslc
@@ -0,0 +1,50 @@
+/** @file
+
+  ACPI Memory mapped configuration space base address Description Table (MCFG).
+  Implementation based on PCI Firmware Specification Revision 3.0 final draft,
+  downloadable at http://www.pcisig.com/home
+
+  Copyright (c) 2014 - 2016, AMD Inc. All rights reserved.
+  Copyright (c) 2018, Linaro Limited. All rights reserved.
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <IndustryStandard/Acpi61.h>
+#include <IndustryStandard/MemoryMappedConfigurationSpaceAccessTable.h>
+
+#include "AcpiTables.h"
+
+#pragma pack(push, 1)
+
+typedef struct {
+  EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_BASE_ADDRESS_TABLE_HEADER Header;
+  EFI_ACPI_MEMORY_MAPPED_ENHANCED_CONFIGURATION_SPACE_BASE_ADDRESS_ALLOCATION_STRUCTURE Structure[2];
+} EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_DESCRIPTION_TABLE;
+
+EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_DESCRIPTION_TABLE Mcfg = {
+  {
+    __ACPI_HEADER (EFI_ACPI_5_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ADDRESS_DESCRIPTION_TABLE_SIGNATURE,
+    EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_DESCRIPTION_TABLE,
+    EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_TABLE_REVISION),
+    EFI_ACPI_RESERVED_QWORD
+  },
+  {
+    {
+      SBSAQEMU_PCI_SEG0_CONFIG_BASE,
+      0,
+      SBSAQEMU_PCI_SEG0_BUSNUM_MIN,
+      SBSAQEMU_PCI_SEG0_BUSNUM_MAX,
+      EFI_ACPI_RESERVED_DWORD
+    }
+  }
+};
+
+#pragma pack(pop)
+
+//
+// Reference the table being generated to prevent the optimizer
+// from removing the data structure from the executable
+//
+VOID* CONST ReferenceAcpiTable = &Mcfg;
diff --git a/Silicon/Qemu/SbsaQemu/AcpiTables/Spcr.aslc b/Silicon/Qemu/SbsaQemu/AcpiTables/Spcr.aslc
new file mode 100644
index 0000000000..fc7098afd1
--- /dev/null
+++ b/Silicon/Qemu/SbsaQemu/AcpiTables/Spcr.aslc
@@ -0,0 +1,122 @@
+/** @file
+
+  Serial Port Console Redirection Table
+  (c) 2000 - 2014 Microsoft Corporation. All rights reserved.
+  http://go.microsoft.com/fwlink/?linkid=403368
+
+  Copyright (c) 2014 - 2016, AMD Inc. All rights reserved.
+  Copyright (c) 2018,2020 Linaro Ltd. All rights reserved.
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <IndustryStandard/Acpi61.h>
+#include <IndustryStandard/SerialPortConsoleRedirectionTable.h>
+
+#include "AcpiTables.h"
+
+#pragma pack(push, 1)
+
+STATIC EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE Spcr = {
+  //
+  // Header
+  //
+  __ACPI_HEADER (EFI_ACPI_5_0_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_SIGNATURE,
+                 EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE,
+                 2), /* New MS definition for PL011 support */
+  //
+  // InterfaceType
+  //
+  EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERFACE_TYPE_ARM_PL011_UART,
+  //
+  // Reserved[3]
+  //
+  { EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE },
+  //
+  // BaseAddress
+  //
+  {
+    EFI_ACPI_5_1_SYSTEM_MEMORY,
+    32,
+    0,
+    EFI_ACPI_5_1_DWORD,
+    SBSAQEMU_UART0_BASE
+  },
+  //
+  // InterruptType
+  //
+  EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERRUPT_TYPE_GIC,
+  //
+  // Irq
+  //
+  0,
+  //
+  // GlobalSystemInterrupt
+  //
+  33,
+  //
+  // BaudRate
+  //
+  EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_BAUD_RATE_115200,
+  //
+  // Parity
+  //
+  EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_PARITY_NO_PARITY,
+  //
+  // StopBits
+  //
+  EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_STOP_BITS_1,
+  //
+  // FlowControl
+  //
+  0,
+  //
+  // TerminalType
+  //
+  EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_TERMINAL_TYPE_ANSI,
+  //
+  // Language
+  //
+  EFI_ACPI_RESERVED_BYTE,
+  //
+  // PciDeviceId
+  //
+  0xFFFF,
+  //
+  // PciVendorId
+  //
+  0xFFFF,
+  //
+  // PciBusNumber
+  //
+  0x00,
+  //
+  // PciDeviceNumber
+  //
+  0x00,
+  //
+  // PciFunctionNumber
+  //
+  0x00,
+  //
+  // PciFlags
+  //
+  0,
+  //
+  // PciSegment
+  //
+  0,
+  //
+  // Reserved2
+  //
+  EFI_ACPI_RESERVED_DWORD
+};
+
+#pragma pack(pop)
+
+//
+// Reference the table being generated to prevent the optimizer from removing
+// the data structure from the executable
+//
+VOID* CONST ReferenceAcpiTable = &Spcr;
diff --git a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuPlatformDxe/SbsaQemuPlatformDxe.c b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuPlatformDxe/SbsaQemuPlatformDxe.c
index b7270a07ab..f55dbdb453 100644
--- a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuPlatformDxe/SbsaQemuPlatformDxe.c
+++ b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuPlatformDxe/SbsaQemuPlatformDxe.c
@@ -51,5 +51,11 @@ InitializeSbsaQemuPlatformDxe (
     return Status;
   }
 
+  Status = gBS->InstallMultipleProtocolInterfaces (&ImageHandle,
+                  &gEdkiiPlatformHasAcpiGuid, NULL, NULL);
+  if (EFI_ERROR (Status)) {
+    DEBUG ((DEBUG_ERROR, "FAILED TO INSTALL gEDKIIPlatformHasAcpiGuid protocol\n"));
+  }
+
   return EFI_SUCCESS;
 }
diff --git a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuPlatformDxe/SbsaQemuPlatformDxe.inf b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuPlatformDxe/SbsaQemuPlatformDxe.inf
index 21d2135f6d..a50d563782 100644
--- a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuPlatformDxe/SbsaQemuPlatformDxe.inf
+++ b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuPlatformDxe/SbsaQemuPlatformDxe.inf
@@ -39,3 +39,13 @@
 [Depex]
   TRUE
 
+[Guids]
+  gEdkiiPlatformHasAcpiGuid
+
+[Protocols]
+  gEdkiiNonDiscoverableDeviceProtocolGuid         ## PRODUCES
+  gEfiAcpiTableProtocolGuid                       ## CONSUMES
+  gEfiPciIoProtocolGuid                           ## CONSUMES
+
+[FixedPcd]
+  gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemRevision
-- 
2.26.2


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Re: [edk2-devel] SbsaQemu: Initial support for static ACPI tables

Posted by Graeme Gregory 3 years, 10 months ago

On Mon, May 25, 2020 at 03:44:24AM +0530, Tanmay Jagdale wrote:
> Add the following static ACPI tables for the SBSA Qemu platform
>   - DSDT
>   - FADT
>   - GTDT
>   - MADT

Comment below on MADT

>   - MCFG
>   - SPCR
> 
> Currently we support 4 CPUs.
> 
> Co-authored-by: Graeme Gregory <graeme.gregory@linaro.org>
> Co-authored-by: Jonathan Cameron <jonathan.cameron@huawei.com>
> Co-authored-by: Tanmay Jagdale <tanmay.jagdale@linaro.org>
> Signed-off-by: Tanmay Jagdale <tanmay.jagdale@linaro.org>
> ---
>  Platform/Qemu/SbsaQemu/SbsaQemu.dsc           |   11 +-
>  Platform/Qemu/SbsaQemu/SbsaQemu.fdf           |   14 +
>  Silicon/Qemu/SbsaQemu/Acpi.dsc.inc            |   42 +
>  Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.h |   61 +
>  .../Qemu/SbsaQemu/AcpiTables/AcpiTables.inf   |   47 +
>  Silicon/Qemu/SbsaQemu/AcpiTables/Dsdt.asl     | 1400 +++++++++++++++++
>  Silicon/Qemu/SbsaQemu/AcpiTables/Fadt.aslc    |   85 +
>  Silicon/Qemu/SbsaQemu/AcpiTables/Gtdt.aslc    |   71 +
>  Silicon/Qemu/SbsaQemu/AcpiTables/Madt.aslc    |   85 +
>  Silicon/Qemu/SbsaQemu/AcpiTables/Mcfg.aslc    |   50 +
>  Silicon/Qemu/SbsaQemu/AcpiTables/Spcr.aslc    |  122 ++
>  .../SbsaQemuPlatformDxe/SbsaQemuPlatformDxe.c |    6 +
>  .../SbsaQemuPlatformDxe.inf                   |   10 +
>  13 files changed, 2003 insertions(+), 1 deletion(-)
>  create mode 100644 Silicon/Qemu/SbsaQemu/Acpi.dsc.inc
>  create mode 100644 Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.h
>  create mode 100644 Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf
>  create mode 100644 Silicon/Qemu/SbsaQemu/AcpiTables/Dsdt.asl
>  create mode 100644 Silicon/Qemu/SbsaQemu/AcpiTables/Fadt.aslc
>  create mode 100644 Silicon/Qemu/SbsaQemu/AcpiTables/Gtdt.aslc
>  create mode 100644 Silicon/Qemu/SbsaQemu/AcpiTables/Madt.aslc
>  create mode 100644 Silicon/Qemu/SbsaQemu/AcpiTables/Mcfg.aslc
>  create mode 100644 Silicon/Qemu/SbsaQemu/AcpiTables/Spcr.aslc
> 
> diff --git a/Platform/Qemu/SbsaQemu/SbsaQemu.dsc b/Platform/Qemu/SbsaQemu/SbsaQemu.dsc
> index 4db3ab4651..ac1398af8f 100644
> --- a/Platform/Qemu/SbsaQemu/SbsaQemu.dsc
> +++ b/Platform/Qemu/SbsaQemu/SbsaQemu.dsc
> @@ -300,6 +300,10 @@ DEFINE NETWORK_HTTP_BOOT_ENABLE       = FALSE
>    gEfiMdePkgTokenSpaceGuid.PcdPostCodePropertyMask|0
>    gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|320
>  
> +  # Core and Cluster Count
> +  gArmPlatformTokenSpaceGuid.PcdCoreCount|4
> +  gArmPlatformTokenSpaceGuid.PcdClusterCount|1
> +
>    # DEBUG_ASSERT_ENABLED       0x01
>    # DEBUG_PRINT_ENABLED        0x02
>    # DEBUG_CODE_ENABLED         0x04
> @@ -376,7 +380,6 @@ DEFINE NETWORK_HTTP_BOOT_ENABLE       = FALSE
>    #
>    gEfiMdeModulePkgTokenSpaceGuid.PcdSetNxForStack|TRUE
>  
> -  gArmPlatformTokenSpaceGuid.PcdCoreCount|1
>    gArmTokenSpaceGuid.PcdVFPEnabled|1
>  
>    # System Memory Base -- fixed
> @@ -516,6 +519,7 @@ DEFINE NETWORK_HTTP_BOOT_ENABLE       = FALSE
>    ShellPkg/Application/Shell/Shell.inf {
>      <LibraryClasses>
>        ShellCommandLib|ShellPkg/Library/UefiShellCommandLib/UefiShellCommandLib.inf
> +      NULL|ShellPkg/Library/UefiShellAcpiViewCommandLib/UefiShellAcpiViewCommandLib.inf
>        NULL|ShellPkg/Library/UefiShellLevel2CommandsLib/UefiShellLevel2CommandsLib.inf
>        NULL|ShellPkg/Library/UefiShellLevel1CommandsLib/UefiShellLevel1CommandsLib.inf
>        NULL|ShellPkg/Library/UefiShellLevel3CommandsLib/UefiShellLevel3CommandsLib.inf
> @@ -675,3 +679,8 @@ DEFINE NETWORK_HTTP_BOOT_ENABLE       = FALSE
>    MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf
>    MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf
>    MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf
> +
> +  #
> +  # ACPI Support
> +!include Silicon/Qemu/SbsaQemu/Acpi.dsc.inc
> +  MdeModulePkg/Universal/Acpi/BootGraphicsResourceTableDxe/BootGraphicsResourceTableDxe.inf
> diff --git a/Platform/Qemu/SbsaQemu/SbsaQemu.fdf b/Platform/Qemu/SbsaQemu/SbsaQemu.fdf
> index be7c78aceb..7f1a60e3ee 100644
> --- a/Platform/Qemu/SbsaQemu/SbsaQemu.fdf
> +++ b/Platform/Qemu/SbsaQemu/SbsaQemu.fdf
> @@ -227,6 +227,14 @@ READ_LOCK_STATUS   = TRUE
>    INF MdeModulePkg/Bus/Scsi/ScsiBusDxe/ScsiBusDxe.inf
>    INF MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDiskDxe.inf
>  
> +  #
> +  # ACPI support
> +  #
> +  INF MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf
> +  INF MdeModulePkg/Universal/Acpi/AcpiPlatformDxe/AcpiPlatformDxe.inf
> +  INF RuleOverride = ACPITABLE Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf
> +  INF MdeModulePkg/Universal/Acpi/BootGraphicsResourceTableDxe/BootGraphicsResourceTableDxe.inf
> +
>    #
>    # PCI support
>    #
> @@ -301,3 +309,9 @@ READ_LOCK_STATUS   = TRUE
>    }
>  
>  !include ArmVirtPkg/ArmVirtRules.fdf.inc
> +
> +[Rule.Common.USER_DEFINED.ACPITABLE]
> +  FILE FREEFORM = $(NAMED_GUID) {
> +    RAW ACPI               |.acpi
> +    RAW ASL                |.aml
> +  }
> diff --git a/Silicon/Qemu/SbsaQemu/Acpi.dsc.inc b/Silicon/Qemu/SbsaQemu/Acpi.dsc.inc
> new file mode 100644
> index 0000000000..76d0fac079
> --- /dev/null
> +++ b/Silicon/Qemu/SbsaQemu/Acpi.dsc.inc
> @@ -0,0 +1,42 @@
> +#
> +#  Copyright (c) 2018, Linaro Limited. All rights reserved.
> +#
> +#  SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +
> +################################################################################
> +#
> +# Pcd Section - list of all EDK II PCD Entries defined by this Platform
> +#
> +################################################################################
> +
> +[PcdsFeatureFlag]
> +  gEfiMdeModulePkgTokenSpaceGuid.PcdInstallAcpiSdtProtocol|TRUE
> +
> +[PcdsFixedAtBuild.common]
> +  gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemId|"LNRO  "
> +  gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemTableId|0x4153425341534253 # SBSA
> +  gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemRevision|0x20190910
> +  gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultCreatorId|0x4f524e4c # LNRO
> +  gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultCreatorRevision|1
> +
> +################################################################################
> +#
> +# Components Section - list of all EDK II Modules needed by this Platform
> +#
> +################################################################################
> +
> +[Components.common]
> +  #
> +  # ACPI support
> +  #
> +  MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf {
> +    <LibraryClasses>
> +      NULL|EmbeddedPkg/Library/PlatformHasAcpiLib/PlatformHasAcpiLib.inf
> +
> +    <PcdsFixedAtBuild>
> +      # support ACPI v5.0 or later
> +      gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiExposedTableVersions|0x20
> +  }
> +  MdeModulePkg/Universal/Acpi/AcpiPlatformDxe/AcpiPlatformDxe.inf
> +  Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf
> diff --git a/Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.h b/Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.h
> new file mode 100644
> index 0000000000..a30ade5a92
> --- /dev/null
> +++ b/Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.h
> @@ -0,0 +1,61 @@
> +/** @file
> +*
> +*  Copyright (c) 2013-2014, ARM Limited. All rights reserved.
> +*  Copyright (c) 2018, Linaro Limited. All rights reserved.
> +*
> +*  SPDX-License-Identifier: BSD-2-Clause-Patent
> +*
> +**/
> +
> +#ifndef __ACPITABLES_H__
> +#define __ACPITABLES_H__
> +
> +//
> +// ACPI table information used to initialize tables.
> +//
> +#define EFI_ACPI_OEM_ID           'L','N','R','O',' ',' '
> +#define EFI_ACPI_OEM_TABLE_ID     SIGNATURE_64('S','B','S','A','S','B','S','A')
> +#define EFI_ACPI_OEM_REVISION     FixedPcdGet32 (PcdAcpiDefaultOemRevision)
> +#define EFI_ACPI_CREATOR_ID       SIGNATURE_32('L','N','R','O')
> +#define EFI_ACPI_CREATOR_REVISION FixedPcdGet32 (PcdAcpiDefaultCreatorRevision)
> +
> +// A macro to initialise the common header part of EFI ACPI tables as defined by
> +// EFI_ACPI_DESCRIPTION_HEADER structure.
> +#define __ACPI_HEADER(Signature, Type, Revision) {                \
> +    Signature,                      /* UINT32  Signature */       \
> +    sizeof (Type),                  /* UINT32  Length */          \
> +    Revision,                       /* UINT8   Revision */        \
> +    0,                              /* UINT8   Checksum */        \
> +    { EFI_ACPI_OEM_ID },            /* UINT8   OemId[6] */        \
> +    EFI_ACPI_OEM_TABLE_ID,          /* UINT64  OemTableId */      \
> +    EFI_ACPI_OEM_REVISION,          /* UINT32  OemRevision */     \
> +    EFI_ACPI_CREATOR_ID,            /* UINT32  CreatorId */       \
> +    EFI_ACPI_CREATOR_REVISION       /* UINT32  CreatorRevision */ \
> +  }
> +
> +#define EFI_ACPI_6_0_GIC_REDISTRIBUTOR_INIT(RedisRegionAddr, RedisDiscLength) \
> +  {                                                                           \
> +    EFI_ACPI_6_0_GICR,                                                        \
> +    sizeof (EFI_ACPI_6_0_GICR_STRUCTURE),                                     \
> +    0,                                                                        \
> +    RedisRegionAddr,                                                          \
> +    RedisDiscLength                                                           \
> +  }
> +
> +#define EFI_ACPI_6_0_GIC_ITS_FRAME_INIT(Id, PhysAddress)                      \
> +  {                                                                           \
> +    EFI_ACPI_6_0_GIC_ITS,                                                     \
> +    sizeof (EFI_ACPI_6_0_GIC_ITS_STRUCTURE),                                  \
> +    0,                                                                        \
> +    Id,                                                                       \
> +    PhysAddress,                                                              \
> +    0                                                                         \
> +  }
> +
> +#define SBSAQEMU_UART0_BASE              0x60000000
> +
> +#define SBSAQEMU_PCI_SEG0_CONFIG_BASE    0xf0000000
> +#define SBSAQEMU_PCI_SEG0_BUSNUM_MIN     0x00
> +#define SBSAQEMU_PCI_SEG0_BUSNUM_MAX     0xFF
> +
> +#endif
> diff --git a/Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf b/Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf
> new file mode 100644
> index 0000000000..63d5754e16
> --- /dev/null
> +++ b/Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf
> @@ -0,0 +1,47 @@
> +## @file
> +#
> +#  ACPI table data and ASL sources required to boot the platform.
> +#
> +#  Copyright (c) 2014-2016, ARM Ltd. All rights reserved.
> +#  Copyright (c) 2018, Linaro Ltd. All rights reserved.
> +#
> +#  SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +##
> +
> +[Defines]
> +  INF_VERSION                    = 0x0001001A
> +  BASE_NAME                      = SbsaAcpiTables
> +  FILE_GUID                      = 7E374E25-8E01-4FEE-87F2-390C23C606CD
> +  MODULE_TYPE                    = USER_DEFINED
> +  VERSION_STRING                 = 1.0
> +
> +[Sources]
> +  AcpiTables.h
> +  Dsdt.asl
> +  Fadt.aslc
> +  Madt.aslc
> +  Gtdt.aslc
> +  Spcr.aslc
> +  Mcfg.aslc
> +
> +[Packages]
> +  ArmPlatformPkg/ArmPlatformPkg.dec
> +  ArmPkg/ArmPkg.dec
> +  EmbeddedPkg/EmbeddedPkg.dec
> +  MdePkg/MdePkg.dec
> +  MdeModulePkg/MdeModulePkg.dec
> +
> +[FixedPcd]
> +  gArmPlatformTokenSpaceGuid.PcdClusterCount
> +  gArmPlatformTokenSpaceGuid.PcdCoreCount
> +  gArmTokenSpaceGuid.PcdGicDistributorBase
> +  gArmTokenSpaceGuid.PcdGicRedistributorsBase
> +
> +  gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum
> +  gArmTokenSpaceGuid.PcdArmArchTimerIntrNum
> +  gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum
> +  gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum
> +
> +  gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemRevision
> +  gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultCreatorRevision
> diff --git a/Silicon/Qemu/SbsaQemu/AcpiTables/Dsdt.asl b/Silicon/Qemu/SbsaQemu/AcpiTables/Dsdt.asl
> new file mode 100644
> index 0000000000..d63e22dd6b
> --- /dev/null
> +++ b/Silicon/Qemu/SbsaQemu/AcpiTables/Dsdt.asl
> @@ -0,0 +1,1400 @@
> +/** @file
> +  Differentiated System Description Table Fields (DSDT)
> +
> +  Copyright (c) 2014-2016, ARM Ltd. All rights reserved.<BR>
> +  Copyright (c) 2018, Linaro Ltd. All rights reserved.<BR>
> +
> +  SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +**/
> +
> +#include "AcpiTables.h"
> +
> +DefinitionBlock ("DsdtTable.aml", "DSDT", 1, "LNRO", "SBSA",
> +                 EFI_ACPI_OEM_REVISION) {
> +  Scope (_SB) {
> +    //
> +    // A53x4 Processor declaration
> +    //
> +    Device (CP00) { // A53-0: Cluster 0, Cpu 0
> +      Name (_HID, "ACPI0007")
> +      Name (_UID, 0)
> +    }
> +
> +    // UART PL011
> +    Device (COM0) {
> +      Name (_HID, "ARMH0011")
> +      Name (_UID, Zero)
> +      Name (_CRS, ResourceTemplate () {
> +        Memory32Fixed (ReadWrite, 0x60000000, 0x00001000)
> +        Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { 33 }
> +      })
> +    }
> +
> +    Device(AHC0) {
> +      Name(_HID, "LNRO001E")
> +      Name(_CLS, Package (3) {
> +        0x01,
> +        0x06,
> +        0x01,
> +      })
> +      Name(_CCA, 1)
> +      Name(_CRS, ResourceTemplate() {
> +        Memory32Fixed(ReadWrite, 0x60100000, 0x1000)
> +        Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 42 }
> +      })
> +    }
> +
> +    //
> +    // USB EHCI Host Controller
> +    //
> +    Device(USB0){
> +        Name(_HID, "LNRO0D20")
> +        Name(_CID, "PNP0D20")
> +
> +        Method(_CRS, 0x0, Serialized){
> +            Name(RBUF, ResourceTemplate(){
> +                Memory32Fixed(ReadWrite, 0x60110000, 0x00010000)
> +                Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 43 }
> +            })
> +            Return(RBUF)
> +        }
> +
> +        //
> +        // Root Hub
> +        //
> +        Device(RHUB){
> +            Name(_ADR, 0x00000000)  // Address of Root Hub should be 0 as per ACPI 5.0 spec
> +
> +            //
> +            // Ports connected to Root Hub
> +            //
> +            Device(HUB1){
> +                Name(_ADR, 0x00000001)
> +                Name(_UPC, Package(){
> +                    0x00,       // Port is NOT connectable
> +                    0xFF,       // Don't care
> +                    0x00000000, // Reserved 0 must be zero
> +                    0x00000000  // Reserved 1 must be zero
> +                })
> +
> +                Device(PRT1){
> +                    Name(_ADR, 0x00000001)
> +                    Name(_UPC, Package(){
> +                        0xFF,        // Port is connectable
> +                        0x00,        // Port connector is A
> +                        0x00000000,
> +                        0x00000000
> +                    })
> +                    Name(_PLD, Package(){
> +                        Buffer(0x10){
> +                            0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> +                            0x31, 0x1C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
> +                        }
> +                    })
> +                } // USB0_RHUB_HUB1_PRT1
> +                Device(PRT2){
> +                    Name(_ADR, 0x00000002)
> +                    Name(_UPC, Package(){
> +                        0xFF,        // Port is connectable
> +                        0x00,        // Port connector is A
> +                        0x00000000,
> +                        0x00000000
> +                    })
> +                    Name(_PLD, Package(){
> +                        Buffer(0x10){
> +                            0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> +                            0x31, 0x1C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
> +                        }
> +                    })
> +                } // USB0_RHUB_HUB1_PRT2
> +
> +                Device(PRT3){
> +                    Name(_ADR, 0x00000003)
> +                    Name(_UPC, Package(){
> +                        0xFF,        // Port is connectable
> +                        0x00,        // Port connector is A
> +                        0x00000000,
> +                        0x00000000
> +                    })
> +                    Name(_PLD, Package(){
> +                        Buffer(0x10){
> +                            0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> +                            0x31, 0x1C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
> +                        }
> +                    })
> +                } // USB0_RHUB_HUB1_PRT3
> +
> +                Device(PRT4){
> +                    Name(_ADR, 0x00000004)
> +                    Name(_UPC, Package(){
> +                        0xFF,        // Port is connectable
> +                        0x00,        // Port connector is A
> +                        0x00000000,
> +                        0x00000000
> +                    })
> +                    Name(_PLD, Package(){
> +                        Buffer(0x10){
> +                            0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> +                            0x31, 0x1C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
> +                        }
> +                    })
> +                } // USB0_RHUB_HUB1_PRT4
> +            } // USB0_RHUB_HUB1
> +        } // USB0_RHUB
> +    } // USB0
> +
> +    Device(PCI0)
> +    {
> +      Name(_HID, EISAID("PNP0A08")) // PCI Express Root Bridge
> +      Name(_CID, EISAID("PNP0A03")) // Compatible PCI Root Bridge
> +      Name(_SEG, Zero) // PCI Segment Group number
> +      Name(_BBN, Zero) // PCI Base Bus Number
> +      Name(_ADR, Zero)
> +      Name(_UID, "PCI0")
> +      Name(_CCA, One)    // Initially mark the PCI coherent (for JunoR1)
> +
> +      Method(_CBA, 0, NotSerialized) {
> +          return (0xf0000000)
> +      }
> +
> +      Device (GSI0)
> +      {
> +        Name (_HID, "PNP0C0F" /* PCI Interrupt Link Device */)  // _HID: Hardware ID
> +        Name (_UID, Zero)  // _UID: Unique ID
> +        Name (_PRS, ResourceTemplate ()  // _PRS: Possible Resource Settings
> +        {
> +          Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
> +          {
> +            0x00000023,
> +          }
> +        })
> +        Name (_CRS, ResourceTemplate ()  // _CRS: Current Resource Settings
> +        {
> +          Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
> +          {
> +            0x00000023,
> +          }
> +        })
> +        Method (_SRS, 1, NotSerialized)  // _SRS: Set Resource Settings
> +        {
> +        }
> +      }
> +
> +      Device (GSI1)
> +      {
> +        Name (_HID, "PNP0C0F" /* PCI Interrupt Link Device */)  // _HID: Hardware ID
> +        Name (_UID, Zero)  // _UID: Unique ID
> +        Name (_PRS, ResourceTemplate ()  // _PRS: Possible Resource Settings
> +        {
> +          Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
> +          {
> +            0x00000024,
> +          }
> +        })
> +        Name (_CRS, ResourceTemplate ()  // _CRS: Current Resource Settings
> +        {
> +          Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
> +          {
> +            0x00000024,
> +          }
> +        })
> +        Method (_SRS, 1, NotSerialized)  // _SRS: Set Resource Settings
> +        {
> +        }
> +      }
> +
> +      Device (GSI2)
> +      {
> +        Name (_HID, "PNP0C0F" /* PCI Interrupt Link Device */)  // _HID: Hardware ID
> +        Name (_UID, Zero)  // _UID: Unique ID
> +        Name (_PRS, ResourceTemplate ()  // _PRS: Possible Resource Settings
> +        {
> +          Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
> +          {
> +            0x00000025,
> +          }
> +        })
> +        Name (_CRS, ResourceTemplate ()  // _CRS: Current Resource Settings
> +        {
> +          Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
> +          {
> +            0x00000025,
> +          }
> +        })
> +        Method (_SRS, 1, NotSerialized)  // _SRS: Set Resource Settings
> +        {
> +        }
> +      }
> +
> +      Device (GSI3)
> +      {
> +        Name (_HID, "PNP0C0F" /* PCI Interrupt Link Device */)  // _HID: Hardware ID
> +        Name (_UID, Zero)  // _UID: Unique ID
> +        Name (_PRS, ResourceTemplate ()  // _PRS: Possible Resource Settings
> +        {
> +          Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
> +          {
> +            0x00000026,
> +          }
> +        })
> +        Name (_CRS, ResourceTemplate ()  // _CRS: Current Resource Settings
> +        {
> +          Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
> +          {
> +            0x00000026,
> +          }
> +        })
> +        Method (_SRS, 1, NotSerialized)  // _SRS: Set Resource Settings
> +        {
> +        }
> +      }
> +
> +      Name (_PRT, Package ()  // _PRT: PCI Routing Table
> +      {
> +        Package ()
> +        {
> +            0x0000FFFF,
> +            Zero,
> +            GSI0,
> +            Zero
> +        },
> +
> +        Package ()
> +        {
> +            0x0000FFFF,
> +            Zero,
> +            GSI1,
> +            Zero
> +        },
> +
> +        Package ()
> +        {
> +            0x0000FFFF,
> +            Zero,
> +            GSI2,
> +            Zero
> +        },
> +
> +        Package ()
> +        {
> +            0x0000FFFF,
> +            Zero,
> +            GSI3,
> +            Zero
> +        },
> +
> +        Package (0x04)
> +        {
> +            0x0001FFFF,
> +            Zero,
> +            GSI1,
> +            Zero
> +        },
> +
> +        Package (0x04)
> +        {
> +            0x0001FFFF,
> +            One,
> +            GSI2,
> +            Zero
> +        },
> +
> +        Package (0x04)
> +        {
> +            0x0001FFFF,
> +            0x02,
> +            GSI3,
> +            Zero
> +        },
> +
> +        Package (0x04)
> +        {
> +            0x0001FFFF,
> +            0x03,
> +            GSI0,
> +            Zero
> +        },
> +
> +        Package (0x04)
> +        {
> +            0x0002FFFF,
> +            Zero,
> +            GSI2,
> +            Zero
> +        },
> +
> +        Package (0x04)
> +        {
> +            0x0002FFFF,
> +            One,
> +            GSI3,
> +            Zero
> +        },
> +
> +        Package (0x04)
> +        {
> +            0x0002FFFF,
> +            0x02,
> +            GSI0,
> +            Zero
> +        },
> +
> +        Package (0x04)
> +        {
> +            0x0002FFFF,
> +            0x03,
> +            GSI1,
> +            Zero
> +        },
> +
> +        Package (0x04)
> +        {
> +            0x0003FFFF,
> +            Zero,
> +            GSI3,
> +            Zero
> +        },
> +
> +        Package (0x04)
> +        {
> +            0x0003FFFF,
> +            One,
> +            GSI0,
> +            Zero
> +        },
> +
> +        Package (0x04)
> +        {
> +            0x0003FFFF,
> +            0x02,
> +            GSI1,
> +            Zero
> +        },
> +
> +        Package (0x04)
> +        {
> +            0x0003FFFF,
> +            0x03,
> +            GSI2,
> +            Zero
> +        },
> +
> +        Package (0x04)
> +        {
> +            0x0004FFFF,
> +            Zero,
> +            GSI0,
> +            Zero
> +        },
> +
> +        Package (0x04)
> +        {
> +            0x0004FFFF,
> +            One,
> +            GSI1,
> +            Zero
> +        },
> +
> +        Package (0x04)
> +        {
> +            0x0004FFFF,
> +            0x02,
> +            GSI2,
> +            Zero
> +        },
> +
> +        Package (0x04)
> +        {
> +            0x0004FFFF,
> +            0x03,
> +            GSI3,
> +            Zero
> +        },
> +
> +        Package (0x04)
> +        {
> +            0x0005FFFF,
> +            Zero,
> +            GSI1,
> +            Zero
> +        },
> +
> +        Package (0x04)
> +        {
> +            0x0005FFFF,
> +            One,
> +            GSI2,
> +            Zero
> +        },
> +
> +        Package (0x04)
> +        {
> +            0x0005FFFF,
> +            0x02,
> +            GSI3,
> +            Zero
> +        },
> +
> +        Package (0x04)
> +        {
> +            0x0005FFFF,
> +            0x03,
> +            GSI0,
> +            Zero
> +        },
> +
> +        Package (0x04)
> +        {
> +            0x0006FFFF,
> +            Zero,
> +            GSI2,
> +            Zero
> +        },
> +
> +        Package (0x04)
> +        {
> +            0x0006FFFF,
> +            One,
> +            GSI3,
> +            Zero
> +        },
> +
> +        Package (0x04)
> +        {
> +            0x0006FFFF,
> +            0x02,
> +            GSI0,
> +            Zero
> +        },
> +
> +        Package (0x04)
> +        {
> +            0x0006FFFF,
> +            0x03,
> +            GSI1,
> +            Zero
> +        },
> +
> +        Package (0x04)
> +        {
> +            0x0007FFFF,
> +            Zero,
> +            GSI3,
> +            Zero
> +        },
> +
> +        Package (0x04)
> +        {
> +            0x0007FFFF,
> +            One,
> +            GSI0,
> +            Zero
> +        },
> +
> +        Package (0x04)
> +        {
> +            0x0007FFFF,
> +            0x02,
> +            GSI1,
> +            Zero
> +        },
> +
> +        Package (0x04)
> +        {
> +            0x0007FFFF,
> +            0x03,
> +            GSI2,
> +            Zero
> +        },
> +
> +        Package (0x04)
> +        {
> +            0x0008FFFF,
> +            Zero,
> +            GSI0,
> +            Zero
> +        },
> +
> +        Package (0x04)
> +        {
> +            0x0008FFFF,
> +            One,
> +            GSI1,
> +            Zero
> +        },
> +
> +        Package (0x04)
> +        {
> +            0x0008FFFF,
> +            0x02,
> +            GSI2,
> +            Zero
> +        },
> +
> +        Package (0x04)
> +        {
> +            0x0008FFFF,
> +            0x03,
> +            GSI3,
> +            Zero
> +        },
> +
> +        Package (0x04)
> +        {
> +            0x0009FFFF,
> +            Zero,
> +            GSI1,
> +            Zero
> +        },
> +
> +        Package (0x04)
> +        {
> +            0x0009FFFF,
> +            One,
> +            GSI2,
> +            Zero
> +        },
> +
> +        Package (0x04)
> +        {
> +            0x0009FFFF,
> +            0x02,
> +            GSI3,
> +            Zero
> +        },
> +
> +        Package (0x04)
> +        {
> +            0x0009FFFF,
> +            0x03,
> +            GSI0,
> +            Zero
> +        },
> +
> +        Package (0x04)
> +        {
> +            0x000AFFFF,
> +            Zero,
> +            GSI2,
> +            Zero
> +        },
> +
> +        Package (0x04)
> +        {
> +            0x000AFFFF,
> +            One,
> +            GSI3,
> +            Zero
> +        },
> +
> +        Package (0x04)
> +        {
> +            0x000AFFFF,
> +            0x02,
> +            GSI0,
> +            Zero
> +        },
> +
> +        Package (0x04)
> +        {
> +            0x000AFFFF,
> +            0x03,
> +            GSI1,
> +            Zero
> +        },
> +
> +        Package (0x04)
> +        {
> +            0x000BFFFF,
> +            Zero,
> +            GSI3,
> +            Zero
> +        },
> +
> +        Package (0x04)
> +        {
> +            0x000BFFFF,
> +            One,
> +            GSI0,
> +            Zero
> +        },
> +
> +        Package (0x04)
> +        {
> +            0x000BFFFF,
> +            0x02,
> +            GSI1,
> +            Zero
> +        },
> +
> +        Package (0x04)
> +        {
> +            0x000BFFFF,
> +            0x03,
> +            GSI2,
> +            Zero
> +        },
> +
> +        Package (0x04)
> +        {
> +            0x000CFFFF,
> +            Zero,
> +            GSI0,
> +            Zero
> +        },
> +
> +        Package (0x04)
> +        {
> +            0x000CFFFF,
> +            One,
> +            GSI1,
> +            Zero
> +        },
> +
> +        Package (0x04)
> +        {
> +            0x000CFFFF,
> +            0x02,
> +            GSI2,
> +            Zero
> +        },
> +
> +        Package (0x04)
> +        {
> +            0x000CFFFF,
> +            0x03,
> +            GSI3,
> +            Zero
> +        },
> +
> +        Package (0x04)
> +        {
> +            0x000DFFFF,
> +            Zero,
> +            GSI1,
> +            Zero
> +        },
> +
> +        Package (0x04)
> +        {
> +            0x000DFFFF,
> +            One,
> +            GSI2,
> +            Zero
> +        },
> +
> +        Package (0x04)
> +        {
> +            0x000DFFFF,
> +            0x02,
> +            GSI3,
> +            Zero
> +        },
> +
> +        Package (0x04)
> +        {
> +            0x000DFFFF,
> +            0x03,
> +            GSI0,
> +            Zero
> +        },
> +
> +        Package (0x04)
> +        {
> +            0x000EFFFF,
> +            Zero,
> +            GSI2,
> +            Zero
> +        },
> +
> +        Package (0x04)
> +        {
> +            0x000EFFFF,
> +            One,
> +            GSI3,
> +            Zero
> +        },
> +
> +        Package (0x04)
> +        {
> +            0x000EFFFF,
> +            0x02,
> +            GSI0,
> +            Zero
> +        },
> +
> +        Package (0x04)
> +        {
> +            0x000EFFFF,
> +            0x03,
> +            GSI1,
> +            Zero
> +        },
> +
> +        Package (0x04)
> +        {
> +            0x000FFFFF,
> +            Zero,
> +            GSI3,
> +            Zero
> +        },
> +
> +        Package (0x04)
> +        {
> +            0x000FFFFF,
> +            One,
> +            GSI0,
> +            Zero
> +        },
> +
> +        Package (0x04)
> +        {
> +            0x000FFFFF,
> +            0x02,
> +            GSI1,
> +            Zero
> +        },
> +
> +        Package (0x04)
> +        {
> +            0x000FFFFF,
> +            0x03,
> +            GSI2,
> +            Zero
> +        },
> +
> +        Package (0x04)
> +        {
> +            0x0010FFFF,
> +            Zero,
> +            GSI0,
> +            Zero
> +        },
> +
> +        Package (0x04)
> +        {
> +            0x0010FFFF,
> +            One,
> +            GSI1,
> +            Zero
> +        },
> +
> +        Package (0x04)
> +        {
> +            0x0010FFFF,
> +            0x02,
> +            GSI2,
> +            Zero
> +        },
> +
> +        Package (0x04)
> +        {
> +            0x0010FFFF,
> +            0x03,
> +            GSI3,
> +            Zero
> +        },
> +
> +        Package (0x04)
> +        {
> +            0x0011FFFF,
> +            Zero,
> +            GSI1,
> +            Zero
> +        },
> +
> +        Package (0x04)
> +        {
> +            0x0011FFFF,
> +            One,
> +            GSI2,
> +            Zero
> +        },
> +
> +        Package (0x04)
> +        {
> +            0x0011FFFF,
> +            0x02,
> +            GSI3,
> +            Zero
> +        },
> +
> +        Package (0x04)
> +        {
> +            0x0011FFFF,
> +            0x03,
> +            GSI0,
> +            Zero
> +        },
> +
> +        Package (0x04)
> +        {
> +            0x0012FFFF,
> +            Zero,
> +            GSI2,
> +            Zero
> +        },
> +
> +        Package (0x04)
> +        {
> +            0x0012FFFF,
> +            One,
> +            GSI3,
> +            Zero
> +        },
> +
> +        Package (0x04)
> +        {
> +            0x0012FFFF,
> +            0x02,
> +            GSI0,
> +            Zero
> +        },
> +
> +        Package (0x04)
> +        {
> +            0x0012FFFF,
> +            0x03,
> +            GSI1,
> +            Zero
> +        },
> +
> +        Package (0x04)
> +        {
> +            0x0013FFFF,
> +            Zero,
> +            GSI3,
> +            Zero
> +        },
> +
> +        Package (0x04)
> +        {
> +            0x0013FFFF,
> +            One,
> +            GSI0,
> +            Zero
> +        },
> +
> +        Package (0x04)
> +        {
> +            0x0013FFFF,
> +            0x02,
> +            GSI1,
> +            Zero
> +        },
> +
> +        Package (0x04)
> +        {
> +            0x0013FFFF,
> +            0x03,
> +            GSI2,
> +            Zero
> +        },
> +
> +        Package (0x04)
> +        {
> +            0x0014FFFF,
> +            Zero,
> +            GSI0,
> +            Zero
> +        },
> +
> +        Package (0x04)
> +        {
> +            0x0014FFFF,
> +            One,
> +            GSI1,
> +            Zero
> +        },
> +
> +        Package (0x04)
> +        {
> +            0x0014FFFF,
> +            0x02,
> +            GSI2,
> +            Zero
> +        },
> +
> +        Package (0x04)
> +        {
> +            0x0014FFFF,
> +            0x03,
> +            GSI3,
> +            Zero
> +        },
> +
> +        Package (0x04)
> +        {
> +            0x0015FFFF,
> +            Zero,
> +            GSI1,
> +            Zero
> +        },
> +
> +        Package (0x04)
> +        {
> +            0x0015FFFF,
> +            One,
> +            GSI2,
> +            Zero
> +        },
> +
> +        Package (0x04)
> +        {
> +            0x0015FFFF,
> +            0x02,
> +            GSI3,
> +            Zero
> +        },
> +
> +        Package (0x04)
> +        {
> +            0x0015FFFF,
> +            0x03,
> +            GSI0,
> +            Zero
> +        },
> +
> +        Package (0x04)
> +        {
> +            0x0016FFFF,
> +            Zero,
> +            GSI2,
> +            Zero
> +        },
> +
> +        Package (0x04)
> +        {
> +            0x0016FFFF,
> +            One,
> +            GSI3,
> +            Zero
> +        },
> +
> +        Package (0x04)
> +        {
> +            0x0016FFFF,
> +            0x02,
> +            GSI0,
> +            Zero
> +        },
> +
> +        Package (0x04)
> +        {
> +            0x0016FFFF,
> +            0x03,
> +            GSI1,
> +            Zero
> +        },
> +
> +        Package (0x04)
> +        {
> +            0x0017FFFF,
> +            Zero,
> +            GSI3,
> +            Zero
> +        },
> +
> +        Package (0x04)
> +        {
> +            0x0017FFFF,
> +            One,
> +            GSI0,
> +            Zero
> +        },
> +
> +        Package (0x04)
> +        {
> +            0x0017FFFF,
> +            0x02,
> +            GSI1,
> +            Zero
> +        },
> +
> +        Package (0x04)
> +        {
> +            0x0017FFFF,
> +            0x03,
> +            GSI2,
> +            Zero
> +        },
> +
> +        Package (0x04)
> +        {
> +            0x0018FFFF,
> +            Zero,
> +            GSI0,
> +            Zero
> +        },
> +
> +        Package (0x04)
> +        {
> +            0x0018FFFF,
> +            One,
> +            GSI1,
> +            Zero
> +        },
> +
> +        Package (0x04)
> +        {
> +            0x0018FFFF,
> +            0x02,
> +            GSI2,
> +            Zero
> +        },
> +
> +        Package (0x04)
> +        {
> +            0x0018FFFF,
> +            0x03,
> +            GSI3,
> +            Zero
> +        },
> +
> +        Package (0x04)
> +        {
> +            0x0019FFFF,
> +            Zero,
> +            GSI1,
> +            Zero
> +        },
> +
> +        Package (0x04)
> +        {
> +            0x0019FFFF,
> +            One,
> +            GSI2,
> +            Zero
> +        },
> +
> +        Package (0x04)
> +        {
> +            0x0019FFFF,
> +            0x02,
> +            GSI3,
> +            Zero
> +        },
> +
> +        Package (0x04)
> +        {
> +            0x0019FFFF,
> +            0x03,
> +            GSI0,
> +            Zero
> +        },
> +
> +        Package (0x04)
> +        {
> +            0x001AFFFF,
> +            Zero,
> +            GSI2,
> +            Zero
> +        },
> +
> +        Package (0x04)
> +        {
> +            0x001AFFFF,
> +            One,
> +            GSI3,
> +            Zero
> +        },
> +
> +        Package (0x04)
> +        {
> +            0x001AFFFF,
> +            0x02,
> +            GSI0,
> +            Zero
> +        },
> +
> +        Package (0x04)
> +        {
> +            0x001AFFFF,
> +            0x03,
> +            GSI1,
> +            Zero
> +        },
> +
> +        Package (0x04)
> +        {
> +            0x001BFFFF,
> +            Zero,
> +            GSI3,
> +            Zero
> +        },
> +
> +        Package (0x04)
> +        {
> +            0x001BFFFF,
> +            One,
> +            GSI0,
> +            Zero
> +        },
> +
> +        Package (0x04)
> +        {
> +            0x001BFFFF,
> +            0x02,
> +            GSI1,
> +            Zero
> +        },
> +
> +        Package (0x04)
> +        {
> +            0x001BFFFF,
> +            0x03,
> +            GSI2,
> +            Zero
> +        },
> +
> +        Package (0x04)
> +        {
> +            0x001CFFFF,
> +            Zero,
> +            GSI0,
> +            Zero
> +        },
> +
> +        Package (0x04)
> +        {
> +            0x001CFFFF,
> +            One,
> +            GSI1,
> +            Zero
> +        },
> +
> +        Package (0x04)
> +        {
> +            0x001CFFFF,
> +            0x02,
> +            GSI2,
> +            Zero
> +        },
> +
> +        Package (0x04)
> +        {
> +            0x001CFFFF,
> +            0x03,
> +            GSI3,
> +            Zero
> +        },
> +
> +        Package (0x04)
> +        {
> +            0x001DFFFF,
> +            Zero,
> +            GSI1,
> +            Zero
> +        },
> +
> +        Package (0x04)
> +        {
> +            0x001DFFFF,
> +            One,
> +            GSI2,
> +            Zero
> +        },
> +
> +        Package (0x04)
> +        {
> +            0x001DFFFF,
> +            0x02,
> +            GSI3,
> +            Zero
> +        },
> +
> +        Package (0x04)
> +        {
> +            0x001DFFFF,
> +            0x03,
> +            GSI0,
> +            Zero
> +        },
> +
> +        Package (0x04)
> +        {
> +            0x001EFFFF,
> +            Zero,
> +            GSI2,
> +            Zero
> +        },
> +
> +        Package (0x04)
> +        {
> +            0x001EFFFF,
> +            One,
> +            GSI3,
> +            Zero
> +        },
> +
> +        Package (0x04)
> +        {
> +            0x001EFFFF,
> +            0x02,
> +            GSI0,
> +            Zero
> +        },
> +
> +        Package (0x04)
> +        {
> +            0x001EFFFF,
> +            0x03,
> +            GSI1,
> +            Zero
> +        },
> +
> +        Package (0x04)
> +        {
> +            0x001FFFFF,
> +            Zero,
> +            GSI3,
> +            Zero
> +        },
> +
> +        Package (0x04)
> +        {
> +            0x001FFFFF,
> +            One,
> +            GSI0,
> +            Zero
> +        },
> +
> +        Package (0x04)
> +        {
> +            0x001FFFFF,
> +            0x02,
> +            GSI1,
> +            Zero
> +        },
> +
> +        Package (0x04)
> +        {
> +            0x001FFFFF,
> +            0x03,
> +            GSI2,
> +            Zero
> +        },
> +      })
> +
> +      // Root complex resources
> +      Method (_CRS, 0, Serialized) {
> +      Name (RBUF, ResourceTemplate () {
> +        WordBusNumber ( // Bus numbers assigned to this root
> +        ResourceProducer,
> +        MinFixed, MaxFixed, PosDecode,
> +        0,   // AddressGranularity
> +        0,   // AddressMinimum - Minimum Bus Number
> +        255, // AddressMaximum - Maximum Bus Number
> +        0,   // AddressTranslation - Set to 0
> +        256  // RangeLength - Number of Busses
> +        )
> +
> +        DWordMemory ( // 32-bit BAR Windows
> +          ResourceProducer, PosDecode,
> +          MinFixed, MaxFixed,
> +          Cacheable, ReadWrite,
> +          0x00000000,                          // Granularity
> +          0x80000000,                          // Min Base Address
> +          0xEFFFFFFF,                          // Max Base Address
> +          0x00000000,                          // Translate
> +          0x70000000                           // Length
> +          )
> +
> +        QWordMemory ( // 64-bit BAR Windows
> +          ResourceProducer, PosDecode,
> +          MinFixed, MaxFixed,
> +          Cacheable, ReadWrite,
> +          0x00000000,                          // Granularity
> +          0x100000000,                        // Min Base Address
> +          0xFFFFFFFFFF,                        // Max Base Address
> +          0x00000000,                          // Translate
> +          0xFF00000000                          // Length
> +          )
> +
> +        DWordIo ( // IO window
> +          ResourceProducer,
> +          MinFixed,
> +          MaxFixed,
> +          PosDecode,
> +          EntireRange,
> +          0x00000000,                          // Granularity
> +          0x00000000,                          // Min Base Address
> +          0x0000ffff,                          // Max Base Address
> +          0x7fff0000,                          // Translate
> +          0x00010000,                          // Length
> +          ,,,TypeTranslation
> +          )
> +        }) // Name(RBUF)
> +
> +        Return (RBUF)
> +      } // Method(_CRS)
> +
> +      Device (RES0)
> +      {
> +        Name (_HID, "PNP0C02" /* PNP Motherboard Resources */)  // _HID: Hardware ID
> +        Name (_CRS, ResourceTemplate ()  // _CRS: Current Resource Settings
> +        {
> +           QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
> +           0x0000000000000000, // Granularity
> +           0x00000000F0000000, // Range Minimum
> +           0x00000000FFFFFFFF, // Range Maximum
> +           0x0000000000000000, // Translation Offset
> +           0x0000000010000000, // Length
> +           ,, , AddressRangeMemory, TypeStatic)
> +        })
> +      }
> +
> +      //
> +      // OS Control Handoff
> +      //
> +      Name(SUPP, Zero) // PCI _OSC Support Field value
> +      Name(CTRL, Zero) // PCI _OSC Control Field value
> +
> +      /*
> +        See [1] 6.2.10, [2] 4.5
> +      */
> +      Method(_OSC,4) {
> +        // Check for proper UUID
> +        If(LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) {
> +          // Create DWord-adressable fields from the Capabilities Buffer
> +          CreateDWordField(Arg3,0,CDW1)
> +          CreateDWordField(Arg3,4,CDW2)
> +          CreateDWordField(Arg3,8,CDW3)
> +
> +          // Save Capabilities DWord2 & 3
> +          Store(CDW2,SUPP)
> +          Store(CDW3,CTRL)
> +
> +          // Only allow native hot plug control if OS supports:
> +          // * ASPM
> +          // * Clock PM
> +          // * MSI/MSI-X
> +          If(LNotEqual(And(SUPP, 0x16), 0x16)) {
> +            And(CTRL,0x1E,CTRL) // Mask bit 0 (and undefined bits)
> +          }
> +
> +          // Always allow native PME, AER (no dependencies)
> +
> +          // Never allow SHPC (no SHPC controller in this system)
> +          And(CTRL,0x1D,CTRL)
> +
> +          If(LNotEqual(Arg1,One)) {        // Unknown revision
> +            Or(CDW1,0x08,CDW1)
> +          }
> +
> +          If(LNotEqual(CDW3,CTRL)) {        // Capabilities bits were masked
> +            Or(CDW1,0x10,CDW1)
> +          }
> +
> +          // Update DWORD3 in the buffer
> +          Store(CTRL,CDW3)
> +          Return(Arg3)
> +        } Else {
> +          Or(CDW1,4,CDW1) // Unrecognized UUID
> +          Return(Arg3)
> +        }
> +      } // End _OSC
> +    }
> +  } // Scope (_SB)
> +}
> diff --git a/Silicon/Qemu/SbsaQemu/AcpiTables/Fadt.aslc b/Silicon/Qemu/SbsaQemu/AcpiTables/Fadt.aslc
> new file mode 100644
> index 0000000000..a0ec22abce
> --- /dev/null
> +++ b/Silicon/Qemu/SbsaQemu/AcpiTables/Fadt.aslc
> @@ -0,0 +1,85 @@
> +/** @file
> +*  Fixed ACPI Description Table (FADT)
> +*
> +*  Copyright (c) 2012 - 2016, ARM Limited. All rights reserved.
> +*  Copyright (c) 2018, Linaro Limited. All rights reserved.
> +*
> +*  SPDX-License-Identifier: BSD-2-Clause-Patent
> +*
> +**/
> +
> +#include <Library/AcpiLib.h>
> +#include <IndustryStandard/Acpi.h>
> +
> +#include "AcpiTables.h"
> +
> +EFI_ACPI_6_0_FIXED_ACPI_DESCRIPTION_TABLE Fadt = {
> +  __ACPI_HEADER (
> +    EFI_ACPI_6_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE,
> +    EFI_ACPI_6_0_FIXED_ACPI_DESCRIPTION_TABLE,
> +    EFI_ACPI_6_0_FIXED_ACPI_DESCRIPTION_TABLE_REVISION
> +  ),
> +  0,                                            // UINT32     FirmwareCtrl
> +  0,                                            // UINT32     Dsdt
> +  EFI_ACPI_RESERVED_BYTE,                       // UINT8      Reserved0
> +  EFI_ACPI_6_0_PM_PROFILE_ENTERPRISE_SERVER,    // UINT8      PreferredPmProfile
> +  0,                                            // UINT16     SciInt
> +  0,                                            // UINT32     SmiCmd
> +  0,                                            // UINT8      AcpiEnable
> +  0,                                            // UINT8      AcpiDisable
> +  0,                                            // UINT8      S4BiosReq
> +  0,                                            // UINT8      PstateCnt
> +  0,                                            // UINT32     Pm1aEvtBlk
> +  0,                                            // UINT32     Pm1bEvtBlk
> +  0,                                            // UINT32     Pm1aCntBlk
> +  0,                                            // UINT32     Pm1bCntBlk
> +  0,                                            // UINT32     Pm2CntBlk
> +  0,                                            // UINT32     PmTmrBlk
> +  0,                                            // UINT32     Gpe0Blk
> +  0,                                            // UINT32     Gpe1Blk
> +  0,                                            // UINT8      Pm1EvtLen
> +  0,                                            // UINT8      Pm1CntLen
> +  0,                                            // UINT8      Pm2CntLen
> +  0,                                            // UINT8      PmTmrLen
> +  0,                                            // UINT8      Gpe0BlkLen
> +  0,                                            // UINT8      Gpe1BlkLen
> +  0,                                            // UINT8      Gpe1Base
> +  0,                                            // UINT8      CstCnt
> +  0,                                            // UINT16     PLvl2Lat
> +  0,                                            // UINT16     PLvl3Lat
> +  0,                                            // UINT16     FlushSize
> +  0,                                            // UINT16     FlushStride
> +  0,                                            // UINT8      DutyOffset
> +  0,                                            // UINT8      DutyWidth
> +  0,                                            // UINT8      DayAlrm
> +  0,                                            // UINT8      MonAlrm
> +  0,                                            // UINT8      Century
> +  0,                                            // UINT16     IaPcBootArch
> +  0,                                            // UINT8      Reserved1
> +  EFI_ACPI_6_0_HW_REDUCED_ACPI |
> +  EFI_ACPI_6_0_LOW_POWER_S0_IDLE_CAPABLE,       // UINT32     Flags
> +  NULL_GAS,                                     // GAS        ResetReg
> +  0,                                            // UINT8      ResetValue
> +  EFI_ACPI_6_0_ARM_PSCI_COMPLIANT,              // UINT16     ArmBootArchFlags
> +  EFI_ACPI_6_0_FIXED_ACPI_DESCRIPTION_TABLE_MINOR_REVISION,
> +                                                // UINT8      MinorRevision
> +  0,                                            // UINT64     XFirmwareCtrl
> +  0,                                            // UINT64     XDsdt
> +  NULL_GAS,                                     // GAS        XPm1aEvtBlk
> +  NULL_GAS,                                     // GAS        XPm1bEvtBlk
> +  NULL_GAS,                                     // GAS        XPm1aCntBlk
> +  NULL_GAS,                                     // GAS        XPm1bCntBlk
> +  NULL_GAS,                                     // GAS        XPm2CntBlk
> +  NULL_GAS,                                     // GAS        XPmTmrBlk
> +  NULL_GAS,                                     // GAS        XGpe0Blk
> +  NULL_GAS,                                     // GAS        XGpe1Blk
> +  NULL_GAS,                                     // GAS        SleepControlReg
> +  NULL_GAS,                                     // GAS        SleepStatusReg
> +  0                                             // UINT64     HypervisorVendorId
> +};
> +
> +//
> +// Reference the table being generated to prevent the optimizer
> +// from removing the data structure from the executable
> +//
> +VOID* CONST ReferenceAcpiTable = &Fadt;
> diff --git a/Silicon/Qemu/SbsaQemu/AcpiTables/Gtdt.aslc b/Silicon/Qemu/SbsaQemu/AcpiTables/Gtdt.aslc
> new file mode 100644
> index 0000000000..0053363d11
> --- /dev/null
> +++ b/Silicon/Qemu/SbsaQemu/AcpiTables/Gtdt.aslc
> @@ -0,0 +1,71 @@
> +/** @file
> +*  Generic Timer Description Table (GTDT)
> +*
> +*  Copyright (c) 2012 - 2017, ARM Limited. All rights reserved.
> +*  Copyrignt (c) 2020, Linaro Limited. All rights reserved.
> +*
> +*  SPDX-License-Identifier: BSD-2-Clause-Patent
> +*
> +**/
> +
> +#include "AcpiTables.h"
> +#include <Library/AcpiLib.h>
> +#include <Library/PcdLib.h>
> +#include <IndustryStandard/Acpi.h>
> +
> +#define GTDT_GLOBAL_FLAGS_MAPPED      EFI_ACPI_5_0_GTDT_GLOBAL_FLAG_MEMORY_MAPPED_BLOCK_PRESENT
> +#define GTDT_GLOBAL_FLAGS_NOT_MAPPED  0
> +#define GTDT_GLOBAL_FLAGS_EDGE        EFI_ACPI_5_0_GTDT_GLOBAL_FLAG_INTERRUPT_MODE
> +#define GTDT_GLOBAL_FLAGS_LEVEL       0
> +
> +// Note: We could have a build flag that switches between memory mapped/non-memory mapped timer
> +#ifdef SYSTEM_TIMER_BASE_ADDRESS
> +  #define GTDT_GLOBAL_FLAGS             (GTDT_GLOBAL_FLAGS_MAPPED | GTDT_GLOBAL_FLAGS_LEVEL)
> +#else
> +  #define GTDT_GLOBAL_FLAGS             (GTDT_GLOBAL_FLAGS_NOT_MAPPED | GTDT_GLOBAL_FLAGS_LEVEL)
> +  #define SYSTEM_TIMER_BASE_ADDRESS     0xFFFFFFFFFFFFFFFF
> +#endif
> +
> +#define GTDT_TIMER_EDGE_TRIGGERED   EFI_ACPI_5_0_GTDT_TIMER_FLAG_TIMER_INTERRUPT_MODE
> +#define GTDT_TIMER_LEVEL_TRIGGERED  0
> +#define GTDT_TIMER_ACTIVE_LOW       EFI_ACPI_5_0_GTDT_TIMER_FLAG_TIMER_INTERRUPT_POLARITY
> +#define GTDT_TIMER_ACTIVE_HIGH      0
> +
> +#define GTDT_GTIMER_FLAGS           (GTDT_TIMER_ACTIVE_LOW | GTDT_TIMER_LEVEL_TRIGGERED)
> +
> +  #pragma pack (1)
> +
> +  typedef struct {
> +    EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE          Gtdt;
> +  } GENERIC_TIMER_DESCRIPTION_TABLE;
> +
> +  #pragma pack ()
> +
> +  GENERIC_TIMER_DESCRIPTION_TABLE Gtdt = {
> +    {
> +      __ACPI_HEADER(
> +        EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE_SIGNATURE,
> +        GENERIC_TIMER_DESCRIPTION_TABLE,
> +        EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE_REVISION
> +      ),
> +      SYSTEM_TIMER_BASE_ADDRESS,                    // UINT64  PhysicalAddress
> +      0,                                            // UINT32  Reserved
> +      FixedPcdGet32 (PcdArmArchTimerSecIntrNum),    // UINT32  SecurePL1TimerGSIV
> +      GTDT_GTIMER_FLAGS,                            // UINT32  SecurePL1TimerFlags
> +      FixedPcdGet32 (PcdArmArchTimerIntrNum),       // UINT32  NonSecurePL1TimerGSIV
> +      GTDT_GTIMER_FLAGS,                            // UINT32  NonSecurePL1TimerFlags
> +      FixedPcdGet32 (PcdArmArchTimerVirtIntrNum),   // UINT32  VirtualTimerGSIV
> +      GTDT_GTIMER_FLAGS,                            // UINT32  VirtualTimerFlags
> +      FixedPcdGet32 (PcdArmArchTimerHypIntrNum),    // UINT32  NonSecurePL2TimerGSIV
> +      GTDT_GTIMER_FLAGS,                            // UINT32  NonSecurePL2TimerFlags
> +      0xFFFFFFFFFFFFFFFF,                           // UINT64  CntReadBasePhysicalAddress
> +      0,                                            // UINT32  PlatformTimerCount
> +      0
> +    },
> +  };
> +
> +//
> +// Reference the table being generated to prevent the optimizer from removing the
> +// data structure from the executable
> +//
> +VOID* CONST ReferenceAcpiTable = &Gtdt;
> diff --git a/Silicon/Qemu/SbsaQemu/AcpiTables/Madt.aslc b/Silicon/Qemu/SbsaQemu/AcpiTables/Madt.aslc
> new file mode 100644
> index 0000000000..7bec2d4ef3
> --- /dev/null
> +++ b/Silicon/Qemu/SbsaQemu/AcpiTables/Madt.aslc
> @@ -0,0 +1,85 @@
> +/** @file
> +*  Multiple APIC Description Table (MADT)
> +*
> +*  Copyright (c) 2012 - 2016, ARM Limited. All rights reserved.
> +*  Copyright (c) 2018, Linaro Limited. All rights reserved.
> +*
> +*  SPDX-License-Identifier: BSD-2-Clause-Patent
> +*
> +**/
> +
> +#include <Library/AcpiLib.h>
> +#include <Library/ArmLib.h>
> +#include <Library/PcdLib.h>
> +#include <IndustryStandard/Acpi.h>
> +
> +#include "AcpiTables.h"
> +
> +#define CORES           (FixedPcdGet32 (PcdClusterCount) * \
> +                         FixedPcdGet32 (PcdCoreCount))
> +//
> +// Multiple APIC Description Table
> +//
> +#pragma pack (1)
> +
> +typedef struct {
> +  EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER   Header;
> +  EFI_ACPI_6_0_GIC_STRUCTURE                            GicInterfaces[CORES];
> +  EFI_ACPI_6_0_GIC_DISTRIBUTOR_STRUCTURE                GicDistributor;
> +  EFI_ACPI_6_0_GICR_STRUCTURE                           GicRedistributor;
> +  EFI_ACPI_6_0_GIC_ITS_STRUCTURE                        GicIts;
> +} EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE;
> +
> +#pragma pack ()
> +
> +EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = {
> +  {
> +    __ACPI_HEADER (
> +      EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE,
> +      EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE,
> +      EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION
> +    ),
> +    //
> +    // MADT specific fields
> +    //
> +    0, // LocalApicAddress
> +    0, // Flags
> +  },
> +  {
> +    // Format: EFI_ACPI_6_0_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Mpidr, Flags,
> +    //                                          PmuIrq, GicBase, GicVBase,
> +    //                                          GicHBase, GsivId, GicRBase)
> +    // Note: The GIC Structure of the primary CPU must be the first entry
> +    // (see note in 5.2.12.14 GICC Structure of ACPI v6.0).
> +    EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A53-0
> +        0, 0, GET_MPID(0, 0), EFI_ACPI_6_0_GIC_ENABLED, 23,
> +        FixedPcdGet32 (PcdGicDistributorBase),
> +        0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),

Sometimes you stare at code so long you missed that this says A53 when
SbsaQemu obviously uses A57 emulated cores.

> +    EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A53-0
> +        1, 1, GET_MPID(0, 1), EFI_ACPI_6_0_GIC_ENABLED, 23,
> +        FixedPcdGet32 (PcdGicDistributorBase),
> +        0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
> +    EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A53-0
> +        2, 2, GET_MPID(0, 2), EFI_ACPI_6_0_GIC_ENABLED, 23,
> +        FixedPcdGet32 (PcdGicDistributorBase),
> +        0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
> +    EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A53-0
> +        3, 3, GET_MPID(0, 3), EFI_ACPI_6_0_GIC_ENABLED, 23,
> +        FixedPcdGet32 (PcdGicDistributorBase),
> +        0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
> +  },
> +  // GIC Distributor Entry
> +  EFI_ACPI_6_0_GIC_DISTRIBUTOR_INIT (0, FixedPcdGet32 (PcdGicDistributorBase),
> +                                     0, 3),
> +  // GIC Redistributor
> +  EFI_ACPI_6_0_GIC_REDISTRIBUTOR_INIT (FixedPcdGet32 (PcdGicRedistributorsBase),
> +                                       0x300000),
> +  // GIC ITS
> +  EFI_ACPI_6_0_GIC_ITS_FRAME_INIT(0, 0x30020000)
> +};
> +
> +//
> +// Reference the table being generated to prevent the optimizer
> +// from removing the data structure from the executable
> +//
> +VOID* CONST ReferenceAcpiTable = &Madt;
> diff --git a/Silicon/Qemu/SbsaQemu/AcpiTables/Mcfg.aslc b/Silicon/Qemu/SbsaQemu/AcpiTables/Mcfg.aslc
> new file mode 100644
> index 0000000000..26e1fd3bfe
> --- /dev/null
> +++ b/Silicon/Qemu/SbsaQemu/AcpiTables/Mcfg.aslc
> @@ -0,0 +1,50 @@
> +/** @file
> +
> +  ACPI Memory mapped configuration space base address Description Table (MCFG).
> +  Implementation based on PCI Firmware Specification Revision 3.0 final draft,
> +  downloadable at http://www.pcisig.com/home
> +
> +  Copyright (c) 2014 - 2016, AMD Inc. All rights reserved.
> +  Copyright (c) 2018, Linaro Limited. All rights reserved.
> +
> +  SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +**/
> +
> +#include <IndustryStandard/Acpi61.h>
> +#include <IndustryStandard/MemoryMappedConfigurationSpaceAccessTable.h>
> +
> +#include "AcpiTables.h"
> +
> +#pragma pack(push, 1)
> +
> +typedef struct {
> +  EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_BASE_ADDRESS_TABLE_HEADER Header;
> +  EFI_ACPI_MEMORY_MAPPED_ENHANCED_CONFIGURATION_SPACE_BASE_ADDRESS_ALLOCATION_STRUCTURE Structure[2];
> +} EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_DESCRIPTION_TABLE;
> +
> +EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_DESCRIPTION_TABLE Mcfg = {
> +  {
> +    __ACPI_HEADER (EFI_ACPI_5_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ADDRESS_DESCRIPTION_TABLE_SIGNATURE,
> +    EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_DESCRIPTION_TABLE,
> +    EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_TABLE_REVISION),
> +    EFI_ACPI_RESERVED_QWORD
> +  },
> +  {
> +    {
> +      SBSAQEMU_PCI_SEG0_CONFIG_BASE,
> +      0,
> +      SBSAQEMU_PCI_SEG0_BUSNUM_MIN,
> +      SBSAQEMU_PCI_SEG0_BUSNUM_MAX,
> +      EFI_ACPI_RESERVED_DWORD
> +    }
> +  }
> +};
> +
> +#pragma pack(pop)
> +
> +//
> +// Reference the table being generated to prevent the optimizer
> +// from removing the data structure from the executable
> +//
> +VOID* CONST ReferenceAcpiTable = &Mcfg;
> diff --git a/Silicon/Qemu/SbsaQemu/AcpiTables/Spcr.aslc b/Silicon/Qemu/SbsaQemu/AcpiTables/Spcr.aslc
> new file mode 100644
> index 0000000000..fc7098afd1
> --- /dev/null
> +++ b/Silicon/Qemu/SbsaQemu/AcpiTables/Spcr.aslc
> @@ -0,0 +1,122 @@
> +/** @file
> +
> +  Serial Port Console Redirection Table
> +  (c) 2000 - 2014 Microsoft Corporation. All rights reserved.
> +  http://go.microsoft.com/fwlink/?linkid=403368
> +
> +  Copyright (c) 2014 - 2016, AMD Inc. All rights reserved.
> +  Copyright (c) 2018,2020 Linaro Ltd. All rights reserved.
> +
> +  SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +**/
> +
> +#include <IndustryStandard/Acpi61.h>
> +#include <IndustryStandard/SerialPortConsoleRedirectionTable.h>
> +
> +#include "AcpiTables.h"
> +
> +#pragma pack(push, 1)
> +
> +STATIC EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE Spcr = {
> +  //
> +  // Header
> +  //
> +  __ACPI_HEADER (EFI_ACPI_5_0_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_SIGNATURE,
> +                 EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE,
> +                 2), /* New MS definition for PL011 support */
> +  //
> +  // InterfaceType
> +  //
> +  EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERFACE_TYPE_ARM_PL011_UART,
> +  //
> +  // Reserved[3]
> +  //
> +  { EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE },
> +  //
> +  // BaseAddress
> +  //
> +  {
> +    EFI_ACPI_5_1_SYSTEM_MEMORY,
> +    32,
> +    0,
> +    EFI_ACPI_5_1_DWORD,
> +    SBSAQEMU_UART0_BASE
> +  },
> +  //
> +  // InterruptType
> +  //
> +  EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERRUPT_TYPE_GIC,
> +  //
> +  // Irq
> +  //
> +  0,
> +  //
> +  // GlobalSystemInterrupt
> +  //
> +  33,
> +  //
> +  // BaudRate
> +  //
> +  EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_BAUD_RATE_115200,
> +  //
> +  // Parity
> +  //
> +  EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_PARITY_NO_PARITY,
> +  //
> +  // StopBits
> +  //
> +  EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_STOP_BITS_1,
> +  //
> +  // FlowControl
> +  //
> +  0,
> +  //
> +  // TerminalType
> +  //
> +  EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_TERMINAL_TYPE_ANSI,
> +  //
> +  // Language
> +  //
> +  EFI_ACPI_RESERVED_BYTE,
> +  //
> +  // PciDeviceId
> +  //
> +  0xFFFF,
> +  //
> +  // PciVendorId
> +  //
> +  0xFFFF,
> +  //
> +  // PciBusNumber
> +  //
> +  0x00,
> +  //
> +  // PciDeviceNumber
> +  //
> +  0x00,
> +  //
> +  // PciFunctionNumber
> +  //
> +  0x00,
> +  //
> +  // PciFlags
> +  //
> +  0,
> +  //
> +  // PciSegment
> +  //
> +  0,
> +  //
> +  // Reserved2
> +  //
> +  EFI_ACPI_RESERVED_DWORD
> +};
> +
> +#pragma pack(pop)
> +
> +//
> +// Reference the table being generated to prevent the optimizer from removing
> +// the data structure from the executable
> +//
> +VOID* CONST ReferenceAcpiTable = &Spcr;
> diff --git a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuPlatformDxe/SbsaQemuPlatformDxe.c b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuPlatformDxe/SbsaQemuPlatformDxe.c
> index b7270a07ab..f55dbdb453 100644
> --- a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuPlatformDxe/SbsaQemuPlatformDxe.c
> +++ b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuPlatformDxe/SbsaQemuPlatformDxe.c
> @@ -51,5 +51,11 @@ InitializeSbsaQemuPlatformDxe (
>      return Status;
>    }
>  
> +  Status = gBS->InstallMultipleProtocolInterfaces (&ImageHandle,
> +                  &gEdkiiPlatformHasAcpiGuid, NULL, NULL);
> +  if (EFI_ERROR (Status)) {
> +    DEBUG ((DEBUG_ERROR, "FAILED TO INSTALL gEDKIIPlatformHasAcpiGuid protocol\n"));
> +  }
> +
>    return EFI_SUCCESS;
>  }
> diff --git a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuPlatformDxe/SbsaQemuPlatformDxe.inf b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuPlatformDxe/SbsaQemuPlatformDxe.inf
> index 21d2135f6d..a50d563782 100644
> --- a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuPlatformDxe/SbsaQemuPlatformDxe.inf
> +++ b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuPlatformDxe/SbsaQemuPlatformDxe.inf
> @@ -39,3 +39,13 @@
>  [Depex]
>    TRUE
>  
> +[Guids]
> +  gEdkiiPlatformHasAcpiGuid
> +
> +[Protocols]
> +  gEdkiiNonDiscoverableDeviceProtocolGuid         ## PRODUCES
> +  gEfiAcpiTableProtocolGuid                       ## CONSUMES
> +  gEfiPciIoProtocolGuid                           ## CONSUMES
> +
> +[FixedPcd]
> +  gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemRevision
> -- 
> 2.26.2
> 

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Re: [edk2-devel] SbsaQemu: Initial support for static ACPI tables

Posted by Leif Lindholm 3 years, 10 months ago

On Tue, May 26, 2020 at 14:16:52 +0100, Graeme Gregory wrote:
> On Mon, May 25, 2020 at 03:44:24AM +0530, Tanmay Jagdale wrote:
> > Add the following static ACPI tables for the SBSA Qemu platform
> >   - DSDT
> >   - FADT
> >   - GTDT
> >   - MADT
> 
> Comment below on MADT

...

> > +  {
> > +    // Format: EFI_ACPI_6_0_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Mpidr, Flags,
> > +    //                                          PmuIrq, GicBase, GicVBase,
> > +    //                                          GicHBase, GsivId, GicRBase)
> > +    // Note: The GIC Structure of the primary CPU must be the first entry
> > +    // (see note in 5.2.12.14 GICC Structure of ACPI v6.0).
> > +    EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A53-0
> > +        0, 0, GET_MPID(0, 0), EFI_ACPI_6_0_GIC_ENABLED, 23,
> > +        FixedPcdGet32 (PcdGicDistributorBase),
> > +        0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
> 
> Sometimes you stare at code so long you missed that this says A53 when
> SbsaQemu obviously uses A57 emulated cores.

SbsaQemu *currently* uses A57 emulated cores.
However, this is only a comment.
I guess, for now, when we're still hard-coding stuff, CPU-# would be a
better comment than A53-#.
I don't have any other comments on this.

/
    Leif

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