MdePkg/Include/IndustryStandard/PciExpress40.h | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+)
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2598
All registers definition of DVSEC are defined as per the PCI Express Base
Specification 4.0 chapter 7.9.6.
Signed-off-by: Ashraf Javeed <ashraf.javeed@intel.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>
V2: fixed the comment section description for DVSEC definitions
---
MdePkg/Include/IndustryStandard/PciExpress40.h | 28 ++++++++++++++++++++++++++++
1 file changed, 28 insertions(+)
diff --git a/MdePkg/Include/IndustryStandard/PciExpress40.h b/MdePkg/Include/IndustryStandard/PciExpress40.h
index 9d9b272546..0564d72861 100644
--- a/MdePkg/Include/IndustryStandard/PciExpress40.h
+++ b/MdePkg/Include/IndustryStandard/PciExpress40.h
@@ -4,6 +4,7 @@ Support for the PCI Express 4.0 standard.
This header file may not define all structures. Please extend as required.
Copyright (c) 2018, American Megatrends, Inc. All rights reserved.<BR>
+Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
@@ -78,6 +79,33 @@ typedef struct {
} PCI_EXPRESS_EXTENDED_CAPABILITIES_PHYSICAL_LAYER_16_0;
///@}
+/// The Designated Vendor Specific Capability definitions
+/// Based on section 7.9.6 of PCI Express Base Specification 4.0.
+///@{
+typedef union {
+ struct {
+ UINT32 DvsecVendorId : 16; //bit 0..15
+ UINT32 DvsecRevision : 4; //bit 16..19
+ UINT32 DvsecLength : 12; //bit 20..31
+ }Bits;
+ UINT32 Uint32;
+}PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_1;
+
+typedef union {
+ struct {
+ UINT16 DvsecId : 16; //bit 0..15
+ }Bits;
+ UINT16 Uint16;
+}PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_2;
+
+typedef struct {
+ PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;
+ PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_1 DesignatedVendorSpecificHeader1;
+ PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_2 DesignatedVendorSpecificHeader2;
+ UINT8 DesignatedVendorSpecific[1];
+}PCI_EXPRESS_EXTENDED_CAPABILITIES_DESIGNATED_VENDOR_SPECIFIC;
+///@}
+
#pragma pack()
#endif
--
2.21.0.windows.1
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Reviewed-by: Zhiguang Liu <zhiguang.liu@intel.com>
-----Original Message-----
From: Javeed, Ashraf
Sent: Tuesday, March 17, 2020 4:04 PM
To: devel@edk2.groups.io
Cc: Kinney, Michael D <michael.d.kinney@intel.com>; Gao, Liming <liming.gao@intel.com>; Liu, Zhiguang <zhiguang.liu@intel.com>
Subject: [PATCH V2] MdePkg-PciExpress40.h: DVSEC definition missing
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2598
All registers definition of DVSEC are defined as per the PCI Express Base
Specification 4.0 chapter 7.9.6.
Signed-off-by: Ashraf Javeed <ashraf.javeed@intel.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>
V2: fixed the comment section description for DVSEC definitions
---
MdePkg/Include/IndustryStandard/PciExpress40.h | 28 ++++++++++++++++++++++++++++
1 file changed, 28 insertions(+)
diff --git a/MdePkg/Include/IndustryStandard/PciExpress40.h b/MdePkg/Include/IndustryStandard/PciExpress40.h
index 9d9b272546..0564d72861 100644
--- a/MdePkg/Include/IndustryStandard/PciExpress40.h
+++ b/MdePkg/Include/IndustryStandard/PciExpress40.h
@@ -4,6 +4,7 @@ Support for the PCI Express 4.0 standard.
This header file may not define all structures. Please extend as required.
Copyright (c) 2018, American Megatrends, Inc. All rights reserved.<BR>
+Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
@@ -78,6 +79,33 @@ typedef struct {
} PCI_EXPRESS_EXTENDED_CAPABILITIES_PHYSICAL_LAYER_16_0;
///@}
+/// The Designated Vendor Specific Capability definitions
+/// Based on section 7.9.6 of PCI Express Base Specification 4.0.
+///@{
+typedef union {
+ struct {
+ UINT32 DvsecVendorId : 16; //bit 0..15
+ UINT32 DvsecRevision : 4; //bit 16..19
+ UINT32 DvsecLength : 12; //bit 20..31
+ }Bits;
+ UINT32 Uint32;
+}PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_1;
+
+typedef union {
+ struct {
+ UINT16 DvsecId : 16; //bit 0..15
+ }Bits;
+ UINT16 Uint16;
+}PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_2;
+
+typedef struct {
+ PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;
+ PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_1 DesignatedVendorSpecificHeader1;
+ PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_2 DesignatedVendorSpecificHeader2;
+ UINT8 DesignatedVendorSpecific[1];
+}PCI_EXPRESS_EXTENDED_CAPABILITIES_DESIGNATED_VENDOR_SPECIFIC;
+///@}
+
#pragma pack()
#endif
--
2.21.0.windows.1
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Ashraf:
The change is good. Have you verified the build with this patch?
Reviewed-by: Liming Gao <liming.gao@intel.com>
Thanks
Liming
-----Original Message-----
From: Liu, Zhiguang <zhiguang.liu@intel.com>
Sent: 2020年3月17日 16:08
To: Javeed, Ashraf <ashraf.javeed@intel.com>; devel@edk2.groups.io
Cc: Kinney, Michael D <michael.d.kinney@intel.com>; Gao, Liming <liming.gao@intel.com>
Subject: RE: [PATCH V2] MdePkg-PciExpress40.h: DVSEC definition missing
Reviewed-by: Zhiguang Liu <zhiguang.liu@intel.com>
-----Original Message-----
From: Javeed, Ashraf
Sent: Tuesday, March 17, 2020 4:04 PM
To: devel@edk2.groups.io
Cc: Kinney, Michael D <michael.d.kinney@intel.com>; Gao, Liming <liming.gao@intel.com>; Liu, Zhiguang <zhiguang.liu@intel.com>
Subject: [PATCH V2] MdePkg-PciExpress40.h: DVSEC definition missing
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2598
All registers definition of DVSEC are defined as per the PCI Express Base Specification 4.0 chapter 7.9.6.
Signed-off-by: Ashraf Javeed <ashraf.javeed@intel.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>
V2: fixed the comment section description for DVSEC definitions
---
MdePkg/Include/IndustryStandard/PciExpress40.h | 28 ++++++++++++++++++++++++++++
1 file changed, 28 insertions(+)
diff --git a/MdePkg/Include/IndustryStandard/PciExpress40.h b/MdePkg/Include/IndustryStandard/PciExpress40.h
index 9d9b272546..0564d72861 100644
--- a/MdePkg/Include/IndustryStandard/PciExpress40.h
+++ b/MdePkg/Include/IndustryStandard/PciExpress40.h
@@ -4,6 +4,7 @@ Support for the PCI Express 4.0 standard.
This header file may not define all structures. Please extend as required.
Copyright (c) 2018, American Megatrends, Inc. All rights reserved.<BR>
+Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
@@ -78,6 +79,33 @@ typedef struct {
} PCI_EXPRESS_EXTENDED_CAPABILITIES_PHYSICAL_LAYER_16_0;
///@}
+/// The Designated Vendor Specific Capability definitions /// Based on
+section 7.9.6 of PCI Express Base Specification 4.0.
+///@{
+typedef union {
+ struct {
+ UINT32 DvsecVendorId : 16; //bit 0..15
+ UINT32 DvsecRevision : 4; //bit 16..19
+ UINT32 DvsecLength : 12; //bit 20..31
+ }Bits;
+ UINT32 Uint32;
+}PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_1;
+
+typedef union {
+ struct {
+ UINT16 DvsecId : 16; //bit 0..15
+ }Bits;
+ UINT16 Uint16;
+}PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_2;
+
+typedef struct {
+ PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;
+ PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_1 DesignatedVendorSpecificHeader1;
+ PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_2 DesignatedVendorSpecificHeader2;
+ UINT8 DesignatedVendorSpecific[1];
+}PCI_EXPRESS_EXTENDED_CAPABILITIES_DESIGNATED_VENDOR_SPECIFIC;
+///@}
+
#pragma pack()
#endif
--
2.21.0.windows.1
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Yes, I verified the build with this patch by directly referencing the new data types in a source file.
Thanks
Ashraf
> -----Original Message-----
> From: Gao, Liming <liming.gao@intel.com>
> Sent: Wednesday, March 18, 2020 8:11 AM
> To: Liu, Zhiguang <zhiguang.liu@intel.com>; Javeed, Ashraf
> <ashraf.javeed@intel.com>; devel@edk2.groups.io
> Cc: Kinney, Michael D <michael.d.kinney@intel.com>
> Subject: RE: [PATCH V2] MdePkg-PciExpress40.h: DVSEC definition missing
>
> Ashraf:
> The change is good. Have you verified the build with this patch?
>
> Reviewed-by: Liming Gao <liming.gao@intel.com>
>
> Thanks
> Liming
> -----Original Message-----
> From: Liu, Zhiguang <zhiguang.liu@intel.com>
> Sent: 2020年3月17日 16:08
> To: Javeed, Ashraf <ashraf.javeed@intel.com>; devel@edk2.groups.io
> Cc: Kinney, Michael D <michael.d.kinney@intel.com>; Gao, Liming
> <liming.gao@intel.com>
> Subject: RE: [PATCH V2] MdePkg-PciExpress40.h: DVSEC definition missing
>
> Reviewed-by: Zhiguang Liu <zhiguang.liu@intel.com>
>
> -----Original Message-----
> From: Javeed, Ashraf
> Sent: Tuesday, March 17, 2020 4:04 PM
> To: devel@edk2.groups.io
> Cc: Kinney, Michael D <michael.d.kinney@intel.com>; Gao, Liming
> <liming.gao@intel.com>; Liu, Zhiguang <zhiguang.liu@intel.com>
> Subject: [PATCH V2] MdePkg-PciExpress40.h: DVSEC definition missing
>
> BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2598
>
> All registers definition of DVSEC are defined as per the PCI Express Base
> Specification 4.0 chapter 7.9.6.
>
> Signed-off-by: Ashraf Javeed <ashraf.javeed@intel.com>
> Cc: Michael D Kinney <michael.d.kinney@intel.com>
> Cc: Liming Gao <liming.gao@intel.com>
> Cc: Zhiguang Liu <zhiguang.liu@intel.com>
>
> V2: fixed the comment section description for DVSEC definitions
> ---
> MdePkg/Include/IndustryStandard/PciExpress40.h | 28
> ++++++++++++++++++++++++++++
> 1 file changed, 28 insertions(+)
>
> diff --git a/MdePkg/Include/IndustryStandard/PciExpress40.h
> b/MdePkg/Include/IndustryStandard/PciExpress40.h
> index 9d9b272546..0564d72861 100644
> --- a/MdePkg/Include/IndustryStandard/PciExpress40.h
> +++ b/MdePkg/Include/IndustryStandard/PciExpress40.h
> @@ -4,6 +4,7 @@ Support for the PCI Express 4.0 standard.
> This header file may not define all structures. Please extend as required.
>
> Copyright (c) 2018, American Megatrends, Inc. All rights reserved.<BR>
> +Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
> SPDX-License-Identifier: BSD-2-Clause-Patent
>
> **/
> @@ -78,6 +79,33 @@ typedef struct {
> } PCI_EXPRESS_EXTENDED_CAPABILITIES_PHYSICAL_LAYER_16_0;
> ///@}
>
> +/// The Designated Vendor Specific Capability definitions /// Based on
> +section 7.9.6 of PCI Express Base Specification 4.0.
> +///@{
> +typedef union {
> + struct {
> + UINT32 DvsecVendorId : 16; //bit 0..15
> + UINT32 DvsecRevision : 4; //bit 16..19
> + UINT32 DvsecLength : 12; //bit 20..31
> + }Bits;
> + UINT32 Uint32;
> +}PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_1;
> +
> +typedef union {
> + struct {
> + UINT16 DvsecId : 16; //bit 0..15
> + }Bits;
> + UINT16 Uint16;
> +}PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_2;
> +
> +typedef struct {
> + PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;
> + PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_1
> DesignatedVendorSpecificHeader1;
> + PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_2
> DesignatedVendorSpecificHeader2;
> + UINT8 DesignatedVendorSpecific[1];
> +}PCI_EXPRESS_EXTENDED_CAPABILITIES_DESIGNATED_VENDOR_SPECIFIC;
> +///@}
> +
> #pragma pack()
>
> #endif
> --
> 2.21.0.windows.1
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That's enough.
> -----Original Message-----
> From: Javeed, Ashraf <ashraf.javeed@intel.com>
> Sent: Wednesday, March 18, 2020 12:51 PM
> To: Gao, Liming <liming.gao@intel.com>; Liu, Zhiguang <zhiguang.liu@intel.com>; devel@edk2.groups.io
> Cc: Kinney, Michael D <michael.d.kinney@intel.com>
> Subject: RE: [PATCH V2] MdePkg-PciExpress40.h: DVSEC definition missing
>
> Yes, I verified the build with this patch by directly referencing the new data types in a source file.
> Thanks
> Ashraf
>
> > -----Original Message-----
> > From: Gao, Liming <liming.gao@intel.com>
> > Sent: Wednesday, March 18, 2020 8:11 AM
> > To: Liu, Zhiguang <zhiguang.liu@intel.com>; Javeed, Ashraf
> > <ashraf.javeed@intel.com>; devel@edk2.groups.io
> > Cc: Kinney, Michael D <michael.d.kinney@intel.com>
> > Subject: RE: [PATCH V2] MdePkg-PciExpress40.h: DVSEC definition missing
> >
> > Ashraf:
> > The change is good. Have you verified the build with this patch?
> >
> > Reviewed-by: Liming Gao <liming.gao@intel.com>
> >
> > Thanks
> > Liming
> > -----Original Message-----
> > From: Liu, Zhiguang <zhiguang.liu@intel.com>
> > Sent: 2020年3月17日 16:08
> > To: Javeed, Ashraf <ashraf.javeed@intel.com>; devel@edk2.groups.io
> > Cc: Kinney, Michael D <michael.d.kinney@intel.com>; Gao, Liming
> > <liming.gao@intel.com>
> > Subject: RE: [PATCH V2] MdePkg-PciExpress40.h: DVSEC definition missing
> >
> > Reviewed-by: Zhiguang Liu <zhiguang.liu@intel.com>
> >
> > -----Original Message-----
> > From: Javeed, Ashraf
> > Sent: Tuesday, March 17, 2020 4:04 PM
> > To: devel@edk2.groups.io
> > Cc: Kinney, Michael D <michael.d.kinney@intel.com>; Gao, Liming
> > <liming.gao@intel.com>; Liu, Zhiguang <zhiguang.liu@intel.com>
> > Subject: [PATCH V2] MdePkg-PciExpress40.h: DVSEC definition missing
> >
> > BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2598
> >
> > All registers definition of DVSEC are defined as per the PCI Express Base
> > Specification 4.0 chapter 7.9.6.
> >
> > Signed-off-by: Ashraf Javeed <ashraf.javeed@intel.com>
> > Cc: Michael D Kinney <michael.d.kinney@intel.com>
> > Cc: Liming Gao <liming.gao@intel.com>
> > Cc: Zhiguang Liu <zhiguang.liu@intel.com>
> >
> > V2: fixed the comment section description for DVSEC definitions
> > ---
> > MdePkg/Include/IndustryStandard/PciExpress40.h | 28
> > ++++++++++++++++++++++++++++
> > 1 file changed, 28 insertions(+)
> >
> > diff --git a/MdePkg/Include/IndustryStandard/PciExpress40.h
> > b/MdePkg/Include/IndustryStandard/PciExpress40.h
> > index 9d9b272546..0564d72861 100644
> > --- a/MdePkg/Include/IndustryStandard/PciExpress40.h
> > +++ b/MdePkg/Include/IndustryStandard/PciExpress40.h
> > @@ -4,6 +4,7 @@ Support for the PCI Express 4.0 standard.
> > This header file may not define all structures. Please extend as required.
> >
> > Copyright (c) 2018, American Megatrends, Inc. All rights reserved.<BR>
> > +Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
> > SPDX-License-Identifier: BSD-2-Clause-Patent
> >
> > **/
> > @@ -78,6 +79,33 @@ typedef struct {
> > } PCI_EXPRESS_EXTENDED_CAPABILITIES_PHYSICAL_LAYER_16_0;
> > ///@}
> >
> > +/// The Designated Vendor Specific Capability definitions /// Based on
> > +section 7.9.6 of PCI Express Base Specification 4.0.
> > +///@{
> > +typedef union {
> > + struct {
> > + UINT32 DvsecVendorId : 16; //bit 0..15
> > + UINT32 DvsecRevision : 4; //bit 16..19
> > + UINT32 DvsecLength : 12; //bit 20..31
> > + }Bits;
> > + UINT32 Uint32;
> > +}PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_1;
> > +
> > +typedef union {
> > + struct {
> > + UINT16 DvsecId : 16; //bit 0..15
> > + }Bits;
> > + UINT16 Uint16;
> > +}PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_2;
> > +
> > +typedef struct {
> > + PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;
> > + PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_1
> > DesignatedVendorSpecificHeader1;
> > + PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_2
> > DesignatedVendorSpecificHeader2;
> > + UINT8 DesignatedVendorSpecific[1];
> > +}PCI_EXPRESS_EXTENDED_CAPABILITIES_DESIGNATED_VENDOR_SPECIFIC;
> > +///@}
> > +
> > #pragma pack()
> >
> > #endif
> > --
> > 2.21.0.windows.1
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I am sorry I just noticed this patch.
Is it better to have "DesignatedVendorSpecific[0]"?
This will make the sizeof (structure) more accurate.
> -----Original Message-----
> From: devel@edk2.groups.io <devel@edk2.groups.io> On Behalf Of Javeed,
> Ashraf
> Sent: Tuesday, March 17, 2020 4:04 PM
> To: devel@edk2.groups.io
> Cc: Kinney, Michael D <michael.d.kinney@intel.com>; Gao, Liming
> <liming.gao@intel.com>; Liu, Zhiguang <zhiguang.liu@intel.com>
> Subject: [edk2-devel] [PATCH V2] MdePkg-PciExpress40.h: DVSEC definition
> missing
>
> BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2598
>
> All registers definition of DVSEC are defined as per the PCI Express Base
> Specification 4.0 chapter 7.9.6.
>
> Signed-off-by: Ashraf Javeed <ashraf.javeed@intel.com>
> Cc: Michael D Kinney <michael.d.kinney@intel.com>
> Cc: Liming Gao <liming.gao@intel.com>
> Cc: Zhiguang Liu <zhiguang.liu@intel.com>
>
> V2: fixed the comment section description for DVSEC definitions
> ---
> MdePkg/Include/IndustryStandard/PciExpress40.h | 28
> ++++++++++++++++++++++++++++
> 1 file changed, 28 insertions(+)
>
> diff --git a/MdePkg/Include/IndustryStandard/PciExpress40.h
> b/MdePkg/Include/IndustryStandard/PciExpress40.h
> index 9d9b272546..0564d72861 100644
> --- a/MdePkg/Include/IndustryStandard/PciExpress40.h
> +++ b/MdePkg/Include/IndustryStandard/PciExpress40.h
> @@ -4,6 +4,7 @@ Support for the PCI Express 4.0 standard.
> This header file may not define all structures. Please extend as required.
>
> Copyright (c) 2018, American Megatrends, Inc. All rights reserved.<BR>
> +Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
> SPDX-License-Identifier: BSD-2-Clause-Patent
>
> **/
> @@ -78,6 +79,33 @@ typedef struct {
> } PCI_EXPRESS_EXTENDED_CAPABILITIES_PHYSICAL_LAYER_16_0;
> ///@}
>
> +/// The Designated Vendor Specific Capability definitions
> +/// Based on section 7.9.6 of PCI Express Base Specification 4.0.
> +///@{
> +typedef union {
> + struct {
> + UINT32 DvsecVendorId : 16; //bit 0..15
> + UINT32 DvsecRevision : 4; //bit 16..19
> + UINT32 DvsecLength : 12; //bit 20..31
> + }Bits;
> + UINT32 Uint32;
> +}PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_1;
> +
> +typedef union {
> + struct {
> + UINT16 DvsecId : 16; //bit 0..15
> + }Bits;
> + UINT16 Uint16;
> +}PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_2;
> +
> +typedef struct {
> + PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;
> + PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_1
> DesignatedVendorSpecificHeader1;
> + PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_2
> DesignatedVendorSpecificHeader2;
> + UINT8 DesignatedVendorSpecific[1];
> +}PCI_EXPRESS_EXTENDED_CAPABILITIES_DESIGNATED_VENDOR_SPECIFIC;
> +///@}
> +
> #pragma pack()
>
> #endif
> --
> 2.21.0.windows.1
>
>
>
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All the PCIe capability structures with the PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER; that has variable length features have been implemented in this way. I am counting around 12 structures which have been defined in the same way.
> -----Original Message-----
> From: Ni, Ray <ray.ni@intel.com>
> Sent: Thursday, March 19, 2020 2:30 PM
> To: Javeed, Ashraf <ashraf.javeed@intel.com>; Gao, Liming
> <liming.gao@intel.com>; Liu, Zhiguang <zhiguang.liu@intel.com>; Kinney,
> Michael D <michael.d.kinney@intel.com>
> Cc: devel@edk2.groups.io
> Subject: RE: [edk2-devel] [PATCH V2] MdePkg-PciExpress40.h: DVSEC
> definition missing
>
> I am sorry I just noticed this patch.
> Is it better to have "DesignatedVendorSpecific[0]"?
> This will make the sizeof (structure) more accurate.
>
> > -----Original Message-----
> > From: devel@edk2.groups.io <devel@edk2.groups.io> On Behalf Of
> Javeed,
> > Ashraf
> > Sent: Tuesday, March 17, 2020 4:04 PM
> > To: devel@edk2.groups.io
> > Cc: Kinney, Michael D <michael.d.kinney@intel.com>; Gao, Liming
> > <liming.gao@intel.com>; Liu, Zhiguang <zhiguang.liu@intel.com>
> > Subject: [edk2-devel] [PATCH V2] MdePkg-PciExpress40.h: DVSEC
> > definition missing
> >
> > BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2598
> >
> > All registers definition of DVSEC are defined as per the PCI Express
> > Base Specification 4.0 chapter 7.9.6.
> >
> > Signed-off-by: Ashraf Javeed <ashraf.javeed@intel.com>
> > Cc: Michael D Kinney <michael.d.kinney@intel.com>
> > Cc: Liming Gao <liming.gao@intel.com>
> > Cc: Zhiguang Liu <zhiguang.liu@intel.com>
> >
> > V2: fixed the comment section description for DVSEC definitions
> > ---
> > MdePkg/Include/IndustryStandard/PciExpress40.h | 28
> > ++++++++++++++++++++++++++++
> > 1 file changed, 28 insertions(+)
> >
> > diff --git a/MdePkg/Include/IndustryStandard/PciExpress40.h
> > b/MdePkg/Include/IndustryStandard/PciExpress40.h
> > index 9d9b272546..0564d72861 100644
> > --- a/MdePkg/Include/IndustryStandard/PciExpress40.h
> > +++ b/MdePkg/Include/IndustryStandard/PciExpress40.h
> > @@ -4,6 +4,7 @@ Support for the PCI Express 4.0 standard.
> > This header file may not define all structures. Please extend as required.
> >
> > Copyright (c) 2018, American Megatrends, Inc. All rights
> > reserved.<BR>
> > +Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
> > SPDX-License-Identifier: BSD-2-Clause-Patent
> >
> > **/
> > @@ -78,6 +79,33 @@ typedef struct {
> > } PCI_EXPRESS_EXTENDED_CAPABILITIES_PHYSICAL_LAYER_16_0;
> > ///@}
> >
> > +/// The Designated Vendor Specific Capability definitions /// Based
> > +on section 7.9.6 of PCI Express Base Specification 4.0.
> > +///@{
> > +typedef union {
> > + struct {
> > + UINT32 DvsecVendorId : 16; //bit 0..15
> > + UINT32 DvsecRevision : 4; //bit 16..19
> > + UINT32 DvsecLength : 12; //bit 20..31
> > + }Bits;
> > + UINT32 Uint32;
> > +}PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_1;
> > +
> > +typedef union {
> > + struct {
> > + UINT16 DvsecId : 16; //bit 0..15
> > + }Bits;
> > + UINT16 Uint16;
> > +}PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_2;
> > +
> > +typedef struct {
> > + PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;
> > + PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_1
> > DesignatedVendorSpecificHeader1;
> > + PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_2
> > DesignatedVendorSpecificHeader2;
> > + UINT8 DesignatedVendorSpecific[1];
> >
> +}PCI_EXPRESS_EXTENDED_CAPABILITIES_DESIGNATED_VENDOR_SPECIFIC;
> > +///@}
> > +
> > #pragma pack()
> >
> > #endif
> > --
> > 2.21.0.windows.1
> >
> >
> >
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I agree with you about that fact😊
These "[1]" was added 6 years ago when "[0]" still caused compilation failure.
Later, about 5 years ago, Mike enabled "[0]" with the below change in MdePkg/Include/Base.h:
//
// Disable warning when last field of data structure is a zero sized array.
//
#pragma warning ( disable : 4200 )
We cannot change these "[1]" to "[0]" because that would cause existing code that depends on
sizeof() result fails.
But for new code, it's encouraged to use "[0]".
Thanks,
Ray
> -----Original Message-----
> From: Javeed, Ashraf <ashraf.javeed@intel.com>
> Sent: Thursday, March 19, 2020 6:00 PM
> To: Ni, Ray <ray.ni@intel.com>; Gao, Liming <liming.gao@intel.com>; Liu, Zhiguang <zhiguang.liu@intel.com>; Kinney,
> Michael D <michael.d.kinney@intel.com>
> Cc: devel@edk2.groups.io
> Subject: RE: [edk2-devel] [PATCH V2] MdePkg-PciExpress40.h: DVSEC definition missing
>
> All the PCIe capability structures with the PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER; that has variable length
> features have been implemented in this way. I am counting around 12 structures which have been defined in the same
> way.
>
> > -----Original Message-----
> > From: Ni, Ray <ray.ni@intel.com>
> > Sent: Thursday, March 19, 2020 2:30 PM
> > To: Javeed, Ashraf <ashraf.javeed@intel.com>; Gao, Liming
> > <liming.gao@intel.com>; Liu, Zhiguang <zhiguang.liu@intel.com>; Kinney,
> > Michael D <michael.d.kinney@intel.com>
> > Cc: devel@edk2.groups.io
> > Subject: RE: [edk2-devel] [PATCH V2] MdePkg-PciExpress40.h: DVSEC
> > definition missing
> >
> > I am sorry I just noticed this patch.
> > Is it better to have "DesignatedVendorSpecific[0]"?
> > This will make the sizeof (structure) more accurate.
> >
> > > -----Original Message-----
> > > From: devel@edk2.groups.io <devel@edk2.groups.io> On Behalf Of
> > Javeed,
> > > Ashraf
> > > Sent: Tuesday, March 17, 2020 4:04 PM
> > > To: devel@edk2.groups.io
> > > Cc: Kinney, Michael D <michael.d.kinney@intel.com>; Gao, Liming
> > > <liming.gao@intel.com>; Liu, Zhiguang <zhiguang.liu@intel.com>
> > > Subject: [edk2-devel] [PATCH V2] MdePkg-PciExpress40.h: DVSEC
> > > definition missing
> > >
> > > BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2598
> > >
> > > All registers definition of DVSEC are defined as per the PCI Express
> > > Base Specification 4.0 chapter 7.9.6.
> > >
> > > Signed-off-by: Ashraf Javeed <ashraf.javeed@intel.com>
> > > Cc: Michael D Kinney <michael.d.kinney@intel.com>
> > > Cc: Liming Gao <liming.gao@intel.com>
> > > Cc: Zhiguang Liu <zhiguang.liu@intel.com>
> > >
> > > V2: fixed the comment section description for DVSEC definitions
> > > ---
> > > MdePkg/Include/IndustryStandard/PciExpress40.h | 28
> > > ++++++++++++++++++++++++++++
> > > 1 file changed, 28 insertions(+)
> > >
> > > diff --git a/MdePkg/Include/IndustryStandard/PciExpress40.h
> > > b/MdePkg/Include/IndustryStandard/PciExpress40.h
> > > index 9d9b272546..0564d72861 100644
> > > --- a/MdePkg/Include/IndustryStandard/PciExpress40.h
> > > +++ b/MdePkg/Include/IndustryStandard/PciExpress40.h
> > > @@ -4,6 +4,7 @@ Support for the PCI Express 4.0 standard.
> > > This header file may not define all structures. Please extend as required.
> > >
> > > Copyright (c) 2018, American Megatrends, Inc. All rights
> > > reserved.<BR>
> > > +Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
> > > SPDX-License-Identifier: BSD-2-Clause-Patent
> > >
> > > **/
> > > @@ -78,6 +79,33 @@ typedef struct {
> > > } PCI_EXPRESS_EXTENDED_CAPABILITIES_PHYSICAL_LAYER_16_0;
> > > ///@}
> > >
> > > +/// The Designated Vendor Specific Capability definitions /// Based
> > > +on section 7.9.6 of PCI Express Base Specification 4.0.
> > > +///@{
> > > +typedef union {
> > > + struct {
> > > + UINT32 DvsecVendorId : 16; //bit 0..15
> > > + UINT32 DvsecRevision : 4; //bit 16..19
> > > + UINT32 DvsecLength : 12; //bit 20..31
> > > + }Bits;
> > > + UINT32 Uint32;
> > > +}PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_1;
> > > +
> > > +typedef union {
> > > + struct {
> > > + UINT16 DvsecId : 16; //bit 0..15
> > > + }Bits;
> > > + UINT16 Uint16;
> > > +}PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_2;
> > > +
> > > +typedef struct {
> > > + PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;
> > > + PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_1
> > > DesignatedVendorSpecificHeader1;
> > > + PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_2
> > > DesignatedVendorSpecificHeader2;
> > > + UINT8 DesignatedVendorSpecific[1];
> > >
> > +}PCI_EXPRESS_EXTENDED_CAPABILITIES_DESIGNATED_VENDOR_SPECIFIC;
> > > +///@}
> > > +
> > > #pragma pack()
> > >
> > > #endif
> > > --
> > > 2.21.0.windows.1
> > >
> > >
> > >
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