Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Michael Kubacki <michael.a.kubacki@intel.com>
Cc: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
---
.../FspWrapperPlatformSecLib.c | 186 ---------
.../SecFspWrapperPlatformSecLib/FsptCoreUpd.h | 40 --
.../SecFspWrapperPlatformSecLib/Ia32/Fsp.h | 42 --
.../Ia32/PeiCoreEntry.nasm | 130 -------
.../Ia32/SecEntry.nasm | 361 ------------------
.../Ia32/Stack.nasm | 72 ----
.../PlatformInit.c | 47 ---
.../SecFspWrapperPlatformSecLib.inf | 97 -----
.../SecGetPerformance.c | 89 -----
.../SecPlatformInformation.c | 78 ----
.../SecRamInitData.c | 36 --
.../SecTempRamDone.c | 73 ----
.../GalagoPro3/OpenBoardPkg.dsc | 2 +-
.../KabylakeRvp3/OpenBoardPkg.dsc | 2 +-
14 files changed, 2 insertions(+), 1253 deletions(-)
delete mode 100644 Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/FspWrapperPlatformSecLib.c
delete mode 100644 Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/FsptCoreUpd.h
delete mode 100644 Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/Fsp.h
delete mode 100644 Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/PeiCoreEntry.nasm
delete mode 100644 Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/SecEntry.nasm
delete mode 100644 Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/Stack.nasm
delete mode 100644 Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/PlatformInit.c
delete mode 100644 Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecFspWrapperPlatformSecLib.inf
delete mode 100644 Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecGetPerformance.c
delete mode 100644 Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecPlatformInformation.c
delete mode 100644 Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecRamInitData.c
delete mode 100644 Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecTempRamDone.c
diff --git a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/FspWrapperPlatformSecLib.c b/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/FspWrapperPlatformSecLib.c
deleted file mode 100644
index d40eecae95..0000000000
--- a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/FspWrapperPlatformSecLib.c
+++ /dev/null
@@ -1,186 +0,0 @@
-/** @file
- Provide FSP wrapper platform sec related function.
-
-Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR>
-SPDX-License-Identifier: BSD-2-Clause-Patent
-
-**/
-
-#include <PiPei.h>
-
-#include <Ppi/SecPlatformInformation.h>
-#include <Ppi/SecPerformance.h>
-#include <Ppi/FirmwareVolumeInfo.h>
-#include <Ppi/TopOfTemporaryRam.h>
-#include <Ppi/PeiCoreFvLocation.h>
-#include <Guid/FirmwareFileSystem2.h>
-
-#include <Library/LocalApicLib.h>
-#include <Library/BaseMemoryLib.h>
-#include <Library/DebugLib.h>
-#include <Library/IoLib.h>
-
-/**
- This interface conveys state information out of the Security (SEC) phase into PEI.
-
- @param[in] PeiServices Pointer to the PEI Services Table.
- @param[in,out] StructureSize Pointer to the variable describing size of the input buffer.
- @param[out] PlatformInformationRecord Pointer to the EFI_SEC_PLATFORM_INFORMATION_RECORD.
-
- @retval EFI_SUCCESS The data was successfully returned.
- @retval EFI_BUFFER_TOO_SMALL The buffer was too small.
-
-**/
-EFI_STATUS
-EFIAPI
-SecPlatformInformation (
- IN CONST EFI_PEI_SERVICES **PeiServices,
- IN OUT UINT64 *StructureSize,
- OUT EFI_SEC_PLATFORM_INFORMATION_RECORD *PlatformInformationRecord
- );
-
-/**
- This interface conveys performance information out of the Security (SEC) phase into PEI.
-
- This service is published by the SEC phase. The SEC phase handoff has an optional
- EFI_PEI_PPI_DESCRIPTOR list as its final argument when control is passed from SEC into the
- PEI Foundation. As such, if the platform supports collecting performance data in SEC,
- this information is encapsulated into the data structure abstracted by this service.
- This information is collected for the boot-strap processor (BSP) on IA-32.
-
- @param[in] PeiServices The pointer to the PEI Services Table.
- @param[in] This The pointer to this instance of the PEI_SEC_PERFORMANCE_PPI.
- @param[out] Performance The pointer to performance data collected in SEC phase.
-
- @retval EFI_SUCCESS The data was successfully returned.
-
-**/
-EFI_STATUS
-EFIAPI
-SecGetPerformance (
- IN CONST EFI_PEI_SERVICES **PeiServices,
- IN PEI_SEC_PERFORMANCE_PPI *This,
- OUT FIRMWARE_SEC_PERFORMANCE *Performance
- );
-
-PEI_SEC_PERFORMANCE_PPI mSecPerformancePpi = {
- SecGetPerformance
-};
-
-EFI_PEI_CORE_FV_LOCATION_PPI mPeiCoreFvLocationPpi = {
- (VOID *) (UINTN) FixedPcdGet32 (PcdFspmBaseAddress)
-};
-
-EFI_PEI_PPI_DESCRIPTOR mPeiCoreFvLocationPpiList[] = {
- {
- EFI_PEI_PPI_DESCRIPTOR_PPI,
- &gEfiPeiCoreFvLocationPpiGuid,
- &mPeiCoreFvLocationPpi
- }
-};
-
-EFI_PEI_PPI_DESCRIPTOR mPeiSecPlatformPpi[] = {
- {
- EFI_PEI_PPI_DESCRIPTOR_PPI,
- &gTopOfTemporaryRamPpiGuid,
- NULL // To be patched later.
- },
- {
- EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,
- &gPeiSecPerformancePpiGuid,
- &mSecPerformancePpi
- },
-};
-
-#define LEGACY_8259_MASK_REGISTER_MASTER 0x21
-#define LEGACY_8259_MASK_REGISTER_SLAVE 0xA1
-#define LEGACY_8259_EDGE_LEVEL_TRIGGERED_REGISTER_MASTER 0x4D0
-#define LEGACY_8259_EDGE_LEVEL_TRIGGERED_REGISTER_SLAVE 0x4D1
-
-/**
- Write to mask and edge/level triggered registers of master and slave 8259 PICs.
-
- @param[in] Mask low byte for master PIC mask register,
- high byte for slave PIC mask register.
- @param[in] EdgeLevel low byte for master PIC edge/level triggered register,
- high byte for slave PIC edge/level triggered register.
-
-**/
-VOID
-Interrupt8259WriteMask (
- IN UINT16 Mask,
- IN UINT16 EdgeLevel
- )
-{
- IoWrite8 (LEGACY_8259_MASK_REGISTER_MASTER, (UINT8) Mask);
- IoWrite8 (LEGACY_8259_MASK_REGISTER_SLAVE, (UINT8) (Mask >> 8));
- IoWrite8 (LEGACY_8259_EDGE_LEVEL_TRIGGERED_REGISTER_MASTER, (UINT8) EdgeLevel);
- IoWrite8 (LEGACY_8259_EDGE_LEVEL_TRIGGERED_REGISTER_SLAVE, (UINT8) (EdgeLevel >> 8));
-}
-
-/**
- A developer supplied function to perform platform specific operations.
-
- It's a developer supplied function to perform any operations appropriate to a
- given platform. It's invoked just before passing control to PEI core by SEC
- core. Platform developer may modify the SecCoreData passed to PEI Core.
- It returns a platform specific PPI list that platform wishes to pass to PEI core.
- The Generic SEC core module will merge this list to join the final list passed to
- PEI core.
-
- @param[in,out] SecCoreData The same parameter as passing to PEI core. It
- could be overridden by this function.
-
- @return The platform specific PPI list to be passed to PEI core or
- NULL if there is no need of such platform specific PPI list.
-
-**/
-EFI_PEI_PPI_DESCRIPTOR *
-EFIAPI
-SecPlatformMain (
- IN OUT EFI_SEC_PEI_HAND_OFF *SecCoreData
- )
-{
- EFI_PEI_PPI_DESCRIPTOR *PpiList;
- UINT8 TopOfTemporaryRamPpiIndex;
- UINT8 *CopyDestinationPointer;
-
- DEBUG ((DEBUG_INFO, "FSP Wrapper BootFirmwareVolumeBase - 0x%x\n", SecCoreData->BootFirmwareVolumeBase));
- DEBUG ((DEBUG_INFO, "FSP Wrapper BootFirmwareVolumeSize - 0x%x\n", SecCoreData->BootFirmwareVolumeSize));
- DEBUG ((DEBUG_INFO, "FSP Wrapper TemporaryRamBase - 0x%x\n", SecCoreData->TemporaryRamBase));
- DEBUG ((DEBUG_INFO, "FSP Wrapper TemporaryRamSize - 0x%x\n", SecCoreData->TemporaryRamSize));
- DEBUG ((DEBUG_INFO, "FSP Wrapper PeiTemporaryRamBase - 0x%x\n", SecCoreData->PeiTemporaryRamBase));
- DEBUG ((DEBUG_INFO, "FSP Wrapper PeiTemporaryRamSize - 0x%x\n", SecCoreData->PeiTemporaryRamSize));
- DEBUG ((DEBUG_INFO, "FSP Wrapper StackBase - 0x%x\n", SecCoreData->StackBase));
- DEBUG ((DEBUG_INFO, "FSP Wrapper StackSize - 0x%x\n", SecCoreData->StackSize));
-
- InitializeApicTimer (0, (UINT32) -1, TRUE, 5);
-
- //
- // Set all 8259 interrupts to edge triggered and disabled
- //
- Interrupt8259WriteMask (0xFFFF, 0x0000);
-
- //
- // Use middle of Heap as temp buffer, it will be copied by caller.
- // Do not use Stack, because it will cause wrong calculation on stack by PeiCore
- //
- PpiList = (VOID *)((UINTN) SecCoreData->PeiTemporaryRamBase + (UINTN) SecCoreData->PeiTemporaryRamSize/2);
- CopyDestinationPointer = (UINT8 *) PpiList;
- TopOfTemporaryRamPpiIndex = 0;
- if (PcdGet8 (PcdFspModeSelection) == 0) {
- //
- // In Dispatch mode, wrapper should provide PeiCoreFvLocationPpi.
- //
- CopyMem (CopyDestinationPointer, mPeiCoreFvLocationPpiList, sizeof (mPeiCoreFvLocationPpiList));
- TopOfTemporaryRamPpiIndex = 1;
- CopyDestinationPointer += sizeof (mPeiCoreFvLocationPpiList);
- }
- CopyMem (CopyDestinationPointer, mPeiSecPlatformPpi, sizeof(mPeiSecPlatformPpi));
- //
- // Patch TopOfTemporaryRamPpi
- //
- PpiList[TopOfTemporaryRamPpiIndex].Ppi = (VOID *)((UINTN) SecCoreData->TemporaryRamBase + SecCoreData->TemporaryRamSize);
-
- return PpiList;
-}
diff --git a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/FsptCoreUpd.h b/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/FsptCoreUpd.h
deleted file mode 100644
index 7c0f605b92..0000000000
--- a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/FsptCoreUpd.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/** @file
-
-Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
-SPDX-License-Identifier: BSD-2-Clause-Patent
-
-**/
-
-#ifndef __FSPT_CORE_UPD_H__
-#define __FSPT_CORE_UPD_H__
-
-#pragma pack(1)
-
-/** Fsp T Core UPD
-**/
-typedef struct {
-
-/** Offset 0x0020
-**/
- UINT32 MicrocodeRegionBase;
-
-/** Offset 0x0024
-**/
- UINT32 MicrocodeRegionSize;
-
-/** Offset 0x0028
-**/
- UINT32 CodeRegionBase;
-
-/** Offset 0x002C
-**/
- UINT32 CodeRegionSize;
-
-/** Offset 0x0030
-**/
- UINT8 Reserved[16];
-} FSPT_CORE_UPD;
-
-#pragma pack()
-
-#endif
diff --git a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/Fsp.h b/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/Fsp.h
deleted file mode 100644
index 9f6cdcf476..0000000000
--- a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/Fsp.h
+++ /dev/null
@@ -1,42 +0,0 @@
-/** @file
- Fsp related definitions
-
-Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
-SPDX-License-Identifier: BSD-2-Clause-Patent
-
-**/
-
-#ifndef __FSP_H__
-#define __FSP_H__
-
-//
-// Fv Header
-//
-#define FVH_SIGINATURE_OFFSET 0x28
-#define FVH_SIGINATURE_VALID_VALUE 0x4856465F // valid signature:_FVH
-#define FVH_HEADER_LENGTH_OFFSET 0x30
-#define FVH_EXTHEADER_OFFSET_OFFSET 0x34
-#define FVH_EXTHEADER_SIZE_OFFSET 0x10
-
-//
-// Ffs Header
-//
-#define FSP_HEADER_GUID_DWORD1 0x912740BE
-#define FSP_HEADER_GUID_DWORD2 0x47342284
-#define FSP_HEADER_GUID_DWORD3 0xB08471B9
-#define FSP_HEADER_GUID_DWORD4 0x0C3F3527
-#define FFS_HEADER_SIZE_VALUE 0x18
-
-//
-// Section Header
-//
-#define SECTION_HEADER_TYPE_OFFSET 0x03
-#define RAW_SECTION_HEADER_SIZE_VALUE 0x04
-
-//
-// Fsp Header
-//
-#define FSP_HEADER_IMAGEBASE_OFFSET 0x1C
-#define FSP_HEADER_TEMPRAMINIT_OFFSET 0x30
-
-#endif
diff --git a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/PeiCoreEntry.nasm b/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/PeiCoreEntry.nasm
deleted file mode 100644
index 5c5b788085..0000000000
--- a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/PeiCoreEntry.nasm
+++ /dev/null
@@ -1,130 +0,0 @@
-;------------------------------------------------------------------------------
-;
-; Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
-; SPDX-License-Identifier: BSD-2-Clause-Patent
-;
-; Module Name:
-;
-; PeiCoreEntry.nasm
-;
-; Abstract:
-;
-; Find and call SecStartup
-;
-;------------------------------------------------------------------------------
-
-SECTION .text
-
-extern ASM_PFX(SecStartup)
-extern ASM_PFX(PlatformInit)
-
-global ASM_PFX(CallPeiCoreEntryPoint)
-ASM_PFX(CallPeiCoreEntryPoint):
- ;
- ; Obtain the hob list pointer
- ;
- mov eax, [esp+4]
- ;
- ; Obtain the stack information
- ; ECX: start of range
- ; EDX: end of range
- ;
- mov ecx, [esp+8]
- mov edx, [esp+0xC]
-
- ;
- ; Platform init
- ;
- pushad
- push edx
- push ecx
- push eax
- call ASM_PFX(PlatformInit)
- pop eax
- pop eax
- pop eax
- popad
-
- ;
- ; Set stack top pointer
- ;
- mov esp, edx
-
- ;
- ; Push the hob list pointer
- ;
- push eax
-
- ;
- ; Save the value
- ; ECX: start of range
- ; EDX: end of range
- ;
- mov ebp, esp
- push ecx
- push edx
-
- ;
- ; Push processor count to stack first, then BIST status (AP then BSP)
- ;
- mov eax, 1
- cpuid
- shr ebx, 16
- and ebx, 0xFF
- cmp bl, 1
- jae PushProcessorCount
-
- ;
- ; Some processors report 0 logical processors. Effectively 0 = 1.
- ; So we fix up the processor count
- ;
- inc ebx
-
-PushProcessorCount:
- push ebx
-
- ;
- ; We need to implement a long-term solution for BIST capture. For now, we just copy BSP BIST
- ; for all processor threads
- ;
- xor ecx, ecx
- mov cl, bl
-PushBist:
- movd eax, mm0
- push eax
- loop PushBist
-
- ; Save Time-Stamp Counter
- movd eax, mm5
- push eax
-
- movd eax, mm6
- push eax
-
- ;
- ; Pass entry point of the PEI core
- ;
- mov edi, 0xFFFFFFE0
- push DWORD [edi]
-
- ;
- ; Pass BFV into the PEI Core
- ;
- mov edi, 0xFFFFFFFC
- push DWORD [edi]
-
- ;
- ; Pass stack size into the PEI Core
- ;
- mov ecx, [ebp - 4]
- mov edx, [ebp - 8]
- push ecx ; RamBase
-
- sub edx, ecx
- push edx ; RamSize
-
- ;
- ; Pass Control into the PEI Core
- ;
- call ASM_PFX(SecStartup)
-
diff --git a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/SecEntry.nasm b/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/SecEntry.nasm
deleted file mode 100644
index 7f6d771e41..0000000000
--- a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/SecEntry.nasm
+++ /dev/null
@@ -1,361 +0,0 @@
-;------------------------------------------------------------------------------
-;
-; Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
-; SPDX-License-Identifier: BSD-2-Clause-Patent
-; Module Name:
-;
-; SecEntry.nasm
-;
-; Abstract:
-;
-; This is the code that goes from real-mode to protected mode.
-; It consumes the reset vector, calls TempRamInit API from FSP binary.
-;
-;------------------------------------------------------------------------------
-
-#include "Fsp.h"
-
-SECTION .text
-
-extern ASM_PFX(CallPeiCoreEntryPoint)
-extern ASM_PFX(FsptUpdDataPtr)
-extern ASM_PFX(BoardBeforeTempRamInit)
-; Pcds
-extern ASM_PFX(PcdGet32 (PcdFspTemporaryRamSize))
-extern ASM_PFX(PcdGet32 (PcdFsptBaseAddress))
-
-;----------------------------------------------------------------------------
-;
-; Procedure: _ModuleEntryPoint
-;
-; Input: None
-;
-; Output: None
-;
-; Destroys: Assume all registers
-;
-; Description:
-;
-; Transition to non-paged flat-model protected mode from a
-; hard-coded GDT that provides exactly two descriptors.
-; This is a bare bones transition to protected mode only
-; used for a while in PEI and possibly DXE.
-;
-; After enabling protected mode, a far jump is executed to
-; transfer to PEI using the newly loaded GDT.
-;
-; Return: None
-;
-; MMX Usage:
-; MM0 = BIST State
-; MM5 = Save time-stamp counter value high32bit
-; MM6 = Save time-stamp counter value low32bit.
-;
-;----------------------------------------------------------------------------
-
-BITS 16
-align 4
-global ASM_PFX(_ModuleEntryPoint)
-ASM_PFX(_ModuleEntryPoint):
- fninit ; clear any pending Floating point exceptions
- ;
- ; Store the BIST value in mm0
- ;
- movd mm0, eax
- cli
-
- ;
- ; Check INIT# is asserted by port 0xCF9
- ;
- mov dx, 0CF9h
- in al, dx
- cmp al, 04h
- jnz NotWarmStart
-
-
- ;
- ; @note Issue warm reset, since if CPU only reset is issued not all MSRs are restored to their defaults
- ;
- mov dx, 0CF9h
- mov al, 06h
- out dx, al
-
-NotWarmStart:
- ;
- ; Save time-stamp counter value
- ; rdtsc load 64bit time-stamp counter to EDX:EAX
- ;
- rdtsc
- movd mm5, edx
- movd mm6, eax
-
- ;
- ; Load the GDT table in GdtDesc
- ;
- mov esi, GdtDesc
- DB 66h
- lgdt [cs:si]
-
- ;
- ; Transition to 16 bit protected mode
- ;
- mov eax, cr0 ; Get control register 0
- or eax, 00000003h ; Set PE bit (bit #0) & MP bit (bit #1)
- mov cr0, eax ; Activate protected mode
-
- mov eax, cr4 ; Get control register 4
- or eax, 00000600h ; Set OSFXSR bit (bit #9) & OSXMMEXCPT bit (bit #10)
- mov cr4, eax
-
- ;
- ; Now we're in 16 bit protected mode
- ; Set up the selectors for 32 bit protected mode entry
- ;
- mov ax, SYS_DATA_SEL
- mov ds, ax
- mov es, ax
- mov fs, ax
- mov gs, ax
- mov ss, ax
-
- ;
- ; Transition to Flat 32 bit protected mode
- ; The jump to a far pointer causes the transition to 32 bit mode
- ;
- mov esi, ProtectedModeEntryLinearAddress
- jmp dword far [cs:si]
-
-;----------------------------------------------------------------------------
-;
-; Procedure: ProtectedModeEntryPoint
-;
-; Input: None
-;
-; Output: None
-;
-; Destroys: Assume all registers
-;
-; Description:
-;
-; This function handles:
-; Call two basic APIs from FSP binary
-; Initializes stack with some early data (BIST, PEI entry, etc)
-;
-; Return: None
-;
-;----------------------------------------------------------------------------
-
-BITS 32
-align 4
-ProtectedModeEntryPoint:
- ;
- ; Early board hooks
- ;
- mov esp, BoardBeforeTempRamInitRet
- jmp ASM_PFX(BoardBeforeTempRamInit)
-
-BoardBeforeTempRamInitRet:
-
- ; Find the fsp info header
- mov edi, [ASM_PFX(PcdGet32 (PcdFsptBaseAddress))]
-
- mov eax, dword [edi + FVH_SIGINATURE_OFFSET]
- cmp eax, FVH_SIGINATURE_VALID_VALUE
- jnz FspHeaderNotFound
-
- xor eax, eax
- mov ax, word [edi + FVH_EXTHEADER_OFFSET_OFFSET]
- cmp ax, 0
- jnz FspFvExtHeaderExist
-
- xor eax, eax
- mov ax, word [edi + FVH_HEADER_LENGTH_OFFSET] ; Bypass Fv Header
- add edi, eax
- jmp FspCheckFfsHeader
-
-FspFvExtHeaderExist:
- add edi, eax
- mov eax, dword [edi + FVH_EXTHEADER_SIZE_OFFSET] ; Bypass Ext Fv Header
- add edi, eax
-
- ; Round up to 8 byte alignment
- mov eax, edi
- and al, 07h
- jz FspCheckFfsHeader
-
- and edi, 0FFFFFFF8h
- add edi, 08h
-
-FspCheckFfsHeader:
- ; Check the ffs guid
- mov eax, dword [edi]
- cmp eax, FSP_HEADER_GUID_DWORD1
- jnz FspHeaderNotFound
-
- mov eax, dword [edi + 4]
- cmp eax, FSP_HEADER_GUID_DWORD2
- jnz FspHeaderNotFound
-
- mov eax, dword [edi + 8]
- cmp eax, FSP_HEADER_GUID_DWORD3
- jnz FspHeaderNotFound
-
- mov eax, dword [edi + 0Ch]
- cmp eax, FSP_HEADER_GUID_DWORD4
- jnz FspHeaderNotFound
-
- add edi, FFS_HEADER_SIZE_VALUE ; Bypass the ffs header
-
- ; Check the section type as raw section
- mov al, byte [edi + SECTION_HEADER_TYPE_OFFSET]
- cmp al, 019h
- jnz FspHeaderNotFound
-
- add edi, RAW_SECTION_HEADER_SIZE_VALUE ; Bypass the section header
- jmp FspHeaderFound
-
-FspHeaderNotFound:
- jmp $
-
-FspHeaderFound:
- ; Get the fsp TempRamInit Api address
- mov eax, dword [edi + FSP_HEADER_IMAGEBASE_OFFSET]
- add eax, dword [edi + FSP_HEADER_TEMPRAMINIT_OFFSET]
-
- ; Setup the hardcode stack
- mov esp, TempRamInitStack
-
- ; Call the fsp TempRamInit Api
- jmp eax
-
-TempRamInitDone:
- cmp eax, 8000000Eh ;Check if EFI_NOT_FOUND returned. Error code for Microcode Update not found.
- je CallSecFspInit ;If microcode not found, don't hang, but continue.
-
- cmp eax, 0 ;Check if EFI_SUCCESS retuned.
- jnz FspApiFailed
-
- ; ECX: start of range
- ; EDX: end of range
-CallSecFspInit:
- sub edx, [ASM_PFX(PcdGet32 (PcdFspTemporaryRamSize))] ; TemporaryRam for FSP
- xor eax, eax
- mov esp, edx
-
- ; Align the stack at DWORD
- add esp, 3
- and esp, 0FFFFFFFCh
-
- push edx
- push ecx
- push eax ; zero - no hob list yet
- call ASM_PFX(CallPeiCoreEntryPoint)
-
-FspApiFailed:
- jmp $
-
-align 10h
-TempRamInitStack:
- DD TempRamInitDone
- DD ASM_PFX(FsptUpdDataPtr); TempRamInitParams
-
-;
-; ROM-based Global-Descriptor Table for the Tiano PEI Phase
-;
-align 16
-global ASM_PFX(BootGdtTable)
-
-;
-; GDT[0]: 0x00: Null entry, never used.
-;
-NULL_SEL EQU $ - GDT_BASE ; Selector [0]
-GDT_BASE:
-ASM_PFX(BootGdtTable):
- DD 0
- DD 0
-;
-; Linear data segment descriptor
-;
-LINEAR_SEL EQU $ - GDT_BASE ; Selector [0x8]
- DW 0FFFFh ; limit 0xFFFFF
- DW 0 ; base 0
- DB 0
- DB 092h ; present, ring 0, data, expand-up, writable
- DB 0CFh ; page-granular, 32-bit
- DB 0
-;
-; Linear code segment descriptor
-;
-LINEAR_CODE_SEL EQU $ - GDT_BASE ; Selector [0x10]
- DW 0FFFFh ; limit 0xFFFFF
- DW 0 ; base 0
- DB 0
- DB 09Bh ; present, ring 0, data, expand-up, not-writable
- DB 0CFh ; page-granular, 32-bit
- DB 0
-;
-; System data segment descriptor
-;
-SYS_DATA_SEL EQU $ - GDT_BASE ; Selector [0x18]
- DW 0FFFFh ; limit 0xFFFFF
- DW 0 ; base 0
- DB 0
- DB 093h ; present, ring 0, data, expand-up, not-writable
- DB 0CFh ; page-granular, 32-bit
- DB 0
-
-;
-; System code segment descriptor
-;
-SYS_CODE_SEL EQU $ - GDT_BASE ; Selector [0x20]
- DW 0FFFFh ; limit 0xFFFFF
- DW 0 ; base 0
- DB 0
- DB 09Ah ; present, ring 0, data, expand-up, writable
- DB 0CFh ; page-granular, 32-bit
- DB 0
-;
-; Spare segment descriptor
-;
-SYS16_CODE_SEL EQU $ - GDT_BASE ; Selector [0x28]
- DW 0FFFFh ; limit 0xFFFFF
- DW 0 ; base 0
- DB 0Eh ; Changed from F000 to E000.
- DB 09Bh ; present, ring 0, code, expand-up, writable
- DB 00h ; byte-granular, 16-bit
- DB 0
-;
-; Spare segment descriptor
-;
-SYS16_DATA_SEL EQU $ - GDT_BASE ; Selector [0x30]
- DW 0FFFFh ; limit 0xFFFF
- DW 0 ; base 0
- DB 0
- DB 093h ; present, ring 0, data, expand-up, not-writable
- DB 00h ; byte-granular, 16-bit
- DB 0
-
-;
-; Spare segment descriptor
-;
-SPARE5_SEL EQU $ - GDT_BASE ; Selector [0x38]
- DW 0 ; limit 0
- DW 0 ; base 0
- DB 0
- DB 0 ; present, ring 0, data, expand-up, writable
- DB 0 ; page-granular, 32-bit
- DB 0
-GDT_SIZE EQU $ - GDT_BASE ; Size, in bytes
-
-;
-; GDT Descriptor
-;
-GdtDesc: ; GDT descriptor
- DW GDT_SIZE - 1 ; GDT limit
- DD GDT_BASE ; GDT base address
-
-
-ProtectedModeEntryLinearAddress:
-ProtectedModeEntryLinear:
- DD ProtectedModeEntryPoint ; Offset of our 32 bit code
- DW LINEAR_CODE_SEL
diff --git a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/Stack.nasm b/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/Stack.nasm
deleted file mode 100644
index 47db32d64c..0000000000
--- a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/Stack.nasm
+++ /dev/null
@@ -1,72 +0,0 @@
-;------------------------------------------------------------------------------
-;
-; Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
-; SPDX-License-Identifier: BSD-2-Clause-Patent
-; Abstract:
-;
-; Switch the stack from temporary memory to permanent memory.
-;
-;------------------------------------------------------------------------------
-
- SECTION .text
-
-;------------------------------------------------------------------------------
-; VOID
-; EFIAPI
-; SecSwitchStack (
-; UINT32 TemporaryMemoryBase,
-; UINT32 PermanentMemoryBase
-; );
-;------------------------------------------------------------------------------
-global ASM_PFX(SecSwitchStack)
-ASM_PFX(SecSwitchStack):
- ;
- ; Save three register: eax, ebx, ecx
- ;
- push eax
- push ebx
- push ecx
- push edx
-
- ;
- ; !!CAUTION!! this function address's is pushed into stack after
- ; migration of whole temporary memory, so need save it to permanent
- ; memory at first!
- ;
-
- mov ebx, [esp + 20] ; Save the first parameter
- mov ecx, [esp + 24] ; Save the second parameter
-
- ;
- ; Save this function's return address into permanent memory at first.
- ; Then, Fixup the esp point to permanent memory
- ;
- mov eax, esp
- sub eax, ebx
- add eax, ecx
- mov edx, dword [esp] ; copy pushed register's value to permanent memory
- mov dword [eax], edx
- mov edx, dword [esp + 4]
- mov dword [eax + 4], edx
- mov edx, dword [esp + 8]
- mov dword [eax + 8], edx
- mov edx, dword [esp + 12]
- mov dword [eax + 12], edx
- mov edx, dword [esp + 16] ; Update this function's return address into permanent memory
- mov dword [eax + 16], edx
- mov esp, eax ; From now, esp is pointed to permanent memory
-
- ;
- ; Fixup the ebp point to permanent memory
- ;
- mov eax, ebp
- sub eax, ebx
- add eax, ecx
- mov ebp, eax ; From now, ebp is pointed to permanent memory
-
- pop edx
- pop ecx
- pop ebx
- pop eax
- ret
-
diff --git a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/PlatformInit.c b/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/PlatformInit.c
deleted file mode 100644
index ef89e3f310..0000000000
--- a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/PlatformInit.c
+++ /dev/null
@@ -1,47 +0,0 @@
-/** @file
- Provide platform init function.
-
-Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
-SPDX-License-Identifier: BSD-2-Clause-Patent
-
-**/
-
-
-#include <PiPei.h>
-#include <Library/DebugLib.h>
-#include <Library/SerialPortLib.h>
-#include <Library/SecBoardInitLib.h>
-#include <Library/TestPointCheckLib.h>
-
-/**
- Platform initialization.
-
- @param[in] FspHobList HobList produced by FSP.
- @param[in] StartOfRange Start of temporary RAM.
- @param[in] EndOfRange End of temporary RAM.
-**/
-VOID
-EFIAPI
-PlatformInit (
- IN VOID *FspHobList,
- IN VOID *StartOfRange,
- IN VOID *EndOfRange
- )
-{
- //
- // Platform initialization
- // Enable Serial port here
- //
- if (PcdGetBool(PcdSecSerialPortDebugEnable)) {
- SerialPortInitialize ();
- }
-
- DEBUG ((DEBUG_INFO, "PrintPeiCoreEntryPointParam in PlatformInit\n"));
- DEBUG ((DEBUG_INFO, "FspHobList - 0x%x\n", FspHobList));
- DEBUG ((DEBUG_INFO, "StartOfRange - 0x%x\n", StartOfRange));
- DEBUG ((DEBUG_INFO, "EndOfRange - 0x%x\n", EndOfRange));
-
- BoardAfterTempRamInit ();
-
- TestPointTempMemoryFunction (StartOfRange, EndOfRange);
-}
diff --git a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecFspWrapperPlatformSecLib.inf b/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecFspWrapperPlatformSecLib.inf
deleted file mode 100644
index c99dd5ecdd..0000000000
--- a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecFspWrapperPlatformSecLib.inf
+++ /dev/null
@@ -1,97 +0,0 @@
-## @file
-# Provide FSP wrapper platform sec related function.
-#
-# Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR>
-#
-# SPDX-License-Identifier: BSD-2-Clause-Patent
-#
-#
-##
-
-################################################################################
-#
-# Defines Section - statements that will be processed to create a Makefile.
-#
-################################################################################
-[Defines]
- INF_VERSION = 0x00010005
- BASE_NAME = SecFspWrapperPlatformSecLib
- FILE_GUID = 4E1C4F95-90EA-47de-9ACC-B8920189A1F5
- MODULE_TYPE = SEC
- VERSION_STRING = 1.0
- LIBRARY_CLASS = PlatformSecLib
-
-
-#
-# The following information is for reference only and not required by the build tools.
-#
-# VALID_ARCHITECTURES = IA32 X64
-#
-
-################################################################################
-#
-# Sources Section - list of files that are required for the build to succeed.
-#
-################################################################################
-
-[Sources]
- FspWrapperPlatformSecLib.c
- SecRamInitData.c
- SecPlatformInformation.c
- SecGetPerformance.c
- SecTempRamDone.c
- PlatformInit.c
-
-[Sources.IA32]
- Ia32/SecEntry.nasm
- Ia32/PeiCoreEntry.nasm
- Ia32/Stack.nasm
- Ia32/Fsp.h
-
-################################################################################
-#
-# Package Dependency Section - list of Package files that are required for
-# this module.
-#
-################################################################################
-
-[Packages]
- MdePkg/MdePkg.dec
- MdeModulePkg/MdeModulePkg.dec
- UefiCpuPkg/UefiCpuPkg.dec
- IntelFsp2Pkg/IntelFsp2Pkg.dec
- IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec
- MinPlatformPkg/MinPlatformPkg.dec
- KabylakeSiliconPkg/SiPkg.dec
-
-[LibraryClasses]
- LocalApicLib
- SerialPortLib
- FspWrapperPlatformLib
- FspWrapperApiLib
- BoardInitLib
- SecBoardInitLib
- TestPointCheckLib
- PeiServicesTablePointerLib
-
-[Ppis]
- gEfiSecPlatformInformationPpiGuid ## CONSUMES
- gPeiSecPerformancePpiGuid ## CONSUMES
- gTopOfTemporaryRamPpiGuid ## PRODUCES
- gEfiPeiFirmwareVolumeInfoPpiGuid ## PRODUCES
- gFspTempRamExitPpiGuid ## CONSUMES
-
-[Pcd]
- gUefiCpuPkgTokenSpaceGuid.PcdPeiTemporaryRamStackSize ## CONSUMES
- gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress ## CONSUMES
- gIntelFsp2PkgTokenSpaceGuid.PcdFspTemporaryRamSize ## CONSUMES
- gMinPlatformPkgTokenSpaceGuid.PcdSecSerialPortDebugEnable ## CONSUMES
-
-[FixedPcd]
- gIntelFsp2WrapperTokenSpaceGuid.PcdCpuMicrocodePatchAddress ## CONSUMES
- gIntelFsp2WrapperTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize ## CONSUMES
- gIntelFsp2WrapperTokenSpaceGuid.PcdFlashMicrocodeOffset ## CONSUMES
- gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheAddress ## CONSUMES
- gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheSize ## CONSUMES
- gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress ## CONSUMES
- gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection ## CONSUMES
diff --git a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecGetPerformance.c b/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecGetPerformance.c
deleted file mode 100644
index c4eeb2b188..0000000000
--- a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecGetPerformance.c
+++ /dev/null
@@ -1,89 +0,0 @@
-/** @file
- Sample to provide SecGetPerformance function.
-
-Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
-SPDX-License-Identifier: BSD-2-Clause-Patent
-
-**/
-
-#include <PiPei.h>
-
-#include <Ppi/SecPerformance.h>
-#include <Ppi/TopOfTemporaryRam.h>
-
-#include <Library/BaseMemoryLib.h>
-#include <Library/TimerLib.h>
-#include <Library/DebugLib.h>
-
-/**
- This interface conveys performance information out of the Security (SEC) phase into PEI.
-
- This service is published by the SEC phase. The SEC phase handoff has an optional
- EFI_PEI_PPI_DESCRIPTOR list as its final argument when control is passed from SEC into the
- PEI Foundation. As such, if the platform supports collecting performance data in SEC,
- this information is encapsulated into the data structure abstracted by this service.
- This information is collected for the boot-strap processor (BSP) on IA-32.
-
- @param[in] PeiServices The pointer to the PEI Services Table.
- @param[in] This The pointer to this instance of the PEI_SEC_PERFORMANCE_PPI.
- @param[out] Performance The pointer to performance data collected in SEC phase.
-
- @retval EFI_SUCCESS The data was successfully returned.
-
-**/
-EFI_STATUS
-EFIAPI
-SecGetPerformance (
- IN CONST EFI_PEI_SERVICES **PeiServices,
- IN PEI_SEC_PERFORMANCE_PPI *This,
- OUT FIRMWARE_SEC_PERFORMANCE *Performance
- )
-{
- UINT32 Size;
- UINT32 Count;
- UINT32 TopOfTemporaryRam;
- UINT64 Ticker;
- VOID *TopOfTemporaryRamPpi;
- EFI_STATUS Status;
-
- DEBUG ((DEBUG_INFO, "SecGetPerformance\n"));
-
- Status = (*PeiServices)->LocatePpi (
- PeiServices,
- &gTopOfTemporaryRamPpiGuid,
- 0,
- NULL,
- (VOID **) &TopOfTemporaryRamPpi
- );
- if (EFI_ERROR (Status)) {
- return EFI_NOT_FOUND;
- }
- //
- // |--------------| <- TopOfTemporaryRam - BL
- // | List Ptr |
- // |--------------|
- // | BL RAM Start |
- // |--------------|
- // | BL RAM End |
- // |--------------|
- // |Number of BSPs|
- // |--------------|
- // | BIST |
- // |--------------|
- // | .... |
- // |--------------|
- // | TSC[63:32] |
- // |--------------|
- // | TSC[31:00] |
- // |--------------|
- //
- TopOfTemporaryRam = (UINT32)(UINTN)TopOfTemporaryRamPpi - sizeof(UINT32);
- TopOfTemporaryRam -= sizeof(UINT32) * 2;
- Count = *(UINT32 *) (UINTN) (TopOfTemporaryRam - sizeof (UINT32));
- Size = Count * sizeof (UINT32);
-
- Ticker = *(UINT64 *) (UINTN) (TopOfTemporaryRam - sizeof (UINT32) - Size - sizeof (UINT32) * 2);
- Performance->ResetEnd = GetTimeInNanoSecond (Ticker);
-
- return EFI_SUCCESS;
-}
diff --git a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecPlatformInformation.c b/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecPlatformInformation.c
deleted file mode 100644
index 5b94ed2bef..0000000000
--- a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecPlatformInformation.c
+++ /dev/null
@@ -1,78 +0,0 @@
-/** @file
- Provide SecPlatformInformation function.
-
-Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
-SPDX-License-Identifier: BSD-2-Clause-Patent
-
-**/
-
-#include <PiPei.h>
-
-#include <Ppi/SecPlatformInformation.h>
-#include <Ppi/TopOfTemporaryRam.h>
-
-#include <Library/BaseMemoryLib.h>
-#include <Library/DebugLib.h>
-
-/**
- This interface conveys state information out of the Security (SEC) phase into PEI.
-
- @param[in] PeiServices Pointer to the PEI Services Table.
- @param[in,out] StructureSize Pointer to the variable describing size of the input buffer.
- @param[out] PlatformInformationRecord Pointer to the EFI_SEC_PLATFORM_INFORMATION_RECORD.
-
- @retval EFI_SUCCESS The data was successfully returned.
- @retval EFI_BUFFER_TOO_SMALL The buffer was too small.
-
-**/
-EFI_STATUS
-EFIAPI
-SecPlatformInformation (
- IN CONST EFI_PEI_SERVICES **PeiServices,
- IN OUT UINT64 *StructureSize,
- OUT EFI_SEC_PLATFORM_INFORMATION_RECORD *PlatformInformationRecord
- )
-{
- UINT32 *Bist;
- UINT32 Size;
- UINT32 Count;
- UINT32 TopOfTemporaryRam;
- VOID *TopOfTemporaryRamPpi;
- EFI_STATUS Status;
-
- DEBUG ((DEBUG_INFO, "SecPlatformInformation\n"));
-
- Status = (*PeiServices)->LocatePpi (
- PeiServices,
- &gTopOfTemporaryRamPpiGuid,
- 0,
- NULL,
- (VOID **) &TopOfTemporaryRamPpi
- );
- if (EFI_ERROR (Status)) {
- return EFI_NOT_FOUND;
- }
-
- //
- // The entries of BIST information, together with the number of them,
- // reside in the bottom of stack, left untouched by normal stack operation.
- // This routine copies the BIST information to the buffer pointed by
- // PlatformInformationRecord for output.
- //
- TopOfTemporaryRam = (UINT32)(UINTN)TopOfTemporaryRamPpi - sizeof (UINT32);
- TopOfTemporaryRam -= sizeof(UINT32) * 2;
- Count = *((UINT32 *)(UINTN) (TopOfTemporaryRam - sizeof (UINT32)));
- Size = Count * sizeof (IA32_HANDOFF_STATUS);
-
- if ((*StructureSize) < (UINT64) Size) {
- *StructureSize = Size;
- return EFI_BUFFER_TOO_SMALL;
- }
-
- *StructureSize = Size;
- Bist = (UINT32 *) (TopOfTemporaryRam - sizeof (UINT32) - Size);
-
- CopyMem (PlatformInformationRecord, Bist, Size);
-
- return EFI_SUCCESS;
-}
diff --git a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecRamInitData.c b/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecRamInitData.c
deleted file mode 100644
index b356327b4c..0000000000
--- a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecRamInitData.c
+++ /dev/null
@@ -1,36 +0,0 @@
-/** @file
- Provide TempRamInitParams data.
-
-Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
-SPDX-License-Identifier: BSD-2-Clause-Patent
-
-**/
-
-#include <Library/PcdLib.h>
-#include <FspEas.h>
-#include "FsptCoreUpd.h"
-
-typedef struct {
- FSP_UPD_HEADER FspUpdHeader;
- FSPT_CORE_UPD FsptCoreUpd;
-} FSPT_UPD_CORE_DATA;
-
-GLOBAL_REMOVE_IF_UNREFERENCED CONST FSPT_UPD_CORE_DATA FsptUpdDataPtr = {
- {
- 0x4450555F54505346,
- 0x00,
- { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
- }
- },
- {
- ((UINT32)FixedPcdGet64 (PcdCpuMicrocodePatchAddress) + FixedPcdGet32 (PcdFlashMicrocodeOffset)),
- ((UINT32)FixedPcdGet64 (PcdCpuMicrocodePatchRegionSize) - FixedPcdGet32 (PcdFlashMicrocodeOffset)),
- 0, // Set CodeRegionBase as 0, so that caching will be 4GB-(CodeRegionSize > LLCSize ? LLCSize : CodeRegionSize) will be used.
- FixedPcdGet32 (PcdFlashCodeCacheSize),
- { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
- }
- }
-};
-
diff --git a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecTempRamDone.c b/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecTempRamDone.c
deleted file mode 100644
index 922e4ec204..0000000000
--- a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecTempRamDone.c
+++ /dev/null
@@ -1,73 +0,0 @@
-/** @file
- Provide SecTemporaryRamDone function.
-
-Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR>
-SPDX-License-Identifier: BSD-2-Clause-Patent
-
-**/
-
-#include <PiPei.h>
-
-#include <Ppi/TemporaryRamDone.h>
-#include <Ppi/TempRamExitPpi.h>
-
-#include <Library/BaseMemoryLib.h>
-#include <Library/DebugLib.h>
-#include <Library/PcdLib.h>
-#include <Library/DebugAgentLib.h>
-#include <Library/FspWrapperPlatformLib.h>
-#include <Library/FspWrapperApiLib.h>
-#include <Library/BoardInitLib.h>
-#include <Library/PeiServicesTablePointerLib.h>
-
-/**
-This interface disables temporary memory in SEC Phase.
-**/
-VOID
-EFIAPI
-SecPlatformDisableTemporaryMemory (
- VOID
- )
-{
- EFI_STATUS Status;
- VOID *TempRamExitParam;
- CONST EFI_PEI_SERVICES **PeiServices;
- FSP_TEMP_RAM_EXIT_PPI *TempRamExitPpi;
-
- DEBUG ((DEBUG_INFO, "SecPlatformDisableTemporaryMemory enter\n"));
-
- Status = BoardInitBeforeTempRamExit ();
- ASSERT_EFI_ERROR (Status);
-
- if (PcdGet8 (PcdFspModeSelection) == 1) {
- //
- // FSP API mode
- //
- TempRamExitParam = UpdateTempRamExitParam ();
- Status = CallTempRamExit (TempRamExitParam);
- DEBUG ((DEBUG_INFO, "TempRamExit status: 0x%x\n", Status));
- ASSERT_EFI_ERROR (Status);
- } else {
- //
- // FSP Dispatch mode
- //
- PeiServices = GetPeiServicesTablePointer ();
- Status = (*PeiServices)->LocatePpi (
- PeiServices,
- &gFspTempRamExitPpiGuid,
- 0,
- NULL,
- (VOID **) &TempRamExitPpi
- );
- ASSERT_EFI_ERROR (Status);
- if (EFI_ERROR (Status)) {
- return;
- }
- TempRamExitPpi->TempRamExit (NULL);
- }
-
- Status = BoardInitAfterTempRamExit ();
- ASSERT_EFI_ERROR (Status);
-
- return ;
-}
diff --git a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.dsc b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.dsc
index 2bc2b4126b..acdc31e708 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.dsc
+++ b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.dsc
@@ -126,7 +126,7 @@
#######################################
GpioExpanderLib|$(PLATFORM_BOARD_PACKAGE)/Library/BaseGpioExpanderLib/BaseGpioExpanderLib.inf
I2cAccessLib|$(PLATFORM_BOARD_PACKAGE)/Library/PeiI2cAccessLib/PeiI2cAccessLib.inf
- PlatformSecLib|$(PLATFORM_BOARD_PACKAGE)/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecFspWrapperPlatformSecLib.inf
+ PlatformSecLib|$(PLATFORM_PACKAGE)/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecFspWrapperPlatformSecLib.inf
# Thunderbolt
!if gKabylakeOpenBoardPkgTokenSpaceGuid.PcdTbtEnable == TRUE
diff --git a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc
index 77e4a6a610..4b07c0a684 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc
+++ b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc
@@ -166,7 +166,7 @@
EcLib|$(PLATFORM_BOARD_PACKAGE)/Library/BaseEcLib/BaseEcLib.inf
GpioExpanderLib|$(PLATFORM_BOARD_PACKAGE)/Library/BaseGpioExpanderLib/BaseGpioExpanderLib.inf
I2cAccessLib|$(PLATFORM_BOARD_PACKAGE)/Library/PeiI2cAccessLib/PeiI2cAccessLib.inf
- PlatformSecLib|$(PLATFORM_BOARD_PACKAGE)/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecFspWrapperPlatformSecLib.inf
+ PlatformSecLib|$(PLATFORM_PACKAGE)/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecFspWrapperPlatformSecLib.inf
# Thunderbolt
!if gKabylakeOpenBoardPkgTokenSpaceGuid.PcdTbtEnable == TRUE
--
2.24.0.windows.2
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Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
> -----Original Message-----
> From: Desimone, Nathaniel L <nathaniel.l.desimone@intel.com>
> Sent: Thursday, November 21, 2019 4:59 PM
> To: devel@edk2.groups.io
> Cc: Chiu, Chasel <chasel.chiu@intel.com>; Kubacki, Michael A
> <michael.a.kubacki@intel.com>; Jeremy Soller <jeremy@system76.com>
> Subject: [edk2-platforms] [PATCH V2 13/14] KabylakeOpenBoardPkg: Remove
> SecFspWrapperPlatformSecLib override
>
> Cc: Chasel Chiu <chasel.chiu@intel.com>
> Cc: Michael Kubacki <michael.a.kubacki@intel.com>
> Cc: Jeremy Soller <jeremy@system76.com>
> Signed-off-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
> ---
> .../FspWrapperPlatformSecLib.c | 186 ---------
> .../SecFspWrapperPlatformSecLib/FsptCoreUpd.h | 40 --
> .../SecFspWrapperPlatformSecLib/Ia32/Fsp.h | 42 --
> .../Ia32/PeiCoreEntry.nasm | 130 -------
> .../Ia32/SecEntry.nasm | 361 ------------------
> .../Ia32/Stack.nasm | 72 ----
> .../PlatformInit.c | 47 ---
> .../SecFspWrapperPlatformSecLib.inf | 97 -----
> .../SecGetPerformance.c | 89 -----
> .../SecPlatformInformation.c | 78 ----
> .../SecRamInitData.c | 36 --
> .../SecTempRamDone.c | 73 ----
> .../GalagoPro3/OpenBoardPkg.dsc | 2 +-
> .../KabylakeRvp3/OpenBoardPkg.dsc | 2 +-
> 14 files changed, 2 insertions(+), 1253 deletions(-) delete mode 100644
> Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperP
> latformSecLib/FspWrapperPlatformSecLib.c
> delete mode 100644
> Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperP
> latformSecLib/FsptCoreUpd.h
> delete mode 100644
> Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperP
> latformSecLib/Ia32/Fsp.h
> delete mode 100644
> Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperP
> latformSecLib/Ia32/PeiCoreEntry.nasm
> delete mode 100644
> Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperP
> latformSecLib/Ia32/SecEntry.nasm
> delete mode 100644
> Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperP
> latformSecLib/Ia32/Stack.nasm
> delete mode 100644
> Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperP
> latformSecLib/PlatformInit.c
> delete mode 100644
> Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperP
> latformSecLib/SecFspWrapperPlatformSecLib.inf
> delete mode 100644
> Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperP
> latformSecLib/SecGetPerformance.c
> delete mode 100644
> Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperP
> latformSecLib/SecPlatformInformation.c
> delete mode 100644
> Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperP
> latformSecLib/SecRamInitData.c
> delete mode 100644
> Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperP
> latformSecLib/SecTempRamDone.c
>
> diff --git
> a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrappe
> rPlatformSecLib/FspWrapperPlatformSecLib.c
> b/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrappe
> rPlatformSecLib/FspWrapperPlatformSecLib.c
> deleted file mode 100644
> index d40eecae95..0000000000
> ---
> a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrappe
> rPlatformSecLib/FspWrapperPlatformSecLib.c
> +++ /dev/null
> @@ -1,186 +0,0 @@
> -/** @file- Provide FSP wrapper platform sec related function.--Copyright (c)
> 2017 - 2019, Intel Corporation. All rights
> reserved.<BR>-SPDX-License-Identifier: BSD-2-Clause-Patent--**/--#include
> <PiPei.h>--#include <Ppi/SecPlatformInformation.h>-#include
> <Ppi/SecPerformance.h>-#include <Ppi/FirmwareVolumeInfo.h>-#include
> <Ppi/TopOfTemporaryRam.h>-#include <Ppi/PeiCoreFvLocation.h>-#include
> <Guid/FirmwareFileSystem2.h>--#include <Library/LocalApicLib.h>-#include
> <Library/BaseMemoryLib.h>-#include <Library/DebugLib.h>-#include
> <Library/IoLib.h>--/**- This interface conveys state information out of the
> Security (SEC) phase into PEI.-- @param[in] PeiServices
> Pointer to the PEI Services Table.- @param[in,out] StructureSize
> Pointer to the variable describing size of the input buffer.- @param[out]
> PlatformInformationRecord Pointer to the
> EFI_SEC_PLATFORM_INFORMATION_RECORD.-- @retval EFI_SUCCESS
> The data was successfully returned.- @retval EFI_BUFFER_TOO_SMALL
> The buffer was too small.--**/-EFI_STATUS-EFIAPI-SecPlatformInformation (-
> IN CONST EFI_PEI_SERVICES **PeiServices,- IN OUT
> UINT64 *StructureSize,- OUT
> EFI_SEC_PLATFORM_INFORMATION_RECORD
> *PlatformInformationRecord- );--/**- This interface conveys performance
> information out of the Security (SEC) phase into PEI.-- This service is
> published by the SEC phase. The SEC phase handoff has an optional-
> EFI_PEI_PPI_DESCRIPTOR list as its final argument when control is passed
> from SEC into the- PEI Foundation. As such, if the platform supports
> collecting performance data in SEC,- this information is encapsulated into
> the data structure abstracted by this service.- This information is collected
> for the boot-strap processor (BSP) on IA-32.-- @param[in] PeiServices
> The pointer to the PEI Services Table.- @param[in] This The
> pointer to this instance of the PEI_SEC_PERFORMANCE_PPI.- @param[out]
> Performance The pointer to performance data collected in SEC phase.--
> @retval EFI_SUCCESS The data was successfully
> returned.--**/-EFI_STATUS-EFIAPI-SecGetPerformance (- IN CONST
> EFI_PEI_SERVICES **PeiServices,- IN
> PEI_SEC_PERFORMANCE_PPI *This,- OUT
> FIRMWARE_SEC_PERFORMANCE
> *Performance- );--PEI_SEC_PERFORMANCE_PPI mSecPerformancePpi = {-
> SecGetPerformance-};--EFI_PEI_CORE_FV_LOCATION_PPI
> mPeiCoreFvLocationPpi = {- (VOID *) (UINTN) FixedPcdGet32
> (PcdFspmBaseAddress)-};--EFI_PEI_PPI_DESCRIPTOR
> mPeiCoreFvLocationPpiList[] = {- {- EFI_PEI_PPI_DESCRIPTOR_PPI,-
> &gEfiPeiCoreFvLocationPpiGuid,-
> &mPeiCoreFvLocationPpi- }-};--EFI_PEI_PPI_DESCRIPTOR
> mPeiSecPlatformPpi[] = {- {- EFI_PEI_PPI_DESCRIPTOR_PPI,-
> &gTopOfTemporaryRamPpiGuid,- NULL // To be patched later.- },- {-
> EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,-
> &gPeiSecPerformancePpiGuid,- &mSecPerformancePpi- },-};--#define
> LEGACY_8259_MASK_REGISTER_MASTER 0x21-#define
> LEGACY_8259_MASK_REGISTER_SLAVE 0xA1-#define
> LEGACY_8259_EDGE_LEVEL_TRIGGERED_REGISTER_MASTER 0x4D0-#define
> LEGACY_8259_EDGE_LEVEL_TRIGGERED_REGISTER_SLAVE 0x4D1--/**-
> Write to mask and edge/level triggered registers of master and slave 8259
> PICs.-- @param[in] Mask low byte for master PIC mask register,-
> high byte for slave PIC mask register.- @param[in] EdgeLevel low byte
> for master PIC edge/level triggered register,-
> high byte for slave PIC edge/level triggered
> register.--**/-VOID-Interrupt8259WriteMask (- IN UINT16 Mask,- IN
> UINT16 EdgeLevel- )-{- IoWrite8
> (LEGACY_8259_MASK_REGISTER_MASTER, (UINT8) Mask);- IoWrite8
> (LEGACY_8259_MASK_REGISTER_SLAVE, (UINT8) (Mask >> 8));- IoWrite8
> (LEGACY_8259_EDGE_LEVEL_TRIGGERED_REGISTER_MASTER, (UINT8)
> EdgeLevel);- IoWrite8
> (LEGACY_8259_EDGE_LEVEL_TRIGGERED_REGISTER_SLAVE, (UINT8)
> (EdgeLevel >> 8));-}--/**- A developer supplied function to perform
> platform specific operations.-- It's a developer supplied function to
> perform any operations appropriate to a- given platform. It's invoked just
> before passing control to PEI core by SEC- core. Platform developer may
> modify the SecCoreData passed to PEI Core.- It returns a platform specific
> PPI list that platform wishes to pass to PEI core.- The Generic SEC core
> module will merge this list to join the final list passed to- PEI core.--
> @param[in,out] SecCoreData The same parameter as passing to
> PEI core. It- could be
> overridden by this function.-- @return The platform specific PPI list to be
> passed to PEI core or- NULL if there is no need of such platform
> specific PPI list.--**/-EFI_PEI_PPI_DESCRIPTOR *-EFIAPI-SecPlatformMain (-
> IN OUT EFI_SEC_PEI_HAND_OFF *SecCoreData- )-{-
> EFI_PEI_PPI_DESCRIPTOR *PpiList;- UINT8
> TopOfTemporaryRamPpiIndex;- UINT8
> *CopyDestinationPointer;-- DEBUG ((DEBUG_INFO, "FSP Wrapper
> BootFirmwareVolumeBase - 0x%x\n",
> SecCoreData->BootFirmwareVolumeBase));- DEBUG ((DEBUG_INFO, "FSP
> Wrapper BootFirmwareVolumeSize - 0x%x\n",
> SecCoreData->BootFirmwareVolumeSize));- DEBUG ((DEBUG_INFO, "FSP
> Wrapper TemporaryRamBase - 0x%x\n",
> SecCoreData->TemporaryRamBase));- DEBUG ((DEBUG_INFO, "FSP Wrapper
> TemporaryRamSize - 0x%x\n", SecCoreData->TemporaryRamSize));-
> DEBUG ((DEBUG_INFO, "FSP Wrapper PeiTemporaryRamBase - 0x%x\n",
> SecCoreData->PeiTemporaryRamBase));- DEBUG ((DEBUG_INFO, "FSP
> Wrapper PeiTemporaryRamSize - 0x%x\n",
> SecCoreData->PeiTemporaryRamSize));- DEBUG ((DEBUG_INFO, "FSP
> Wrapper StackBase - 0x%x\n", SecCoreData->StackBase));-
> DEBUG ((DEBUG_INFO, "FSP Wrapper StackSize - 0x%x\n",
> SecCoreData->StackSize));-- InitializeApicTimer (0, (UINT32) -1, TRUE, 5);--
> //- // Set all 8259 interrupts to edge triggered and disabled- //-
> Interrupt8259WriteMask (0xFFFF, 0x0000);-- //- // Use middle of Heap as
> temp buffer, it will be copied by caller.- // Do not use Stack, because it will
> cause wrong calculation on stack by PeiCore- //- PpiList = (VOID *)((UINTN)
> SecCoreData->PeiTemporaryRamBase + (UINTN)
> SecCoreData->PeiTemporaryRamSize/2);- CopyDestinationPointer = (UINT8
> *) PpiList;- TopOfTemporaryRamPpiIndex = 0;- if (PcdGet8
> (PcdFspModeSelection) == 0) {- //- // In Dispatch mode, wrapper
> should provide PeiCoreFvLocationPpi.- //- CopyMem
> (CopyDestinationPointer, mPeiCoreFvLocationPpiList, sizeof
> (mPeiCoreFvLocationPpiList));- TopOfTemporaryRamPpiIndex = 1;-
> CopyDestinationPointer += sizeof (mPeiCoreFvLocationPpiList);- }-
> CopyMem (CopyDestinationPointer, mPeiSecPlatformPpi,
> sizeof(mPeiSecPlatformPpi));- //- // Patch TopOfTemporaryRamPpi- //-
> PpiList[TopOfTemporaryRamPpiIndex].Ppi = (VOID *)((UINTN)
> SecCoreData->TemporaryRamBase + SecCoreData->TemporaryRamSize);--
> return PpiList;-}diff --git
> a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrappe
> rPlatformSecLib/FsptCoreUpd.h
> b/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrappe
> rPlatformSecLib/FsptCoreUpd.h
> deleted file mode 100644
> index 7c0f605b92..0000000000
> ---
> a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrappe
> rPlatformSecLib/FsptCoreUpd.h
> +++ /dev/null
> @@ -1,40 +0,0 @@
> -/** @file--Copyright (c) 2017, Intel Corporation. All rights
> reserved.<BR>-SPDX-License-Identifier: BSD-2-Clause-Patent--**/--#ifndef
> __FSPT_CORE_UPD_H__-#define __FSPT_CORE_UPD_H__--#pragma
> pack(1)--/** Fsp T Core UPD-**/-typedef struct {--/** Offset 0x0020-**/-
> UINT32 MicrocodeRegionBase;--/** Offset
> 0x0024-**/- UINT32 MicrocodeRegionSize;--/**
> Offset 0x0028-**/- UINT32 CodeRegionBase;--/**
> Offset 0x002C-**/- UINT32 CodeRegionSize;--/**
> Offset 0x0030-**/- UINT8 Reserved[16];-}
> FSPT_CORE_UPD;--#pragma pack()--#endifdiff --git
> a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrappe
> rPlatformSecLib/Ia32/Fsp.h
> b/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrappe
> rPlatformSecLib/Ia32/Fsp.h
> deleted file mode 100644
> index 9f6cdcf476..0000000000
> ---
> a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrappe
> rPlatformSecLib/Ia32/Fsp.h
> +++ /dev/null
> @@ -1,42 +0,0 @@
> -/** @file- Fsp related definitions--Copyright (c) 2017, Intel Corporation. All
> rights reserved.<BR>-SPDX-License-Identifier:
> BSD-2-Clause-Patent--**/--#ifndef __FSP_H__-#define __FSP_H__--//-// Fv
> Header-//-#define FVH_SIGINATURE_OFFSET 0x28-#define
> FVH_SIGINATURE_VALID_VALUE 0x4856465F // valid
> signature:_FVH-#define FVH_HEADER_LENGTH_OFFSET 0x30-#define
> FVH_EXTHEADER_OFFSET_OFFSET 0x34-#define
> FVH_EXTHEADER_SIZE_OFFSET 0x10--//-// Ffs Header-//-#define
> FSP_HEADER_GUID_DWORD1 0x912740BE-#define
> FSP_HEADER_GUID_DWORD2 0x47342284-#define
> FSP_HEADER_GUID_DWORD3 0xB08471B9-#define
> FSP_HEADER_GUID_DWORD4 0x0C3F3527-#define
> FFS_HEADER_SIZE_VALUE 0x18--//-// Section Header-//-#define
> SECTION_HEADER_TYPE_OFFSET 0x03-#define
> RAW_SECTION_HEADER_SIZE_VALUE 0x04--//-// Fsp Header-//-#define
> FSP_HEADER_IMAGEBASE_OFFSET 0x1C-#define
> FSP_HEADER_TEMPRAMINIT_OFFSET 0x30--#endifdiff --git
> a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrappe
> rPlatformSecLib/Ia32/PeiCoreEntry.nasm
> b/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrappe
> rPlatformSecLib/Ia32/PeiCoreEntry.nasm
> deleted file mode 100644
> index 5c5b788085..0000000000
> ---
> a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrappe
> rPlatformSecLib/Ia32/PeiCoreEntry.nasm
> +++ /dev/null
> @@ -1,130 +0,0 @@
> -;-------------------------------------------------------------------------------;-; Copyright (c)
> 2019, Intel Corporation. All rights reserved.<BR>-; SPDX-License-Identifier:
> BSD-2-Clause-Patent-;-; Module Name:-;-; PeiCoreEntry.nasm-;-; Abstract:-;-;
> Find and call
> SecStartup-;-;--------------------------------------------------------------------------------SECTI
> ON .text--extern ASM_PFX(SecStartup)-extern ASM_PFX(PlatformInit)--global
> ASM_PFX(CallPeiCoreEntryPoint)-ASM_PFX(CallPeiCoreEntryPoint):- ;- ;
> Obtain the hob list pointer- ;- mov eax, [esp+4]- ;- ; Obtain the
> stack information- ; ECX: start of range- ; EDX: end of range- ;-
> mov ecx, [esp+8]- mov edx, [esp+0xC]-- ;- ; Platform init- ;-
> pushad- push edx- push ecx- push eax- call ASM_PFX(PlatformInit)-
> pop eax- pop eax- pop eax- popad-- ;- ; Set stack top
> pointer- ;- mov esp, edx-- ;- ; Push the hob list pointer- ;-
> push eax-- ;- ; Save the value- ; ECX: start of range- ; EDX:
> end of range- ;- mov ebp, esp- push ecx- push
> edx-- ;- ; Push processor count to stack first, then BIST status (AP then
> BSP)- ;- mov eax, 1- cpuid- shr ebx, 16- and ebx,
> 0xFF- cmp bl, 1- jae PushProcessorCount-- ;- ; Some
> processors report 0 logical processors. Effectively 0 = 1.- ; So we fix up
> the processor count- ;- inc ebx--PushProcessorCount:- push
> ebx-- ;- ; We need to implement a long-term solution for BIST capture.
> For now, we just copy BSP BIST- ; for all processor threads- ;- xor
> ecx, ecx- mov cl, bl-PushBist:- movd eax, mm0- push eax-
> loop PushBist-- ; Save Time-Stamp Counter- movd eax, mm5- push
> eax-- movd eax, mm6- push eax-- ;- ; Pass entry point of the PEI
> core- ;- mov edi, 0xFFFFFFE0- push DWORD [edi]-- ;- ; Pass
> BFV into the PEI Core- ;- mov edi, 0xFFFFFFFC- push DWORD
> [edi]-- ;- ; Pass stack size into the PEI Core- ;- mov ecx, [ebp - 4]-
> mov edx, [ebp - 8]- push ecx ; RamBase-- sub edx,
> ecx- push edx ; RamSize-- ;- ; Pass Control into the PEI
> Core- ;- call ASM_PFX(SecStartup)-diff --git
> a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrappe
> rPlatformSecLib/Ia32/SecEntry.nasm
> b/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrappe
> rPlatformSecLib/Ia32/SecEntry.nasm
> deleted file mode 100644
> index 7f6d771e41..0000000000
> ---
> a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrappe
> rPlatformSecLib/Ia32/SecEntry.nasm
> +++ /dev/null
> @@ -1,361 +0,0 @@
> -;-------------------------------------------------------------------------------;-; Copyright (c)
> 2019, Intel Corporation. All rights reserved.<BR>-; SPDX-License-Identifier:
> BSD-2-Clause-Patent-; Module Name:-;-; SecEntry.nasm-;-; Abstract:-;-;
> This is the code that goes from real-mode to protected mode.-; It
> consumes the reset vector, calls TempRamInit API from FSP
> binary.-;-;--------------------------------------------------------------------------------#include
> "Fsp.h"--SECTION .text--extern ASM_PFX(CallPeiCoreEntryPoint)-extern
> ASM_PFX(FsptUpdDataPtr)-extern ASM_PFX(BoardBeforeTempRamInit)-;
> Pcds-extern ASM_PFX(PcdGet32 (PcdFspTemporaryRamSize))-extern
> ASM_PFX(PcdGet32
> (PcdFsptBaseAddress))--;------------------------------------------------------------------------
> -----;-; Procedure: _ModuleEntryPoint-;-; Input: None-;-; Output:
> None-;-; Destroys: Assume all registers-;-; Description:-;-; Transition
> to non-paged flat-model protected mode from a-; hard-coded GDT that
> provides exactly two descriptors.-; This is a bare bones transition to
> protected mode only-; used for a while in PEI and possibly DXE.-;-;
> After enabling protected mode, a far jump is executed to-; transfer to PEI
> using the newly loaded GDT.-;-; Return: None-;-; MMX Usage:-;
> MM0 = BIST State-; MM5 = Save time-stamp counter value
> high32bit-; MM6 = Save time-stamp counter value
> low32bit.-;-;------------------------------------------------------------------------------BITS
> 16-align 4-global
> ASM_PFX(_ModuleEntryPoint)-ASM_PFX(_ModuleEntryPoint):-
> fninit ; clear any pending Floating
> point exceptions- ;- ; Store the BIST value in mm0- ;- movd mm0,
> eax- cli-- ;- ; Check INIT# is asserted by port 0xCF9- ;- mov dx, 0CF9h-
> in al, dx- cmp al, 04h- jnz NotWarmStart--- ;- ; @note Issue warm
> reset, since if CPU only reset is issued not all MSRs are restored to their
> defaults- ;- mov dx, 0CF9h- mov al, 06h- out dx,
> al--NotWarmStart:- ;- ; Save time-stamp counter value- ; rdtsc load 64bit
> time-stamp counter to EDX:EAX- ;- rdtsc- movd mm5, edx- movd
> mm6, eax-- ;- ; Load the GDT table in GdtDesc- ;- mov esi,
> GdtDesc- DB 66h- lgdt [cs:si]-- ;- ; Transition to 16 bit
> protected mode- ;- mov eax, cr0 ; Get control
> register 0- or eax, 00000003h ; Set PE bit (bit #0) &
> MP bit (bit #1)- mov cr0, eax ; Activate
> protected mode-- mov eax, cr4 ; Get control
> register 4- or eax, 00000600h ; Set OSFXSR bit (bit #9)
> & OSXMMEXCPT bit (bit #10)- mov cr4, eax-- ;- ; Now we're in 16
> bit protected mode- ; Set up the selectors for 32 bit protected mode
> entry- ;- mov ax, SYS_DATA_SEL- mov ds, ax- mov es,
> ax- mov fs, ax- mov gs, ax- mov ss, ax-- ;- ; Transition
> to Flat 32 bit protected mode- ; The jump to a far pointer causes the
> transition to 32 bit mode- ;- mov esi, ProtectedModeEntryLinearAddress-
> jmp dword far
> [cs:si]--;-----------------------------------------------------------------------------;-; Procedure:
> ProtectedModeEntryPoint-;-; Input: None-;-; Output: None-;-;
> Destroys: Assume all registers-;-; Description:-;-; This function handles:-;
> Call two basic APIs from FSP binary-; Initializes stack with some early data
> (BIST, PEI entry, etc)-;-; Return:
> None-;-;------------------------------------------------------------------------------BITS 32-align
> 4-ProtectedModeEntryPoint:- ;- ; Early board hooks- ;- mov esp,
> BoardBeforeTempRamInitRet- jmp
> ASM_PFX(BoardBeforeTempRamInit)--BoardBeforeTempRamInitRet:-- ;
> Find the fsp info header- mov edi, [ASM_PFX(PcdGet32
> (PcdFsptBaseAddress))]-- mov eax, dword [edi +
> FVH_SIGINATURE_OFFSET]- cmp eax, FVH_SIGINATURE_VALID_VALUE-
> jnz FspHeaderNotFound-- xor eax, eax- mov ax, word [edi +
> FVH_EXTHEADER_OFFSET_OFFSET]- cmp ax, 0- jnz
> FspFvExtHeaderExist-- xor eax, eax- mov ax, word [edi +
> FVH_HEADER_LENGTH_OFFSET] ; Bypass Fv Header- add edi, eax-
> jmp FspCheckFfsHeader--FspFvExtHeaderExist:- add edi, eax- mov
> eax, dword [edi + FVH_EXTHEADER_SIZE_OFFSET] ; Bypass Ext Fv Header-
> add edi, eax-- ; Round up to 8 byte alignment- mov eax, edi- and
> al, 07h- jz FspCheckFfsHeader-- and edi, 0FFFFFFF8h- add edi,
> 08h--FspCheckFfsHeader:- ; Check the ffs guid- mov eax, dword [edi]-
> cmp eax, FSP_HEADER_GUID_DWORD1- jnz FspHeaderNotFound--
> mov eax, dword [edi + 4]- cmp eax, FSP_HEADER_GUID_DWORD2- jnz
> FspHeaderNotFound-- mov eax, dword [edi + 8]- cmp eax,
> FSP_HEADER_GUID_DWORD3- jnz FspHeaderNotFound-- mov eax,
> dword [edi + 0Ch]- cmp eax, FSP_HEADER_GUID_DWORD4- jnz
> FspHeaderNotFound-- add edi, FFS_HEADER_SIZE_VALUE ; Bypass
> the ffs header-- ; Check the section type as raw section- mov al, byte
> [edi + SECTION_HEADER_TYPE_OFFSET]- cmp al, 019h- jnz
> FspHeaderNotFound-- add edi, RAW_SECTION_HEADER_SIZE_VALUE ;
> Bypass the section header- jmp FspHeaderFound--FspHeaderNotFound:-
> jmp $--FspHeaderFound:- ; Get the fsp TempRamInit Api address- mov
> eax, dword [edi + FSP_HEADER_IMAGEBASE_OFFSET]- add eax, dword [edi
> + FSP_HEADER_TEMPRAMINIT_OFFSET]-- ; Setup the hardcode stack- mov
> esp, TempRamInitStack-- ; Call the fsp TempRamInit Api- jmp
> eax--TempRamInitDone:- cmp eax, 8000000Eh ;Check if
> EFI_NOT_FOUND returned. Error code for Microcode Update not found.- je
> CallSecFspInit ;If microcode not found, don't hang, but continue.--
> cmp eax, 0 ;Check if EFI_SUCCESS retuned.- jnz
> FspApiFailed-- ; ECX: start of range- ; EDX: end of
> range-CallSecFspInit:- sub edx, [ASM_PFX(PcdGet32
> (PcdFspTemporaryRamSize))] ; TemporaryRam for FSP- xor eax, eax-
> mov esp, edx-- ; Align the stack at DWORD- add esp, 3- and
> esp, 0FFFFFFFCh-- push edx- push ecx- push eax ; zero - no
> hob list yet- call ASM_PFX(CallPeiCoreEntryPoint)--FspApiFailed:- jmp
> $--align 10h-TempRamInitStack:- DD TempRamInitDone- DD
> ASM_PFX(FsptUpdDataPtr); TempRamInitParams--;-; ROM-based
> Global-Descriptor Table for the Tiano PEI Phase-;-align 16-global
> ASM_PFX(BootGdtTable)--;-; GDT[0]: 0x00: Null entry, never used.-;-NULL_SEL
> EQU $ - GDT_BASE ; Selector [0]-GDT_BASE:-ASM_PFX(BootGdtTable):-
> DD 0- DD 0-;-; Linear data segment
> descriptor-;-LINEAR_SEL EQU $ - GDT_BASE ; Selector [0x8]-
> DW 0FFFFh ; limit 0xFFFFF- DW
> 0 ; base 0- DB 0- DB
> 092h ; present, ring 0, data, expand-up,
> writable- DB 0CFh ; page-granular,
> 32-bit- DB 0-;-; Linear code segment descriptor-;-LINEAR_CODE_SEL
> EQU $ - GDT_BASE ; Selector [0x10]- DW
> 0FFFFh ; limit 0xFFFFF- DW
> 0 ; base 0- DB 0- DB
> 09Bh ; present, ring 0, data, expand-up,
> not-writable- DB 0CFh ; page-granular,
> 32-bit- DB 0-;-; System data segment descriptor-;-SYS_DATA_SEL
> EQU $ - GDT_BASE ; Selector [0x18]- DW
> 0FFFFh ; limit 0xFFFFF- DW
> 0 ; base 0- DB 0- DB
> 093h ; present, ring 0, data, expand-up,
> not-writable- DB 0CFh ; page-granular,
> 32-bit- DB 0--;-; System code segment descriptor-;-SYS_CODE_SEL
> EQU $ - GDT_BASE ; Selector [0x20]- DW
> 0FFFFh ; limit 0xFFFFF- DW
> 0 ; base 0- DB 0- DB
> 09Ah ; present, ring 0, data, expand-up,
> writable- DB 0CFh ; page-granular,
> 32-bit- DB 0-;-; Spare segment descriptor-;-SYS16_CODE_SEL EQU
> $ - GDT_BASE ; Selector [0x28]- DW
> 0FFFFh ; limit 0xFFFFF- DW
> 0 ; base 0- DB
> 0Eh ; Changed from F000 to E000.- DB
> 09Bh ; present, ring 0, code, expand-up,
> writable- DB 00h ; byte-granular,
> 16-bit- DB 0-;-; Spare segment descriptor-;-SYS16_DATA_SEL EQU
> $ - GDT_BASE ; Selector [0x30]- DW
> 0FFFFh ; limit 0xFFFF- DW
> 0 ; base 0- DB 0- DB
> 093h ; present, ring 0, data, expand-up,
> not-writable- DB 00h ; byte-granular,
> 16-bit- DB 0--;-; Spare segment descriptor-;-SPARE5_SEL
> EQU $ - GDT_BASE ; Selector [0x38]- DW
> 0 ; limit 0- DW
> 0 ; base 0- DB 0- DB
> 0 ; present, ring 0, data, expand-up,
> writable- DB 0 ; page-granular,
> 32-bit- DB 0-GDT_SIZE EQU $ - GDT_BASE ; Size, in
> bytes--;-; GDT Descriptor-;-GdtDesc: ;
> GDT descriptor- DW GDT_SIZE - 1 ; GDT limit-
> DD GDT_BASE ; GDT base
> address---ProtectedModeEntryLinearAddress:-ProtectedModeEntryLinear:-
> DD ProtectedModeEntryPoint ; Offset of our 32 bit code- DW
> LINEAR_CODE_SELdiff --git
> a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrappe
> rPlatformSecLib/Ia32/Stack.nasm
> b/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrappe
> rPlatformSecLib/Ia32/Stack.nasm
> deleted file mode 100644
> index 47db32d64c..0000000000
> ---
> a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrappe
> rPlatformSecLib/Ia32/Stack.nasm
> +++ /dev/null
> @@ -1,72 +0,0 @@
> -;-------------------------------------------------------------------------------;-; Copyright (c)
> 2019, Intel Corporation. All rights reserved.<BR>-; SPDX-License-Identifier:
> BSD-2-Clause-Patent-; Abstract:-;-; Switch the stack from temporary
> memory to permanent
> memory.-;-;--------------------------------------------------------------------------------
> SECTION .text--;-------------------------------------------------------------------------------;
> VOID-; EFIAPI-; SecSwitchStack (-; UINT32 TemporaryMemoryBase,-;
> UINT32
> PermanentMemoryBase-; );-;---------------------------------------------------------------
> ----------------global
> ASM_PFX(SecSwitchStack)-ASM_PFX(SecSwitchStack):- ;- ; Save three
> register: eax, ebx, ecx- ;- push eax- push ebx- push ecx-
> push edx-- ;- ; !!CAUTION!! this function address's is pushed into
> stack after- ; migration of whole temporary memory, so need save it to
> permanent- ; memory at first!- ;-- mov ebx, [esp +
> 20] ; Save the first parameter- mov ecx, [esp +
> 24] ; Save the second parameter-- ;- ; Save this function's
> return address into permanent memory at first.- ; Then, Fixup the esp
> point to permanent memory- ;- mov eax, esp- sub eax,
> ebx- add eax, ecx- mov edx, dword [esp] ; copy
> pushed register's value to permanent memory- mov dword [eax], edx-
> mov edx, dword [esp + 4]- mov dword [eax + 4], edx- mov
> edx, dword [esp + 8]- mov dword [eax + 8], edx- mov edx,
> dword [esp + 12]- mov dword [eax + 12], edx- mov edx, dword
> [esp + 16] ; Update this function's return address into permanent
> memory- mov dword [eax + 16], edx- mov esp,
> eax ; From now, esp is pointed to permanent
> memory-- ;- ; Fixup the ebp point to permanent memory- ;-
> mov eax, ebp- sub eax, ebx- add eax, ecx- mov ebp,
> eax ; From now, ebp is pointed to permanent memory--
> pop edx- pop ecx- pop ebx- pop eax- ret-diff
> --git
> a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrappe
> rPlatformSecLib/PlatformInit.c
> b/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrappe
> rPlatformSecLib/PlatformInit.c
> deleted file mode 100644
> index ef89e3f310..0000000000
> ---
> a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrappe
> rPlatformSecLib/PlatformInit.c
> +++ /dev/null
> @@ -1,47 +0,0 @@
> -/** @file- Provide platform init function.--Copyright (c) 2017, Intel
> Corporation. All rights reserved.<BR>-SPDX-License-Identifier:
> BSD-2-Clause-Patent--**/---#include <PiPei.h>-#include
> <Library/DebugLib.h>-#include <Library/SerialPortLib.h>-#include
> <Library/SecBoardInitLib.h>-#include <Library/TestPointCheckLib.h>--/**-
> Platform initialization.-- @param[in] FspHobList HobList produced by
> FSP.- @param[in] StartOfRange Start of temporary RAM.- @param[in]
> EndOfRange End of temporary RAM.-**/-VOID-EFIAPI-PlatformInit (- IN
> VOID *FspHobList,- IN VOID
> *StartOfRange,- IN VOID *EndOfRange- )-{- //- //
> Platform initialization- // Enable Serial port here- //- if
> (PcdGetBool(PcdSecSerialPortDebugEnable)) {- SerialPortInitialize
> ();- }-- DEBUG ((DEBUG_INFO, "PrintPeiCoreEntryPointParam in
> PlatformInit\n"));- DEBUG ((DEBUG_INFO, "FspHobList - 0x%x\n",
> FspHobList));- DEBUG ((DEBUG_INFO, "StartOfRange - 0x%x\n",
> StartOfRange));- DEBUG ((DEBUG_INFO, "EndOfRange - 0x%x\n",
> EndOfRange));-- BoardAfterTempRamInit ();--
> TestPointTempMemoryFunction (StartOfRange, EndOfRange);-}diff --git
> a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrappe
> rPlatformSecLib/SecFspWrapperPlatformSecLib.inf
> b/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrappe
> rPlatformSecLib/SecFspWrapperPlatformSecLib.inf
> deleted file mode 100644
> index c99dd5ecdd..0000000000
> ---
> a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrappe
> rPlatformSecLib/SecFspWrapperPlatformSecLib.inf
> +++ /dev/null
> @@ -1,97 +0,0 @@
> -## @file-# Provide FSP wrapper platform sec related function.-#-#
> Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR>-#-#
> SPDX-License-Identifier:
> BSD-2-Clause-Patent-#-#-##--########################################
> ########################################-#-# Defines Section -
> statements that will be processed to create a
> Makefile.-#-######################################################
> ##########################-[Defines]- INF_VERSION
> = 0x00010005- BASE_NAME =
> SecFspWrapperPlatformSecLib- FILE_GUID =
> 4E1C4F95-90EA-47de-9ACC-B8920189A1F5- MODULE_TYPE
> = SEC- VERSION_STRING = 1.0- LIBRARY_CLASS
> = PlatformSecLib---#-# The following information is for reference only and
> not required by the build tools.-#-# VALID_ARCHITECTURES =
> IA32
> X64-#--##########################################################
> ######################-#-# Sources Section - list of files that are required
> for the build to
> succeed.-#-######################################################
> ##########################--[Sources]- FspWrapperPlatformSecLib.c-
> SecRamInitData.c- SecPlatformInformation.c- SecGetPerformance.c-
> SecTempRamDone.c- PlatformInit.c--[Sources.IA32]- Ia32/SecEntry.nasm-
> Ia32/PeiCoreEntry.nasm- Ia32/Stack.nasm-
> Ia32/Fsp.h--######################################################
> ##########################-#-# Package Dependency Section - list of
> Package files that are required for-# this
> module.-#-#######################################################
> #########################--[Packages]- MdePkg/MdePkg.dec-
> MdeModulePkg/MdeModulePkg.dec- UefiCpuPkg/UefiCpuPkg.dec-
> IntelFsp2Pkg/IntelFsp2Pkg.dec-
> IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec-
> MinPlatformPkg/MinPlatformPkg.dec-
> KabylakeSiliconPkg/SiPkg.dec--[LibraryClasses]- LocalApicLib-
> SerialPortLib- FspWrapperPlatformLib- FspWrapperApiLib- BoardInitLib-
> SecBoardInitLib- TestPointCheckLib- PeiServicesTablePointerLib--[Ppis]-
> gEfiSecPlatformInformationPpiGuid ## CONSUMES-
> gPeiSecPerformancePpiGuid ## CONSUMES-
> gTopOfTemporaryRamPpiGuid ## PRODUCES-
> gEfiPeiFirmwareVolumeInfoPpiGuid ## PRODUCES-
> gFspTempRamExitPpiGuid ## CONSUMES--[Pcd]-
> gUefiCpuPkgTokenSpaceGuid.PcdPeiTemporaryRamStackSize
> ## CONSUMES- gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress
> ## CONSUMES- gIntelFsp2PkgTokenSpaceGuid.PcdFspTemporaryRamSize
> ## CONSUMES-
> gMinPlatformPkgTokenSpaceGuid.PcdSecSerialPortDebugEnable
> ## CONSUMES--[FixedPcd]-
> gIntelFsp2WrapperTokenSpaceGuid.PcdCpuMicrocodePatchAddress
> ## CONSUMES-
> gIntelFsp2WrapperTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize
> ## CONSUMES-
> gIntelFsp2WrapperTokenSpaceGuid.PcdFlashMicrocodeOffset
> ## CONSUMES-
> gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheAddress
> ## CONSUMES- gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheSize
> ## CONSUMES- gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress
> ## CONSUMES- gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection
> ## CONSUMESdiff --git
> a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrappe
> rPlatformSecLib/SecGetPerformance.c
> b/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrappe
> rPlatformSecLib/SecGetPerformance.c
> deleted file mode 100644
> index c4eeb2b188..0000000000
> ---
> a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrappe
> rPlatformSecLib/SecGetPerformance.c
> +++ /dev/null
> @@ -1,89 +0,0 @@
> -/** @file- Sample to provide SecGetPerformance function.--Copyright (c)
> 2017, Intel Corporation. All rights reserved.<BR>-SPDX-License-Identifier:
> BSD-2-Clause-Patent--**/--#include <PiPei.h>--#include
> <Ppi/SecPerformance.h>-#include <Ppi/TopOfTemporaryRam.h>--#include
> <Library/BaseMemoryLib.h>-#include <Library/TimerLib.h>-#include
> <Library/DebugLib.h>--/**- This interface conveys performance information
> out of the Security (SEC) phase into PEI.-- This service is published by the
> SEC phase. The SEC phase handoff has an optional-
> EFI_PEI_PPI_DESCRIPTOR list as its final argument when control is passed
> from SEC into the- PEI Foundation. As such, if the platform supports
> collecting performance data in SEC,- this information is encapsulated into
> the data structure abstracted by this service.- This information is collected
> for the boot-strap processor (BSP) on IA-32.-- @param[in] PeiServices
> The pointer to the PEI Services Table.- @param[in] This The
> pointer to this instance of the PEI_SEC_PERFORMANCE_PPI.- @param[out]
> Performance The pointer to performance data collected in SEC phase.--
> @retval EFI_SUCCESS The data was successfully
> returned.--**/-EFI_STATUS-EFIAPI-SecGetPerformance (- IN CONST
> EFI_PEI_SERVICES **PeiServices,- IN
> PEI_SEC_PERFORMANCE_PPI *This,- OUT
> FIRMWARE_SEC_PERFORMANCE *Performance- )-{- UINT32 Size;-
> UINT32 Count;- UINT32 TopOfTemporaryRam;- UINT64
> Ticker;- VOID *TopOfTemporaryRamPpi;- EFI_STATUS Status;--
> DEBUG ((DEBUG_INFO, "SecGetPerformance\n"));-- Status =
> (*PeiServices)->LocatePpi (- PeiServices,-
> &gTopOfTemporaryRamPpiGuid,- 0,-
> NULL,- (VOID **)
> &TopOfTemporaryRamPpi- );- if
> (EFI_ERROR (Status)) {- return EFI_NOT_FOUND;- }- //- //
> |--------------| <- TopOfTemporaryRam - BL- // | List Ptr |- //
> |--------------|- // | BL RAM Start |- // |--------------|- // | BL RAM End
> |- // |--------------|- // |Number of BSPs|- // |--------------|- // |
> BIST |- // |--------------|- // | .... |- // |--------------|- // |
> TSC[63:32] |- // |--------------|- // | TSC[31:00] |- // |--------------|-
> //- TopOfTemporaryRam = (UINT32)(UINTN)TopOfTemporaryRamPpi -
> sizeof(UINT32);- TopOfTemporaryRam -= sizeof(UINT32) * 2;- Count
> = *(UINT32 *) (UINTN) (TopOfTemporaryRam - sizeof (UINT32));- Size
> = Count * sizeof (UINT32);-- Ticker = *(UINT64 *) (UINTN)
> (TopOfTemporaryRam - sizeof (UINT32) - Size - sizeof (UINT32) * 2);-
> Performance->ResetEnd = GetTimeInNanoSecond (Ticker);-- return
> EFI_SUCCESS;-}diff --git
> a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrappe
> rPlatformSecLib/SecPlatformInformation.c
> b/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrappe
> rPlatformSecLib/SecPlatformInformation.c
> deleted file mode 100644
> index 5b94ed2bef..0000000000
> ---
> a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrappe
> rPlatformSecLib/SecPlatformInformation.c
> +++ /dev/null
> @@ -1,78 +0,0 @@
> -/** @file- Provide SecPlatformInformation function.--Copyright (c) 2017,
> Intel Corporation. All rights reserved.<BR>-SPDX-License-Identifier:
> BSD-2-Clause-Patent--**/--#include <PiPei.h>--#include
> <Ppi/SecPlatformInformation.h>-#include
> <Ppi/TopOfTemporaryRam.h>--#include
> <Library/BaseMemoryLib.h>-#include <Library/DebugLib.h>--/**- This
> interface conveys state information out of the Security (SEC) phase into PEI.--
> @param[in] PeiServices Pointer to the PEI Services
> Table.- @param[in,out] StructureSize Pointer to the variable
> describing size of the input buffer.- @param[out]
> PlatformInformationRecord Pointer to the
> EFI_SEC_PLATFORM_INFORMATION_RECORD.-- @retval EFI_SUCCESS
> The data was successfully returned.- @retval EFI_BUFFER_TOO_SMALL
> The buffer was too small.--**/-EFI_STATUS-EFIAPI-SecPlatformInformation (-
> IN CONST EFI_PEI_SERVICES **PeiServices,- IN OUT
> UINT64 *StructureSize,- OUT
> EFI_SEC_PLATFORM_INFORMATION_RECORD
> *PlatformInformationRecord- )-{- UINT32 *Bist;- UINT32
> Size;- UINT32 Count;- UINT32 TopOfTemporaryRam;- VOID
> *TopOfTemporaryRamPpi;- EFI_STATUS Status;-- DEBUG ((DEBUG_INFO,
> "SecPlatformInformation\n"));-- Status = (*PeiServices)->LocatePpi (-
> PeiServices,-
> &gTopOfTemporaryRamPpiGuid,- 0,-
> NULL,- (VOID **)
> &TopOfTemporaryRamPpi- );- if
> (EFI_ERROR (Status)) {- return EFI_NOT_FOUND;- }-- //- // The
> entries of BIST information, together with the number of them,- // reside
> in the bottom of stack, left untouched by normal stack operation.- // This
> routine copies the BIST information to the buffer pointed by- //
> PlatformInformationRecord for output.- //- TopOfTemporaryRam =
> (UINT32)(UINTN)TopOfTemporaryRamPpi - sizeof (UINT32);-
> TopOfTemporaryRam -= sizeof(UINT32) * 2;- Count =
> *((UINT32 *)(UINTN) (TopOfTemporaryRam - sizeof (UINT32)));- Size
> = Count * sizeof (IA32_HANDOFF_STATUS);-- if ((*StructureSize) < (UINT64)
> Size) {- *StructureSize = Size;- return EFI_BUFFER_TOO_SMALL;- }--
> *StructureSize = Size;- Bist = (UINT32 *)
> (TopOfTemporaryRam - sizeof (UINT32) - Size);-- CopyMem
> (PlatformInformationRecord, Bist, Size);-- return EFI_SUCCESS;-}diff --git
> a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrappe
> rPlatformSecLib/SecRamInitData.c
> b/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrappe
> rPlatformSecLib/SecRamInitData.c
> deleted file mode 100644
> index b356327b4c..0000000000
> ---
> a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrappe
> rPlatformSecLib/SecRamInitData.c
> +++ /dev/null
> @@ -1,36 +0,0 @@
> -/** @file- Provide TempRamInitParams data.--Copyright (c) 2017, Intel
> Corporation. All rights reserved.<BR>-SPDX-License-Identifier:
> BSD-2-Clause-Patent--**/--#include <Library/PcdLib.h>-#include
> <FspEas.h>-#include "FsptCoreUpd.h"--typedef struct {- FSP_UPD_HEADER
> FspUpdHeader;- FSPT_CORE_UPD FsptCoreUpd;-}
> FSPT_UPD_CORE_DATA;--GLOBAL_REMOVE_IF_UNREFERENCED CONST
> FSPT_UPD_CORE_DATA FsptUpdDataPtr = {- {- 0x4450555F54505346,-
> 0x00,- { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,-
> 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00- }- },- {-
> ((UINT32)FixedPcdGet64 (PcdCpuMicrocodePatchAddress) + FixedPcdGet32
> (PcdFlashMicrocodeOffset)),- ((UINT32)FixedPcdGet64
> (PcdCpuMicrocodePatchRegionSize) - FixedPcdGet32
> (PcdFlashMicrocodeOffset)),- 0, // Set CodeRegionBase as 0,
> so that caching will be 4GB-(CodeRegionSize > LLCSize ? LLCSize :
> CodeRegionSize) will be used.- FixedPcdGet32 (PcdFlashCodeCacheSize),-
> { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,- 0x00,
> 0x00, 0x00, 0x00, 0x00, 0x00- }- }-};-diff --git
> a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrappe
> rPlatformSecLib/SecTempRamDone.c
> b/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrappe
> rPlatformSecLib/SecTempRamDone.c
> deleted file mode 100644
> index 922e4ec204..0000000000
> ---
> a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrappe
> rPlatformSecLib/SecTempRamDone.c
> +++ /dev/null
> @@ -1,73 +0,0 @@
> -/** @file- Provide SecTemporaryRamDone function.--Copyright (c) 2017 -
> 2019, Intel Corporation. All rights reserved.<BR>-SPDX-License-Identifier:
> BSD-2-Clause-Patent--**/--#include <PiPei.h>--#include
> <Ppi/TemporaryRamDone.h>-#include <Ppi/TempRamExitPpi.h>--#include
> <Library/BaseMemoryLib.h>-#include <Library/DebugLib.h>-#include
> <Library/PcdLib.h>-#include <Library/DebugAgentLib.h>-#include
> <Library/FspWrapperPlatformLib.h>-#include
> <Library/FspWrapperApiLib.h>-#include <Library/BoardInitLib.h>-#include
> <Library/PeiServicesTablePointerLib.h>--/**-This interface disables temporary
> memory in SEC
> Phase.-**/-VOID-EFIAPI-SecPlatformDisableTemporaryMemory (-
> VOID- )-{- EFI_STATUS Status;- VOID
> *TempRamExitParam;- CONST EFI_PEI_SERVICES **PeiServices;-
> FSP_TEMP_RAM_EXIT_PPI *TempRamExitPpi;-- DEBUG ((DEBUG_INFO,
> "SecPlatformDisableTemporaryMemory enter\n"));-- Status =
> BoardInitBeforeTempRamExit ();- ASSERT_EFI_ERROR (Status);-- if
> (PcdGet8 (PcdFspModeSelection) == 1) {- //- // FSP API mode- //-
> TempRamExitParam = UpdateTempRamExitParam ();- Status =
> CallTempRamExit (TempRamExitParam);- DEBUG ((DEBUG_INFO,
> "TempRamExit status: 0x%x\n", Status));- ASSERT_EFI_ERROR (Status);- }
> else {- //- // FSP Dispatch mode- //- PeiServices =
> GetPeiServicesTablePointer ();- Status = (*PeiServices)->LocatePpi (-
> PeiServices,- &gFspTempRamExitPpiGuid,-
> 0,- NULL,-
> (VOID **) &TempRamExitPpi- );-
> ASSERT_EFI_ERROR (Status);- if (EFI_ERROR (Status)) {-
> return;- }- TempRamExitPpi->TempRamExit (NULL);- }-- Status =
> BoardInitAfterTempRamExit ();- ASSERT_EFI_ERROR (Status);--
> return ;-}diff --git
> a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.dsc
> b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.dsc
> index 2bc2b4126b..acdc31e708 100644
> --- a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.dsc
> +++ b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.dsc
> @@ -126,7 +126,7 @@
> #######################################
> GpioExpanderLib|$(PLATFORM_BOARD_PACKAGE)/Library/BaseGpioExpande
> rLib/BaseGpioExpanderLib.inf
> I2cAccessLib|$(PLATFORM_BOARD_PACKAGE)/Library/PeiI2cAccessLib/PeiI2cA
> ccessLib.inf-
> PlatformSecLib|$(PLATFORM_BOARD_PACKAGE)/FspWrapper/Library/SecFsp
> WrapperPlatformSecLib/SecFspWrapperPlatformSecLib.inf+
> PlatformSecLib|$(PLATFORM_PACKAGE)/FspWrapper/Library/SecFspWrapper
> PlatformSecLib/SecFspWrapperPlatformSecLib.inf # Thunderbolt !if
> gKabylakeOpenBoardPkgTokenSpaceGuid.PcdTbtEnable == TRUEdiff --git
> a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc
> b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc
> index 77e4a6a610..4b07c0a684 100644
> ---
> a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc
> +++
> b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc
> @@ -166,7 +166,7 @@
> EcLib|$(PLATFORM_BOARD_PACKAGE)/Library/BaseEcLib/BaseEcLib.inf
> GpioExpanderLib|$(PLATFORM_BOARD_PACKAGE)/Library/BaseGpioExpande
> rLib/BaseGpioExpanderLib.inf
> I2cAccessLib|$(PLATFORM_BOARD_PACKAGE)/Library/PeiI2cAccessLib/PeiI2cA
> ccessLib.inf-
> PlatformSecLib|$(PLATFORM_BOARD_PACKAGE)/FspWrapper/Library/SecFsp
> WrapperPlatformSecLib/SecFspWrapperPlatformSecLib.inf+
> PlatformSecLib|$(PLATFORM_PACKAGE)/FspWrapper/Library/SecFspWrapper
> PlatformSecLib/SecFspWrapperPlatformSecLib.inf # Thunderbolt !if
> gKabylakeOpenBoardPkgTokenSpaceGuid.PcdTbtEnable == TRUE--
> 2.24.0.windows.2
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-=-=-=-=-=-=-=-=-=-=-=-
Reviewed-by: Michael Kubacki <michael.a.kubacki@intel.com>
> -----Original Message-----
> From: Desimone, Nathaniel L <nathaniel.l.desimone@intel.com>
> Sent: Thursday, November 21, 2019 12:59 AM
> To: devel@edk2.groups.io
> Cc: Chiu, Chasel <chasel.chiu@intel.com>; Kubacki, Michael A
> <michael.a.kubacki@intel.com>; Jeremy Soller <jeremy@system76.com>
> Subject: [edk2-platforms] [PATCH V2 13/14] KabylakeOpenBoardPkg:
> Remove SecFspWrapperPlatformSecLib override
>
> Cc: Chasel Chiu <chasel.chiu@intel.com>
> Cc: Michael Kubacki <michael.a.kubacki@intel.com>
> Cc: Jeremy Soller <jeremy@system76.com>
> Signed-off-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
> ---
> .../FspWrapperPlatformSecLib.c | 186 ---------
> .../SecFspWrapperPlatformSecLib/FsptCoreUpd.h | 40 --
> .../SecFspWrapperPlatformSecLib/Ia32/Fsp.h | 42 --
> .../Ia32/PeiCoreEntry.nasm | 130 -------
> .../Ia32/SecEntry.nasm | 361 ------------------
> .../Ia32/Stack.nasm | 72 ----
> .../PlatformInit.c | 47 ---
> .../SecFspWrapperPlatformSecLib.inf | 97 -----
> .../SecGetPerformance.c | 89 -----
> .../SecPlatformInformation.c | 78 ----
> .../SecRamInitData.c | 36 --
> .../SecTempRamDone.c | 73 ----
> .../GalagoPro3/OpenBoardPkg.dsc | 2 +-
> .../KabylakeRvp3/OpenBoardPkg.dsc | 2 +-
> 14 files changed, 2 insertions(+), 1253 deletions(-) delete mode 100644
> Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapper
> PlatformSecLib/FspWrapperPlatformSecLib.c
> delete mode 100644
> Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapper
> PlatformSecLib/FsptCoreUpd.h
> delete mode 100644
> Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapper
> PlatformSecLib/Ia32/Fsp.h
> delete mode 100644
> Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapper
> PlatformSecLib/Ia32/PeiCoreEntry.nasm
> delete mode 100644
> Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapper
> PlatformSecLib/Ia32/SecEntry.nasm
> delete mode 100644
> Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapper
> PlatformSecLib/Ia32/Stack.nasm
> delete mode 100644
> Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapper
> PlatformSecLib/PlatformInit.c
> delete mode 100644
> Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapper
> PlatformSecLib/SecFspWrapperPlatformSecLib.inf
> delete mode 100644
> Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapper
> PlatformSecLib/SecGetPerformance.c
> delete mode 100644
> Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapper
> PlatformSecLib/SecPlatformInformation.c
> delete mode 100644
> Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapper
> PlatformSecLib/SecRamInitData.c
> delete mode 100644
> Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapper
> PlatformSecLib/SecTempRamDone.c
>
> diff --git
> a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapp
> erPlatformSecLib/FspWrapperPlatformSecLib.c
> b/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrap
> perPlatformSecLib/FspWrapperPlatformSecLib.c
> deleted file mode 100644
> index d40eecae95..0000000000
> ---
> a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapp
> erPlatformSecLib/FspWrapperPlatformSecLib.c
> +++ /dev/null
> @@ -1,186 +0,0 @@
> -/** @file- Provide FSP wrapper platform sec related function.--Copyright
> (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR>-SPDX-License-
> Identifier: BSD-2-Clause-Patent--**/--#include <PiPei.h>--#include
> <Ppi/SecPlatformInformation.h>-#include <Ppi/SecPerformance.h>-
> #include <Ppi/FirmwareVolumeInfo.h>-#include
> <Ppi/TopOfTemporaryRam.h>-#include <Ppi/PeiCoreFvLocation.h>-#include
> <Guid/FirmwareFileSystem2.h>--#include <Library/LocalApicLib.h>-#include
> <Library/BaseMemoryLib.h>-#include <Library/DebugLib.h>-#include
> <Library/IoLib.h>--/**- This interface conveys state information out of the
> Security (SEC) phase into PEI.-- @param[in] PeiServices Pointer to
> the PEI Services Table.- @param[in,out] StructureSize Pointer to the
> variable describing size of the input buffer.- @param[out]
> PlatformInformationRecord Pointer to the
> EFI_SEC_PLATFORM_INFORMATION_RECORD.-- @retval EFI_SUCCESS
> The data was successfully returned.- @retval EFI_BUFFER_TOO_SMALL The
> buffer was too small.--**/-EFI_STATUS-EFIAPI-SecPlatformInformation (- IN
> CONST EFI_PEI_SERVICES **PeiServices,- IN OUT UINT64
> *StructureSize,- OUT EFI_SEC_PLATFORM_INFORMATION_RECORD
> *PlatformInformationRecord- );--/**- This interface conveys performance
> information out of the Security (SEC) phase into PEI.-- This service is
> published by the SEC phase. The SEC phase handoff has an optional-
> EFI_PEI_PPI_DESCRIPTOR list as its final argument when control is passed
> from SEC into the- PEI Foundation. As such, if the platform supports
> collecting performance data in SEC,- this information is encapsulated into the
> data structure abstracted by this service.- This information is collected for
> the boot-strap processor (BSP) on IA-32.-- @param[in] PeiServices The
> pointer to the PEI Services Table.- @param[in] This The pointer to this
> instance of the PEI_SEC_PERFORMANCE_PPI.- @param[out] Performance
> The pointer to performance data collected in SEC phase.-- @retval
> EFI_SUCCESS The data was successfully returned.--**/-EFI_STATUS-EFIAPI-
> SecGetPerformance (- IN CONST EFI_PEI_SERVICES **PeiServices,- IN
> PEI_SEC_PERFORMANCE_PPI *This,- OUT
> FIRMWARE_SEC_PERFORMANCE *Performance- );--
> PEI_SEC_PERFORMANCE_PPI mSecPerformancePpi = {-
> SecGetPerformance-};--EFI_PEI_CORE_FV_LOCATION_PPI
> mPeiCoreFvLocationPpi = {- (VOID *) (UINTN) FixedPcdGet32
> (PcdFspmBaseAddress)-};--EFI_PEI_PPI_DESCRIPTOR
> mPeiCoreFvLocationPpiList[] = {- {- EFI_PEI_PPI_DESCRIPTOR_PPI,-
> &gEfiPeiCoreFvLocationPpiGuid,- &mPeiCoreFvLocationPpi- }-};--
> EFI_PEI_PPI_DESCRIPTOR mPeiSecPlatformPpi[] = {- {-
> EFI_PEI_PPI_DESCRIPTOR_PPI,- &gTopOfTemporaryRamPpiGuid,- NULL
> // To be patched later.- },- {- EFI_PEI_PPI_DESCRIPTOR_PPI |
> EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,-
> &gPeiSecPerformancePpiGuid,- &mSecPerformancePpi- },-};--#define
> LEGACY_8259_MASK_REGISTER_MASTER 0x21-#define
> LEGACY_8259_MASK_REGISTER_SLAVE 0xA1-#define
> LEGACY_8259_EDGE_LEVEL_TRIGGERED_REGISTER_MASTER 0x4D0-#define
> LEGACY_8259_EDGE_LEVEL_TRIGGERED_REGISTER_SLAVE 0x4D1--/**-
> Write to mask and edge/level triggered registers of master and slave 8259
> PICs.-- @param[in] Mask low byte for master PIC mask register,-
> high byte for slave PIC mask register.- @param[in] EdgeLevel low byte for
> master PIC edge/level triggered register,- high byte for slave PIC
> edge/level triggered register.--**/-VOID-Interrupt8259WriteMask (- IN
> UINT16 Mask,- IN UINT16 EdgeLevel- )-{- IoWrite8
> (LEGACY_8259_MASK_REGISTER_MASTER, (UINT8) Mask);- IoWrite8
> (LEGACY_8259_MASK_REGISTER_SLAVE, (UINT8) (Mask >> 8));- IoWrite8
> (LEGACY_8259_EDGE_LEVEL_TRIGGERED_REGISTER_MASTER, (UINT8)
> EdgeLevel);- IoWrite8
> (LEGACY_8259_EDGE_LEVEL_TRIGGERED_REGISTER_SLAVE, (UINT8)
> (EdgeLevel >> 8));-}--/**- A developer supplied function to perform
> platform specific operations.-- It's a developer supplied function to perform
> any operations appropriate to a- given platform. It's invoked just before
> passing control to PEI core by SEC- core. Platform developer may modify the
> SecCoreData passed to PEI Core.- It returns a platform specific PPI list that
> platform wishes to pass to PEI core.- The Generic SEC core module will
> merge this list to join the final list passed to- PEI core.-- @param[in,out]
> SecCoreData The same parameter as passing to PEI core. It-
> could be overridden by this function.-- @return The platform specific PPI list
> to be passed to PEI core or- NULL if there is no need of such platform
> specific PPI list.--**/-EFI_PEI_PPI_DESCRIPTOR *-EFIAPI-SecPlatformMain (-
> IN OUT EFI_SEC_PEI_HAND_OFF *SecCoreData- )-{-
> EFI_PEI_PPI_DESCRIPTOR *PpiList;- UINT8
> TopOfTemporaryRamPpiIndex;- UINT8
> *CopyDestinationPointer;-- DEBUG ((DEBUG_INFO, "FSP Wrapper
> BootFirmwareVolumeBase - 0x%x\n", SecCoreData-
> >BootFirmwareVolumeBase));- DEBUG ((DEBUG_INFO, "FSP Wrapper
> BootFirmwareVolumeSize - 0x%x\n", SecCoreData-
> >BootFirmwareVolumeSize));- DEBUG ((DEBUG_INFO, "FSP Wrapper
> TemporaryRamBase - 0x%x\n", SecCoreData->TemporaryRamBase));-
> DEBUG ((DEBUG_INFO, "FSP Wrapper TemporaryRamSize - 0x%x\n",
> SecCoreData->TemporaryRamSize));- DEBUG ((DEBUG_INFO, "FSP Wrapper
> PeiTemporaryRamBase - 0x%x\n", SecCoreData-
> >PeiTemporaryRamBase));- DEBUG ((DEBUG_INFO, "FSP Wrapper
> PeiTemporaryRamSize - 0x%x\n", SecCoreData->PeiTemporaryRamSize));-
> DEBUG ((DEBUG_INFO, "FSP Wrapper StackBase - 0x%x\n",
> SecCoreData->StackBase));- DEBUG ((DEBUG_INFO, "FSP Wrapper StackSize
> - 0x%x\n", SecCoreData->StackSize));-- InitializeApicTimer (0, (UINT32) -1,
> TRUE, 5);-- //- // Set all 8259 interrupts to edge triggered and disabled- //-
> Interrupt8259WriteMask (0xFFFF, 0x0000);-- //- // Use middle of Heap as
> temp buffer, it will be copied by caller.- // Do not use Stack, because it will
> cause wrong calculation on stack by PeiCore- //- PpiList = (VOID *)((UINTN)
> SecCoreData->PeiTemporaryRamBase + (UINTN) SecCoreData-
> >PeiTemporaryRamSize/2);- CopyDestinationPointer = (UINT8 *) PpiList;-
> TopOfTemporaryRamPpiIndex = 0;- if (PcdGet8 (PcdFspModeSelection) ==
> 0) {- //- // In Dispatch mode, wrapper should provide
> PeiCoreFvLocationPpi.- //- CopyMem (CopyDestinationPointer,
> mPeiCoreFvLocationPpiList, sizeof (mPeiCoreFvLocationPpiList));-
> TopOfTemporaryRamPpiIndex = 1;- CopyDestinationPointer += sizeof
> (mPeiCoreFvLocationPpiList);- }- CopyMem (CopyDestinationPointer,
> mPeiSecPlatformPpi, sizeof(mPeiSecPlatformPpi));- //- // Patch
> TopOfTemporaryRamPpi- //- PpiList[TopOfTemporaryRamPpiIndex].Ppi =
> (VOID *)((UINTN) SecCoreData->TemporaryRamBase + SecCoreData-
> >TemporaryRamSize);-- return PpiList;-}diff --git
> a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapp
> erPlatformSecLib/FsptCoreUpd.h
> b/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrap
> perPlatformSecLib/FsptCoreUpd.h
> deleted file mode 100644
> index 7c0f605b92..0000000000
> ---
> a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapp
> erPlatformSecLib/FsptCoreUpd.h
> +++ /dev/null
> @@ -1,40 +0,0 @@
> -/** @file--Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>-
> SPDX-License-Identifier: BSD-2-Clause-Patent--**/--#ifndef
> __FSPT_CORE_UPD_H__-#define __FSPT_CORE_UPD_H__--#pragma
> pack(1)--/** Fsp T Core UPD-**/-typedef struct {--/** Offset 0x0020-**/-
> UINT32 MicrocodeRegionBase;--/** Offset 0x0024-**/- UINT32
> MicrocodeRegionSize;--/** Offset 0x0028-**/- UINT32
> CodeRegionBase;--/** Offset 0x002C-**/- UINT32
> CodeRegionSize;--/** Offset 0x0030-**/- UINT8 Reserved[16];-}
> FSPT_CORE_UPD;--#pragma pack()--#endifdiff --git
> a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapp
> erPlatformSecLib/Ia32/Fsp.h
> b/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrap
> perPlatformSecLib/Ia32/Fsp.h
> deleted file mode 100644
> index 9f6cdcf476..0000000000
> ---
> a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapp
> erPlatformSecLib/Ia32/Fsp.h
> +++ /dev/null
> @@ -1,42 +0,0 @@
> -/** @file- Fsp related definitions--Copyright (c) 2017, Intel Corporation. All
> rights reserved.<BR>-SPDX-License-Identifier: BSD-2-Clause-Patent--**/--
> #ifndef __FSP_H__-#define __FSP_H__--//-// Fv Header-//-#define
> FVH_SIGINATURE_OFFSET 0x28-#define
> FVH_SIGINATURE_VALID_VALUE 0x4856465F // valid signature:_FVH-
> #define FVH_HEADER_LENGTH_OFFSET 0x30-#define
> FVH_EXTHEADER_OFFSET_OFFSET 0x34-#define
> FVH_EXTHEADER_SIZE_OFFSET 0x10--//-// Ffs Header-//-#define
> FSP_HEADER_GUID_DWORD1 0x912740BE-#define
> FSP_HEADER_GUID_DWORD2 0x47342284-#define
> FSP_HEADER_GUID_DWORD3 0xB08471B9-#define
> FSP_HEADER_GUID_DWORD4 0x0C3F3527-#define
> FFS_HEADER_SIZE_VALUE 0x18--//-// Section Header-//-#define
> SECTION_HEADER_TYPE_OFFSET 0x03-#define
> RAW_SECTION_HEADER_SIZE_VALUE 0x04--//-// Fsp Header-//-#define
> FSP_HEADER_IMAGEBASE_OFFSET 0x1C-#define
> FSP_HEADER_TEMPRAMINIT_OFFSET 0x30--#endifdiff --git
> a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapp
> erPlatformSecLib/Ia32/PeiCoreEntry.nasm
> b/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrap
> perPlatformSecLib/Ia32/PeiCoreEntry.nasm
> deleted file mode 100644
> index 5c5b788085..0000000000
> ---
> a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapp
> erPlatformSecLib/Ia32/PeiCoreEntry.nasm
> +++ /dev/null
> @@ -1,130 +0,0 @@
> -;-------------------------------------------------------------------------------;-;
> Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>-; SPDX-
> License-Identifier: BSD-2-Clause-Patent-;-; Module Name:-;-;
> PeiCoreEntry.nasm-;-; Abstract:-;-; Find and call SecStartup-;-;-----------------
> ---------------------------------------------------------------SECTION .text--extern
> ASM_PFX(SecStartup)-extern ASM_PFX(PlatformInit)--global
> ASM_PFX(CallPeiCoreEntryPoint)-ASM_PFX(CallPeiCoreEntryPoint):- ;- ;
> Obtain the hob list pointer- ;- mov eax, [esp+4]- ;- ; Obtain the stack
> information- ; ECX: start of range- ; EDX: end of range- ;- mov ecx,
> [esp+8]- mov edx, [esp+0xC]-- ;- ; Platform init- ;- pushad- push edx-
> push ecx- push eax- call ASM_PFX(PlatformInit)- pop eax- pop eax- pop
> eax- popad-- ;- ; Set stack top pointer- ;- mov esp, edx-- ;- ; Push the
> hob list pointer- ;- push eax-- ;- ; Save the value- ; ECX: start of range- ;
> EDX: end of range- ;- mov ebp, esp- push ecx- push edx-- ;- ; Push
> processor count to stack first, then BIST status (AP then BSP)- ;- mov eax,
> 1- cpuid- shr ebx, 16- and ebx, 0xFF- cmp bl, 1- jae
> PushProcessorCount-- ;- ; Some processors report 0 logical processors.
> Effectively 0 = 1.- ; So we fix up the processor count- ;- inc ebx--
> PushProcessorCount:- push ebx-- ;- ; We need to implement a long-term
> solution for BIST capture. For now, we just copy BSP BIST- ; for all processor
> threads- ;- xor ecx, ecx- mov cl, bl-PushBist:- movd eax, mm0- push
> eax- loop PushBist-- ; Save Time-Stamp Counter- movd eax, mm5- push
> eax-- movd eax, mm6- push eax-- ;- ; Pass entry point of the PEI core- ;-
> mov edi, 0xFFFFFFE0- push DWORD [edi]-- ;- ; Pass BFV into the PEI
> Core- ;- mov edi, 0xFFFFFFFC- push DWORD [edi]-- ;- ; Pass stack size
> into the PEI Core- ;- mov ecx, [ebp - 4]- mov edx, [ebp - 8]- push ecx
> ; RamBase-- sub edx, ecx- push edx ; RamSize-- ;- ; Pass Control into
> the PEI Core- ;- call ASM_PFX(SecStartup)-diff --git
> a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapp
> erPlatformSecLib/Ia32/SecEntry.nasm
> b/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrap
> perPlatformSecLib/Ia32/SecEntry.nasm
> deleted file mode 100644
> index 7f6d771e41..0000000000
> ---
> a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapp
> erPlatformSecLib/Ia32/SecEntry.nasm
> +++ /dev/null
> @@ -1,361 +0,0 @@
> -;-------------------------------------------------------------------------------;-;
> Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>-; SPDX-
> License-Identifier: BSD-2-Clause-Patent-; Module Name:-;-; SecEntry.nasm-
> ;-; Abstract:-;-; This is the code that goes from real-mode to protected
> mode.-; It consumes the reset vector, calls TempRamInit API from FSP
> binary.-;-;--------------------------------------------------------------------------------
> #include "Fsp.h"--SECTION .text--extern ASM_PFX(CallPeiCoreEntryPoint)-
> extern ASM_PFX(FsptUpdDataPtr)-extern
> ASM_PFX(BoardBeforeTempRamInit)-; Pcds-extern ASM_PFX(PcdGet32
> (PcdFspTemporaryRamSize))-extern ASM_PFX(PcdGet32
> (PcdFsptBaseAddress))--;--------------------------------------------------------------
> ---------------;-; Procedure: _ModuleEntryPoint-;-; Input: None-;-;
> Output: None-;-; Destroys: Assume all registers-;-; Description:-;-;
> Transition to non-paged flat-model protected mode from a-; hard-coded
> GDT that provides exactly two descriptors.-; This is a bare bones transition
> to protected mode only-; used for a while in PEI and possibly DXE.-;-; After
> enabling protected mode, a far jump is executed to-; transfer to PEI using
> the newly loaded GDT.-;-; Return: None-;-; MMX Usage:-; MM0 =
> BIST State-; MM5 = Save time-stamp counter value high32bit-;
> MM6 = Save time-stamp counter value low32bit.-;-;-------------------------------
> -----------------------------------------------BITS 16-align 4-global
> ASM_PFX(_ModuleEntryPoint)-ASM_PFX(_ModuleEntryPoint):- fninit
> ; clear any pending Floating point exceptions- ;- ; Store the BIST value in
> mm0- ;- movd mm0, eax- cli-- ;- ; Check INIT# is asserted by port 0xCF9-
> ;- mov dx, 0CF9h- in al, dx- cmp al, 04h- jnz NotWarmStart--- ;- ; @note
> Issue warm reset, since if CPU only reset is issued not all MSRs are restored
> to their defaults- ;- mov dx, 0CF9h- mov al, 06h- out dx, al--NotWarmStart:-
> ;- ; Save time-stamp counter value- ; rdtsc load 64bit time-stamp counter to
> EDX:EAX- ;- rdtsc- movd mm5, edx- movd mm6, eax-- ;- ; Load the GDT
> table in GdtDesc- ;- mov esi, GdtDesc- DB 66h- lgdt [cs:si]-- ;- ;
> Transition to 16 bit protected mode- ;- mov eax, cr0 ; Get control
> register 0- or eax, 00000003h ; Set PE bit (bit #0) & MP bit (bit #1)-
> mov cr0, eax ; Activate protected mode-- mov eax, cr4
> ; Get control register 4- or eax, 00000600h ; Set OSFXSR bit (bit #9) &
> OSXMMEXCPT bit (bit #10)- mov cr4, eax-- ;- ; Now we're in 16 bit
> protected mode- ; Set up the selectors for 32 bit protected mode entry- ;-
> mov ax, SYS_DATA_SEL- mov ds, ax- mov es, ax- mov fs, ax- mov
> gs, ax- mov ss, ax-- ;- ; Transition to Flat 32 bit protected mode- ; The
> jump to a far pointer causes the transition to 32 bit mode- ;- mov esi,
> ProtectedModeEntryLinearAddress- jmp dword far [cs:si]--;------------------
> -----------------------------------------------------------;-; Procedure:
> ProtectedModeEntryPoint-;-; Input: None-;-; Output: None-;-;
> Destroys: Assume all registers-;-; Description:-;-; This function handles:-;
> Call two basic APIs from FSP binary-; Initializes stack with some early data
> (BIST, PEI entry, etc)-;-; Return: None-;-;-----------------------------------------
> -------------------------------------BITS 32-align 4-ProtectedModeEntryPoint:- ;-
> ; Early board hooks- ;- mov esp, BoardBeforeTempRamInitRet- jmp
> ASM_PFX(BoardBeforeTempRamInit)--BoardBeforeTempRamInitRet:-- ;
> Find the fsp info header- mov edi, [ASM_PFX(PcdGet32
> (PcdFsptBaseAddress))]-- mov eax, dword [edi +
> FVH_SIGINATURE_OFFSET]- cmp eax, FVH_SIGINATURE_VALID_VALUE-
> jnz FspHeaderNotFound-- xor eax, eax- mov ax, word [edi +
> FVH_EXTHEADER_OFFSET_OFFSET]- cmp ax, 0- jnz FspFvExtHeaderExist--
> xor eax, eax- mov ax, word [edi + FVH_HEADER_LENGTH_OFFSET] ; Bypass
> Fv Header- add edi, eax- jmp FspCheckFfsHeader--FspFvExtHeaderExist:-
> add edi, eax- mov eax, dword [edi + FVH_EXTHEADER_SIZE_OFFSET] ;
> Bypass Ext Fv Header- add edi, eax-- ; Round up to 8 byte alignment- mov
> eax, edi- and al, 07h- jz FspCheckFfsHeader-- and edi, 0FFFFFFF8h- add
> edi, 08h--FspCheckFfsHeader:- ; Check the ffs guid- mov eax, dword [edi]-
> cmp eax, FSP_HEADER_GUID_DWORD1- jnz FspHeaderNotFound-- mov
> eax, dword [edi + 4]- cmp eax, FSP_HEADER_GUID_DWORD2- jnz
> FspHeaderNotFound-- mov eax, dword [edi + 8]- cmp eax,
> FSP_HEADER_GUID_DWORD3- jnz FspHeaderNotFound-- mov eax, dword
> [edi + 0Ch]- cmp eax, FSP_HEADER_GUID_DWORD4- jnz
> FspHeaderNotFound-- add edi, FFS_HEADER_SIZE_VALUE ; Bypass the
> ffs header-- ; Check the section type as raw section- mov al, byte [edi +
> SECTION_HEADER_TYPE_OFFSET]- cmp al, 019h- jnz FspHeaderNotFound--
> add edi, RAW_SECTION_HEADER_SIZE_VALUE ; Bypass the section header-
> jmp FspHeaderFound--FspHeaderNotFound:- jmp $--FspHeaderFound:- ;
> Get the fsp TempRamInit Api address- mov eax, dword [edi +
> FSP_HEADER_IMAGEBASE_OFFSET]- add eax, dword [edi +
> FSP_HEADER_TEMPRAMINIT_OFFSET]-- ; Setup the hardcode stack- mov
> esp, TempRamInitStack-- ; Call the fsp TempRamInit Api- jmp eax--
> TempRamInitDone:- cmp eax, 8000000Eh ;Check if EFI_NOT_FOUND
> returned. Error code for Microcode Update not found.- je CallSecFspInit
> ;If microcode not found, don't hang, but continue.-- cmp eax, 0 ;Check
> if EFI_SUCCESS retuned.- jnz FspApiFailed-- ; ECX: start of range- ; EDX:
> end of range-CallSecFspInit:- sub edx, [ASM_PFX(PcdGet32
> (PcdFspTemporaryRamSize))] ; TemporaryRam for FSP- xor eax, eax- mov
> esp, edx-- ; Align the stack at DWORD- add esp, 3- and esp, 0FFFFFFFCh--
> push edx- push ecx- push eax ; zero - no hob list yet- call
> ASM_PFX(CallPeiCoreEntryPoint)--FspApiFailed:- jmp $--align 10h-
> TempRamInitStack:- DD TempRamInitDone- DD
> ASM_PFX(FsptUpdDataPtr); TempRamInitParams--;-; ROM-based Global-
> Descriptor Table for the Tiano PEI Phase-;-align 16-global
> ASM_PFX(BootGdtTable)--;-; GDT[0]: 0x00: Null entry, never used.-;-
> NULL_SEL EQU $ - GDT_BASE ; Selector [0]-GDT_BASE:-
> ASM_PFX(BootGdtTable):- DD 0- DD 0-;-; Linear data
> segment descriptor-;-LINEAR_SEL EQU $ - GDT_BASE ; Selector [0x8]-
> DW 0FFFFh ; limit 0xFFFFF- DW 0 ; base 0- DB
> 0- DB 092h ; present, ring 0, data, expand-up, writable- DB
> 0CFh ; page-granular, 32-bit- DB 0-;-; Linear code segment
> descriptor-;-LINEAR_CODE_SEL EQU $ - GDT_BASE ; Selector [0x10]- DW
> 0FFFFh ; limit 0xFFFFF- DW 0 ; base 0- DB 0-
> DB 09Bh ; present, ring 0, data, expand-up, not-writable- DB
> 0CFh ; page-granular, 32-bit- DB 0-;-; System data segment
> descriptor-;-SYS_DATA_SEL EQU $ - GDT_BASE ; Selector [0x18]- DW
> 0FFFFh ; limit 0xFFFFF- DW 0 ; base 0- DB 0-
> DB 093h ; present, ring 0, data, expand-up, not-writable- DB
> 0CFh ; page-granular, 32-bit- DB 0--;-; System code segment
> descriptor-;-SYS_CODE_SEL EQU $ - GDT_BASE ; Selector [0x20]- DW
> 0FFFFh ; limit 0xFFFFF- DW 0 ; base 0- DB 0-
> DB 09Ah ; present, ring 0, data, expand-up, writable- DB 0CFh
> ; page-granular, 32-bit- DB 0-;-; Spare segment descriptor-;-
> SYS16_CODE_SEL EQU $ - GDT_BASE ; Selector [0x28]- DW 0FFFFh
> ; limit 0xFFFFF- DW 0 ; base 0- DB 0Eh ;
> Changed from F000 to E000.- DB 09Bh ; present, ring 0, code,
> expand-up, writable- DB 00h ; byte-granular, 16-bit- DB 0-;-;
> Spare segment descriptor-;-SYS16_DATA_SEL EQU $ - GDT_BASE ;
> Selector [0x30]- DW 0FFFFh ; limit 0xFFFF- DW 0
> ; base 0- DB 0- DB 093h ; present, ring 0, data, expand-up,
> not-writable- DB 00h ; byte-granular, 16-bit- DB 0--;-; Spare
> segment descriptor-;-SPARE5_SEL EQU $ - GDT_BASE ; Selector [0x38]-
> DW 0 ; limit 0- DW 0 ; base 0- DB 0- DB 0
> ; present, ring 0, data, expand-up, writable- DB 0 ; page-
> granular, 32-bit- DB 0-GDT_SIZE EQU $ - GDT_BASE ; Size, in bytes--;-
> ; GDT Descriptor-;-GdtDesc: ; GDT descriptor- DW GDT_SIZE
> - 1 ; GDT limit- DD GDT_BASE ; GDT base address---
> ProtectedModeEntryLinearAddress:-ProtectedModeEntryLinear:- DD
> ProtectedModeEntryPoint ; Offset of our 32 bit code- DW
> LINEAR_CODE_SELdiff --git
> a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapp
> erPlatformSecLib/Ia32/Stack.nasm
> b/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrap
> perPlatformSecLib/Ia32/Stack.nasm
> deleted file mode 100644
> index 47db32d64c..0000000000
> ---
> a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapp
> erPlatformSecLib/Ia32/Stack.nasm
> +++ /dev/null
> @@ -1,72 +0,0 @@
> -;-------------------------------------------------------------------------------;-;
> Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>-; SPDX-
> License-Identifier: BSD-2-Clause-Patent-; Abstract:-;-; Switch the stack from
> temporary memory to permanent memory.-;-;-------------------------------------
> ------------------------------------------- SECTION .text--;----------------------------
> ---------------------------------------------------; VOID-; EFIAPI-; SecSwitchStack (-;
> UINT32 TemporaryMemoryBase,-; UINT32 PermanentMemoryBase-; );-
> ;-------------------------------------------------------------------------------global
> ASM_PFX(SecSwitchStack)-ASM_PFX(SecSwitchStack):- ;- ; Save three
> register: eax, ebx, ecx- ;- push eax- push ebx- push ecx- push edx--
> ;- ; !!CAUTION!! this function address's is pushed into stack after- ;
> migration of whole temporary memory, so need save it to permanent- ;
> memory at first!- ;-- mov ebx, [esp + 20] ; Save the first parameter-
> mov ecx, [esp + 24] ; Save the second parameter-- ;- ; Save this
> function's return address into permanent memory at first.- ; Then, Fixup
> the esp point to permanent memory- ;- mov eax, esp- sub eax, ebx-
> add eax, ecx- mov edx, dword [esp] ; copy pushed register's value to
> permanent memory- mov dword [eax], edx- mov edx, dword [esp + 4]-
> mov dword [eax + 4], edx- mov edx, dword [esp + 8]- mov dword [eax
> + 8], edx- mov edx, dword [esp + 12]- mov dword [eax + 12], edx- mov
> edx, dword [esp + 16] ; Update this function's return address into
> permanent memory- mov dword [eax + 16], edx- mov esp, eax
> ; From now, esp is pointed to permanent memory-- ;- ; Fixup the ebp
> point to permanent memory- ;- mov eax, ebp- sub eax, ebx- add
> eax, ecx- mov ebp, eax ; From now, ebp is pointed to permanent
> memory-- pop edx- pop ecx- pop ebx- pop eax- ret-diff --git
> a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapp
> erPlatformSecLib/PlatformInit.c
> b/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrap
> perPlatformSecLib/PlatformInit.c
> deleted file mode 100644
> index ef89e3f310..0000000000
> ---
> a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapp
> erPlatformSecLib/PlatformInit.c
> +++ /dev/null
> @@ -1,47 +0,0 @@
> -/** @file- Provide platform init function.--Copyright (c) 2017, Intel
> Corporation. All rights reserved.<BR>-SPDX-License-Identifier: BSD-2-Clause-
> Patent--**/---#include <PiPei.h>-#include <Library/DebugLib.h>-#include
> <Library/SerialPortLib.h>-#include <Library/SecBoardInitLib.h>-#include
> <Library/TestPointCheckLib.h>--/**- Platform initialization.-- @param[in]
> FspHobList HobList produced by FSP.- @param[in] StartOfRange Start of
> temporary RAM.- @param[in] EndOfRange End of temporary RAM.-**/-
> VOID-EFIAPI-PlatformInit (- IN VOID *FspHobList,- IN VOID
> *StartOfRange,- IN VOID *EndOfRange- )-{- //- // Platform
> initialization- // Enable Serial port here- //- if
> (PcdGetBool(PcdSecSerialPortDebugEnable)) {- SerialPortInitialize ();- }--
> DEBUG ((DEBUG_INFO, "PrintPeiCoreEntryPointParam in PlatformInit\n"));-
> DEBUG ((DEBUG_INFO, "FspHobList - 0x%x\n", FspHobList));- DEBUG
> ((DEBUG_INFO, "StartOfRange - 0x%x\n", StartOfRange));- DEBUG
> ((DEBUG_INFO, "EndOfRange - 0x%x\n", EndOfRange));--
> BoardAfterTempRamInit ();-- TestPointTempMemoryFunction
> (StartOfRange, EndOfRange);-}diff --git
> a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapp
> erPlatformSecLib/SecFspWrapperPlatformSecLib.inf
> b/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrap
> perPlatformSecLib/SecFspWrapperPlatformSecLib.inf
> deleted file mode 100644
> index c99dd5ecdd..0000000000
> ---
> a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapp
> erPlatformSecLib/SecFspWrapperPlatformSecLib.inf
> +++ /dev/null
> @@ -1,97 +0,0 @@
> -## @file-# Provide FSP wrapper platform sec related function.-#-#
> Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR>-#-#
> SPDX-License-Identifier: BSD-2-Clause-Patent-#-#-##--
> ##########################################################
> ######################-#-# Defines Section - statements that will be
> processed to create a Makefile.-#-
> ##########################################################
> ######################-[Defines]- INF_VERSION =
> 0x00010005- BASE_NAME = SecFspWrapperPlatformSecLib-
> FILE_GUID = 4E1C4F95-90EA-47de-9ACC-B8920189A1F5-
> MODULE_TYPE = SEC- VERSION_STRING = 1.0-
> LIBRARY_CLASS = PlatformSecLib---#-# The following information is
> for reference only and not required by the build tools.-#-#
> VALID_ARCHITECTURES = IA32 X64-#--
> ##########################################################
> ######################-#-# Sources Section - list of files that are
> required for the build to succeed.-#-
> ##########################################################
> ######################--[Sources]- FspWrapperPlatformSecLib.c-
> SecRamInitData.c- SecPlatformInformation.c- SecGetPerformance.c-
> SecTempRamDone.c- PlatformInit.c--[Sources.IA32]- Ia32/SecEntry.nasm-
> Ia32/PeiCoreEntry.nasm- Ia32/Stack.nasm- Ia32/Fsp.h--
> ##########################################################
> ######################-#-# Package Dependency Section - list of
> Package files that are required for-# this module.-#-
> ##########################################################
> ######################--[Packages]- MdePkg/MdePkg.dec-
> MdeModulePkg/MdeModulePkg.dec- UefiCpuPkg/UefiCpuPkg.dec-
> IntelFsp2Pkg/IntelFsp2Pkg.dec-
> IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec-
> MinPlatformPkg/MinPlatformPkg.dec- KabylakeSiliconPkg/SiPkg.dec--
> [LibraryClasses]- LocalApicLib- SerialPortLib- FspWrapperPlatformLib-
> FspWrapperApiLib- BoardInitLib- SecBoardInitLib- TestPointCheckLib-
> PeiServicesTablePointerLib--[Ppis]- gEfiSecPlatformInformationPpiGuid
> ## CONSUMES- gPeiSecPerformancePpiGuid ## CONSUMES-
> gTopOfTemporaryRamPpiGuid ## PRODUCES-
> gEfiPeiFirmwareVolumeInfoPpiGuid ## PRODUCES-
> gFspTempRamExitPpiGuid ## CONSUMES--[Pcd]-
> gUefiCpuPkgTokenSpaceGuid.PcdPeiTemporaryRamStackSize ##
> CONSUMES- gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress
> ## CONSUMES- gIntelFsp2PkgTokenSpaceGuid.PcdFspTemporaryRamSize
> ## CONSUMES-
> gMinPlatformPkgTokenSpaceGuid.PcdSecSerialPortDebugEnable ##
> CONSUMES--[FixedPcd]-
> gIntelFsp2WrapperTokenSpaceGuid.PcdCpuMicrocodePatchAddress ##
> CONSUMES-
> gIntelFsp2WrapperTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize ##
> CONSUMES- gIntelFsp2WrapperTokenSpaceGuid.PcdFlashMicrocodeOffset
> ## CONSUMES-
> gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheAddress ##
> CONSUMES- gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheSize
> ## CONSUMES- gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress
> ## CONSUMES- gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection
> ## CONSUMESdiff --git
> a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapp
> erPlatformSecLib/SecGetPerformance.c
> b/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrap
> perPlatformSecLib/SecGetPerformance.c
> deleted file mode 100644
> index c4eeb2b188..0000000000
> ---
> a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapp
> erPlatformSecLib/SecGetPerformance.c
> +++ /dev/null
> @@ -1,89 +0,0 @@
> -/** @file- Sample to provide SecGetPerformance function.--Copyright (c)
> 2017, Intel Corporation. All rights reserved.<BR>-SPDX-License-Identifier:
> BSD-2-Clause-Patent--**/--#include <PiPei.h>--#include
> <Ppi/SecPerformance.h>-#include <Ppi/TopOfTemporaryRam.h>--#include
> <Library/BaseMemoryLib.h>-#include <Library/TimerLib.h>-#include
> <Library/DebugLib.h>--/**- This interface conveys performance information
> out of the Security (SEC) phase into PEI.-- This service is published by the SEC
> phase. The SEC phase handoff has an optional- EFI_PEI_PPI_DESCRIPTOR list
> as its final argument when control is passed from SEC into the- PEI
> Foundation. As such, if the platform supports collecting performance data in
> SEC,- this information is encapsulated into the data structure abstracted by
> this service.- This information is collected for the boot-strap processor (BSP)
> on IA-32.-- @param[in] PeiServices The pointer to the PEI Services Table.-
> @param[in] This The pointer to this instance of the
> PEI_SEC_PERFORMANCE_PPI.- @param[out] Performance The pointer to
> performance data collected in SEC phase.-- @retval EFI_SUCCESS The data
> was successfully returned.--**/-EFI_STATUS-EFIAPI-SecGetPerformance (-
> IN CONST EFI_PEI_SERVICES **PeiServices,- IN
> PEI_SEC_PERFORMANCE_PPI *This,- OUT
> FIRMWARE_SEC_PERFORMANCE *Performance- )-{- UINT32 Size;-
> UINT32 Count;- UINT32 TopOfTemporaryRam;- UINT64 Ticker;-
> VOID *TopOfTemporaryRamPpi;- EFI_STATUS Status;-- DEBUG
> ((DEBUG_INFO, "SecGetPerformance\n"));-- Status = (*PeiServices)-
> >LocatePpi (- PeiServices,-
> &gTopOfTemporaryRamPpiGuid,- 0,- NULL,-
> (VOID **) &TopOfTemporaryRamPpi- );- if (EFI_ERROR
> (Status)) {- return EFI_NOT_FOUND;- }- //- // |--------------| <-
> TopOfTemporaryRam - BL- // | List Ptr |- // |--------------|- // | BL RAM
> Start |- // |--------------|- // | BL RAM End |- // |--------------|- // |Number
> of BSPs|- // |--------------|- // | BIST |- // |--------------|- // | .... |-
> // |--------------|- // | TSC[63:32] |- // |--------------|- // | TSC[31:00] |- //
> |--------------|- //- TopOfTemporaryRam =
> (UINT32)(UINTN)TopOfTemporaryRamPpi - sizeof(UINT32);-
> TopOfTemporaryRam -= sizeof(UINT32) * 2;- Count = *(UINT32 *)
> (UINTN) (TopOfTemporaryRam - sizeof (UINT32));- Size = Count *
> sizeof (UINT32);-- Ticker = *(UINT64 *) (UINTN) (TopOfTemporaryRam -
> sizeof (UINT32) - Size - sizeof (UINT32) * 2);- Performance->ResetEnd =
> GetTimeInNanoSecond (Ticker);-- return EFI_SUCCESS;-}diff --git
> a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapp
> erPlatformSecLib/SecPlatformInformation.c
> b/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrap
> perPlatformSecLib/SecPlatformInformation.c
> deleted file mode 100644
> index 5b94ed2bef..0000000000
> ---
> a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapp
> erPlatformSecLib/SecPlatformInformation.c
> +++ /dev/null
> @@ -1,78 +0,0 @@
> -/** @file- Provide SecPlatformInformation function.--Copyright (c) 2017,
> Intel Corporation. All rights reserved.<BR>-SPDX-License-Identifier: BSD-2-
> Clause-Patent--**/--#include <PiPei.h>--#include
> <Ppi/SecPlatformInformation.h>-#include <Ppi/TopOfTemporaryRam.h>--
> #include <Library/BaseMemoryLib.h>-#include <Library/DebugLib.h>--/**-
> This interface conveys state information out of the Security (SEC) phase into
> PEI.-- @param[in] PeiServices Pointer to the PEI Services Table.-
> @param[in,out] StructureSize Pointer to the variable describing size of
> the input buffer.- @param[out] PlatformInformationRecord Pointer to the
> EFI_SEC_PLATFORM_INFORMATION_RECORD.-- @retval EFI_SUCCESS
> The data was successfully returned.- @retval EFI_BUFFER_TOO_SMALL The
> buffer was too small.--**/-EFI_STATUS-EFIAPI-SecPlatformInformation (- IN
> CONST EFI_PEI_SERVICES **PeiServices,- IN OUT UINT64
> *StructureSize,- OUT EFI_SEC_PLATFORM_INFORMATION_RECORD
> *PlatformInformationRecord- )-{- UINT32 *Bist;- UINT32 Size;- UINT32
> Count;- UINT32 TopOfTemporaryRam;- VOID
> *TopOfTemporaryRamPpi;- EFI_STATUS Status;-- DEBUG ((DEBUG_INFO,
> "SecPlatformInformation\n"));-- Status = (*PeiServices)->LocatePpi (-
> PeiServices,- &gTopOfTemporaryRamPpiGuid,-
> 0,- NULL,- (VOID **) &TopOfTemporaryRamPpi-
> );- if (EFI_ERROR (Status)) {- return EFI_NOT_FOUND;- }-- //- // The
> entries of BIST information, together with the number of them,- // reside in
> the bottom of stack, left untouched by normal stack operation.- // This
> routine copies the BIST information to the buffer pointed by- //
> PlatformInformationRecord for output.- //- TopOfTemporaryRam =
> (UINT32)(UINTN)TopOfTemporaryRamPpi - sizeof (UINT32);-
> TopOfTemporaryRam -= sizeof(UINT32) * 2;- Count = *((UINT32
> *)(UINTN) (TopOfTemporaryRam - sizeof (UINT32)));- Size = Count *
> sizeof (IA32_HANDOFF_STATUS);-- if ((*StructureSize) < (UINT64) Size) {-
> *StructureSize = Size;- return EFI_BUFFER_TOO_SMALL;- }--
> *StructureSize = Size;- Bist = (UINT32 *) (TopOfTemporaryRam - sizeof
> (UINT32) - Size);-- CopyMem (PlatformInformationRecord, Bist, Size);--
> return EFI_SUCCESS;-}diff --git
> a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapp
> erPlatformSecLib/SecRamInitData.c
> b/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrap
> perPlatformSecLib/SecRamInitData.c
> deleted file mode 100644
> index b356327b4c..0000000000
> ---
> a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapp
> erPlatformSecLib/SecRamInitData.c
> +++ /dev/null
> @@ -1,36 +0,0 @@
> -/** @file- Provide TempRamInitParams data.--Copyright (c) 2017, Intel
> Corporation. All rights reserved.<BR>-SPDX-License-Identifier: BSD-2-Clause-
> Patent--**/--#include <Library/PcdLib.h>-#include <FspEas.h>-#include
> "FsptCoreUpd.h"--typedef struct {- FSP_UPD_HEADER FspUpdHeader;-
> FSPT_CORE_UPD FsptCoreUpd;-} FSPT_UPD_CORE_DATA;--
> GLOBAL_REMOVE_IF_UNREFERENCED CONST FSPT_UPD_CORE_DATA
> FsptUpdDataPtr = {- {- 0x4450555F54505346,- 0x00,- { 0x00, 0x00, 0x00,
> 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,- 0x00, 0x00, 0x00, 0x00, 0x00,
> 0x00, 0x00- }- },- {- ((UINT32)FixedPcdGet64
> (PcdCpuMicrocodePatchAddress) + FixedPcdGet32
> (PcdFlashMicrocodeOffset)),- ((UINT32)FixedPcdGet64
> (PcdCpuMicrocodePatchRegionSize) - FixedPcdGet32
> (PcdFlashMicrocodeOffset)),- 0, // Set CodeRegionBase as 0, so that
> caching will be 4GB-(CodeRegionSize > LLCSize ? LLCSize : CodeRegionSize)
> will be used.- FixedPcdGet32 (PcdFlashCodeCacheSize),- { 0x00, 0x00,
> 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,- 0x00, 0x00, 0x00, 0x00,
> 0x00, 0x00- }- }-};-diff --git
> a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapp
> erPlatformSecLib/SecTempRamDone.c
> b/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrap
> perPlatformSecLib/SecTempRamDone.c
> deleted file mode 100644
> index 922e4ec204..0000000000
> ---
> a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapp
> erPlatformSecLib/SecTempRamDone.c
> +++ /dev/null
> @@ -1,73 +0,0 @@
> -/** @file- Provide SecTemporaryRamDone function.--Copyright (c) 2017 -
> 2019, Intel Corporation. All rights reserved.<BR>-SPDX-License-Identifier:
> BSD-2-Clause-Patent--**/--#include <PiPei.h>--#include
> <Ppi/TemporaryRamDone.h>-#include <Ppi/TempRamExitPpi.h>--#include
> <Library/BaseMemoryLib.h>-#include <Library/DebugLib.h>-#include
> <Library/PcdLib.h>-#include <Library/DebugAgentLib.h>-#include
> <Library/FspWrapperPlatformLib.h>-#include
> <Library/FspWrapperApiLib.h>-#include <Library/BoardInitLib.h>-#include
> <Library/PeiServicesTablePointerLib.h>--/**-This interface disables
> temporary memory in SEC Phase.-**/-VOID-EFIAPI-
> SecPlatformDisableTemporaryMemory (- VOID- )-{- EFI_STATUS
> Status;- VOID *TempRamExitParam;- CONST EFI_PEI_SERVICES
> **PeiServices;- FSP_TEMP_RAM_EXIT_PPI *TempRamExitPpi;-- DEBUG
> ((DEBUG_INFO, "SecPlatformDisableTemporaryMemory enter\n"));-- Status
> = BoardInitBeforeTempRamExit ();- ASSERT_EFI_ERROR (Status);-- if
> (PcdGet8 (PcdFspModeSelection) == 1) {- //- // FSP API mode- //-
> TempRamExitParam = UpdateTempRamExitParam ();- Status =
> CallTempRamExit (TempRamExitParam);- DEBUG ((DEBUG_INFO,
> "TempRamExit status: 0x%x\n", Status));- ASSERT_EFI_ERROR (Status);- }
> else {- //- // FSP Dispatch mode- //- PeiServices =
> GetPeiServicesTablePointer ();- Status = (*PeiServices)->LocatePpi (-
> PeiServices,- &gFspTempRamExitPpiGuid,- 0,-
> NULL,- (VOID **) &TempRamExitPpi- );-
> ASSERT_EFI_ERROR (Status);- if (EFI_ERROR (Status)) {- return;- }-
> TempRamExitPpi->TempRamExit (NULL);- }-- Status =
> BoardInitAfterTempRamExit ();- ASSERT_EFI_ERROR (Status);-- return ;-}diff
> --git
> a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.dsc
> b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.dsc
> index 2bc2b4126b..acdc31e708 100644
> --- a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.dsc
> +++
> b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.dsc
> @@ -126,7 +126,7 @@
> #######################################
> GpioExpanderLib|$(PLATFORM_BOARD_PACKAGE)/Library/BaseGpioExpan
> derLib/BaseGpioExpanderLib.inf
> I2cAccessLib|$(PLATFORM_BOARD_PACKAGE)/Library/PeiI2cAccessLib/PeiI2
> cAccessLib.inf-
> PlatformSecLib|$(PLATFORM_BOARD_PACKAGE)/FspWrapper/Library/SecFs
> pWrapperPlatformSecLib/SecFspWrapperPlatformSecLib.inf+
> PlatformSecLib|$(PLATFORM_PACKAGE)/FspWrapper/Library/SecFspWrapp
> erPlatformSecLib/SecFspWrapperPlatformSecLib.inf # Thunderbolt !if
> gKabylakeOpenBoardPkgTokenSpaceGuid.PcdTbtEnable == TRUEdiff --git
> a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc
> b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc
> index 77e4a6a610..4b07c0a684 100644
> ---
> a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc
> +++
> b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc
> @@ -166,7 +166,7 @@
> EcLib|$(PLATFORM_BOARD_PACKAGE)/Library/BaseEcLib/BaseEcLib.inf
> GpioExpanderLib|$(PLATFORM_BOARD_PACKAGE)/Library/BaseGpioExpan
> derLib/BaseGpioExpanderLib.inf
> I2cAccessLib|$(PLATFORM_BOARD_PACKAGE)/Library/PeiI2cAccessLib/PeiI2
> cAccessLib.inf-
> PlatformSecLib|$(PLATFORM_BOARD_PACKAGE)/FspWrapper/Library/SecFs
> pWrapperPlatformSecLib/SecFspWrapperPlatformSecLib.inf+
> PlatformSecLib|$(PLATFORM_PACKAGE)/FspWrapper/Library/SecFspWrapp
> erPlatformSecLib/SecFspWrapperPlatformSecLib.inf # Thunderbolt !if
> gKabylakeOpenBoardPkgTokenSpaceGuid.PcdTbtEnable == TRUE--
> 2.24.0.windows.2
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