Now that the SMRAM at the default SMBASE is honored everywhere necessary,
implement the actual detection. The (simple) steps are described in
previous patch "OvmfPkg/IndustryStandard: add MCH_DEFAULT_SMBASE* register
macros".

Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: Boris Ostrovsky <boris.ostrovsky@oracle.com>
Cc: Brijesh Singh <brijesh.singh@amd.com>
Cc: Igor Mammedov <imammedo@redhat.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Joao M Martins <joao.m.martins@oracle.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Jun Nakajima <jun.nakajima@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Paolo Bonzini <pbonzini@redhat.com>
Cc: Phillip Goerl <phillip.goerl@oracle.com>
Cc: Yingwen Chen <yingwen.chen@intel.com>
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=1512
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
---
 OvmfPkg/PlatformPei/MemDetect.c | 11 ++++++++++-
 1 file changed, 10 insertions(+), 1 deletion(-)

diff --git a/OvmfPkg/PlatformPei/MemDetect.c b/OvmfPkg/PlatformPei/MemDetect.c
index 8fdc9c2ed7c9..3364193b4952 100644
--- a/OvmfPkg/PlatformPei/MemDetect.c
+++ b/OvmfPkg/PlatformPei/MemDetect.c
@@ -98,14 +98,23 @@ Q35SmramAtDefaultSmbaseInitialization (
   VOID
   )
 {
+  UINTN         CtlReg;
+  UINT8         CtlRegVal;
   RETURN_STATUS PcdStatus;
 
   ASSERT (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID);
 
-  mQ35SmramAtDefaultSmbase = FALSE;
+  CtlReg = DRAMC_REGISTER_Q35 (MCH_DEFAULT_SMBASE_CTL);
+  PciWrite8 (CtlReg, MCH_DEFAULT_SMBASE_QUERY);
+  CtlRegVal = PciRead8 (CtlReg);
+
+  mQ35SmramAtDefaultSmbase = (BOOLEAN)(CtlRegVal == MCH_DEFAULT_SMBASE_IN_RAM);
   PcdStatus = PcdSetBoolS (PcdQ35SmramAtDefaultSmbase,
                 mQ35SmramAtDefaultSmbase);
   ASSERT_RETURN_ERROR (PcdStatus);
+  if (mQ35SmramAtDefaultSmbase) {
+    DEBUG ((DEBUG_INFO, "%a: SMRAM at default SMBASE found\n", __FUNCTION__));
+  }
 }
 
 
-- 
2.19.1.3.g30247aa5d201


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