MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c | 54 +++---------------------- 1 file changed, 5 insertions(+), 49 deletions(-)
SD host controller specification section 3.9 recommends that controller's bus timing should be switched after card's bus timing has been switched. In current eMMC driver implementation every host controller switch has been done before call to EmmcSwitchBusTiming which is causing issues on some eMMC controllers. In HS200 switch sequence we removed stopping and starting the SD clock when switching the host controller timing. Stopping the clock before bus timing switch is only neccessary if preset value enable is set in host controller. Current code doesn't check if this field is enabled or doesn't support this feature for any other bus timing change so it has been removed. Tests performed: - eMMC enumeration and OS boot in HS400 - eMMC enumeration and OS boot in HS200 - eMMC enumeration and OS boot in high speed SDR 8bit @52MHz Tests have been performed on 2 eMMC host controllers. One that has been failing with old driver and one that has been passing with old driver. Both controllers pass all tests with multiple eMMC devices used. Note: We were unable to test DDR speed mode because on test machines both new flow and old flow was failing with this speed. I suspect it is a hardware problem. Cc: Hao A Wu <hao.a.wu@intel.com> Cc: Marcin Wojtas <mw@semihalf.com> Albecki, Mateusz (1): MdeModulePkg/SdMmcPciHcDxe: Fix bus timing switch sequence MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c | 54 +++---------------------- 1 file changed, 5 insertions(+), 49 deletions(-) -- 2.14.1.windows.1 -------------------------------------------------------------------- Intel Technology Poland sp. z o.o. ul. Slowackiego 173 | 80-298 Gdansk | Sad Rejonowy Gdansk Polnoc | VII Wydzial Gospodarczy Krajowego Rejestru Sadowego - KRS 101882 | NIP 957-07-52-316 | Kapital zakladowy 200.000 PLN. Ta wiadomosc wraz z zalacznikami jest przeznaczona dla okreslonego adresata i moze zawierac informacje poufne. W razie przypadkowego otrzymania tej wiadomosci, prosimy o powiadomienie nadawcy oraz trwale jej usuniecie; jakiekolwiek przegladanie lub rozpowszechnianie jest zabronione. This e-mail and any attachments may contain confidential material for the sole use of the intended recipient(s). If you are not the intended recipient, please contact the sender and delete all copies; any review or distribution by others is strictly prohibited. -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#47831): https://edk2.groups.io/g/devel/message/47831 Mute This Topic: https://groups.io/mt/34262001/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=-=-=-=-=-=-=-=-=-=-=-
Hi Mateusz, For the v2, could you please push the patches to some repo, so that it would be easy to fetch and test? Best regards, Marcin pon., 23 wrz 2019 o 10:37 Albecki, Mateusz <mateusz.albecki@intel.com> napisał(a): > SD host controller specification section 3.9 recommends that controller's > bus timing > should be switched after card's bus timing has been switched. In current > eMMC > driver implementation every host controller switch has been done before > call to > EmmcSwitchBusTiming which is causing issues on some eMMC controllers. > > In HS200 switch sequence we removed stopping and starting the SD clock when > switching the host controller timing. Stopping the clock before bus timing > switch is only neccessary if preset value enable is set in host controller. > Current code doesn't check if this field is enabled or doesn't support > this feature for any other bus timing change so it has been removed. > > Tests performed: > - eMMC enumeration and OS boot in HS400 > - eMMC enumeration and OS boot in HS200 > - eMMC enumeration and OS boot in high speed SDR 8bit @52MHz > > Tests have been performed on 2 eMMC host controllers. One that has been > failing > with old driver and one that has been passing with old driver. Both > controllers > pass all tests with multiple eMMC devices used. > > Note: We were unable to test DDR speed mode because on test machines both > new flow > and old flow was failing with this speed. I suspect it is a hardware > problem. > > Cc: Hao A Wu <hao.a.wu@intel.com> > Cc: Marcin Wojtas <mw@semihalf.com> > > Albecki, Mateusz (1): > MdeModulePkg/SdMmcPciHcDxe: Fix bus timing switch sequence > > MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c | 54 > +++---------------------- > 1 file changed, 5 insertions(+), 49 deletions(-) > > -- > 2.14.1.windows.1 > > -------------------------------------------------------------------- > > Intel Technology Poland sp. z o.o. > ul. Slowackiego 173 | 80-298 Gdansk | Sad Rejonowy Gdansk Polnoc | VII > Wydzial Gospodarczy Krajowego Rejestru Sadowego - KRS 101882 | NIP > 957-07-52-316 | Kapital zakladowy 200.000 PLN. > > Ta wiadomosc wraz z zalacznikami jest przeznaczona dla okreslonego > adresata i moze zawierac informacje poufne. W razie przypadkowego > otrzymania tej wiadomosci, prosimy o powiadomienie nadawcy oraz trwale jej > usuniecie; jakiekolwiek > przegladanie lub rozpowszechnianie jest zabronione. > This e-mail and any attachments may contain confidential material for the > sole use of the intended recipient(s). If you are not the intended > recipient, please contact the sender and delete all copies; any review or > distribution by > others is strictly prohibited. > > -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#48078): https://edk2.groups.io/g/devel/message/48078 Mute This Topic: https://groups.io/mt/34262001/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=-=-=-=-=-=-=-=-=-=-=-
Hello Marcin, I have uploaded the V2 series to my fork. You can get the patch at: https://github.com/hwu25/edk2/tree/emmc_busmode_v2 Best Regards, Hao Wu From: Marcin Wojtas [mailto:mw@semihalf.com] Sent: Thursday, September 26, 2019 3:25 PM To: Albecki, Mateusz Cc: edk2-devel-groups-io; Wu, Hao A Subject: Re: [PATCH 0/1] Fix eMMC bus timing switch issue Hi Mateusz, For the v2, could you please push the patches to some repo, so that it would be easy to fetch and test? Best regards, Marcin pon., 23 wrz 2019 o 10:37 Albecki, Mateusz <mateusz.albecki@intel.com<mailto:mateusz.albecki@intel.com>> napisał(a): SD host controller specification section 3.9 recommends that controller's bus timing should be switched after card's bus timing has been switched. In current eMMC driver implementation every host controller switch has been done before call to EmmcSwitchBusTiming which is causing issues on some eMMC controllers. In HS200 switch sequence we removed stopping and starting the SD clock when switching the host controller timing. Stopping the clock before bus timing switch is only neccessary if preset value enable is set in host controller. Current code doesn't check if this field is enabled or doesn't support this feature for any other bus timing change so it has been removed. Tests performed: - eMMC enumeration and OS boot in HS400 - eMMC enumeration and OS boot in HS200 - eMMC enumeration and OS boot in high speed SDR 8bit @52MHz Tests have been performed on 2 eMMC host controllers. One that has been failing with old driver and one that has been passing with old driver. Both controllers pass all tests with multiple eMMC devices used. Note: We were unable to test DDR speed mode because on test machines both new flow and old flow was failing with this speed. I suspect it is a hardware problem. Cc: Hao A Wu <hao.a.wu@intel.com<mailto:hao.a.wu@intel.com>> Cc: Marcin Wojtas <mw@semihalf.com<mailto:mw@semihalf.com>> Albecki, Mateusz (1): MdeModulePkg/SdMmcPciHcDxe: Fix bus timing switch sequence MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c | 54 +++---------------------- 1 file changed, 5 insertions(+), 49 deletions(-) -- 2.14.1.windows.1 -------------------------------------------------------------------- Intel Technology Poland sp. z o.o. ul. Slowackiego 173 | 80-298 Gdansk | Sad Rejonowy Gdansk Polnoc | VII Wydzial Gospodarczy Krajowego Rejestru Sadowego - KRS 101882 | NIP 957-07-52-316 | Kapital zakladowy 200.000 PLN. Ta wiadomosc wraz z zalacznikami jest przeznaczona dla okreslonego adresata i moze zawierac informacje poufne. W razie przypadkowego otrzymania tej wiadomosci, prosimy o powiadomienie nadawcy oraz trwale jej usuniecie; jakiekolwiek przegladanie lub rozpowszechnianie jest zabronione. This e-mail and any attachments may contain confidential material for the sole use of the intended recipient(s). If you are not the intended recipient, please contact the sender and delete all copies; any review or distribution by others is strictly prohibited. -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#48168): https://edk2.groups.io/g/devel/message/48168 Mute This Topic: https://groups.io/mt/34262001/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=-=-=-=-=-=-=-=-=-=-=-
Thanks! Everything keep working on my boards: Tested-by: Marcin Wojtas <mw@semihalf.com> Best regards, Marcin pt., 27 wrz 2019 o 03:38 Wu, Hao A <hao.a.wu@intel.com> napisał(a): > Hello Marcin, > > > > I have uploaded the V2 series to my fork. > > You can get the patch at: > > https://github.com/hwu25/edk2/tree/emmc_busmode_v2 > > > > Best Regards, > > Hao Wu > > > > *From:* Marcin Wojtas [mailto:mw@semihalf.com] > *Sent:* Thursday, September 26, 2019 3:25 PM > *To:* Albecki, Mateusz > *Cc:* edk2-devel-groups-io; Wu, Hao A > *Subject:* Re: [PATCH 0/1] Fix eMMC bus timing switch issue > > > > Hi Mateusz, > > > > For the v2, could you please push the patches to some repo, so that it > would be easy to fetch and test? > > > > Best regards, > > Marcin > > > > pon., 23 wrz 2019 o 10:37 Albecki, Mateusz <mateusz.albecki@intel.com> > napisał(a): > > SD host controller specification section 3.9 recommends that controller's > bus timing > should be switched after card's bus timing has been switched. In current > eMMC > driver implementation every host controller switch has been done before > call to > EmmcSwitchBusTiming which is causing issues on some eMMC controllers. > > In HS200 switch sequence we removed stopping and starting the SD clock when > switching the host controller timing. Stopping the clock before bus timing > switch is only neccessary if preset value enable is set in host > controller. > Current code doesn't check if this field is enabled or doesn't support > this feature for any other bus timing change so it has been removed. > > Tests performed: > - eMMC enumeration and OS boot in HS400 > - eMMC enumeration and OS boot in HS200 > - eMMC enumeration and OS boot in high speed SDR 8bit @52MHz > > Tests have been performed on 2 eMMC host controllers. One that has been > failing > with old driver and one that has been passing with old driver. Both > controllers > pass all tests with multiple eMMC devices used. > > Note: We were unable to test DDR speed mode because on test machines both > new flow > and old flow was failing with this speed. I suspect it is a hardware > problem. > > Cc: Hao A Wu <hao.a.wu@intel.com> > Cc: Marcin Wojtas <mw@semihalf.com> > > Albecki, Mateusz (1): > MdeModulePkg/SdMmcPciHcDxe: Fix bus timing switch sequence > > MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c | 54 > +++---------------------- > 1 file changed, 5 insertions(+), 49 deletions(-) > > -- > 2.14.1.windows.1 > > -------------------------------------------------------------------- > > Intel Technology Poland sp. z o.o. > ul. Slowackiego 173 | 80-298 Gdansk | Sad Rejonowy Gdansk Polnoc | VII > Wydzial Gospodarczy Krajowego Rejestru Sadowego - KRS 101882 | NIP > 957-07-52-316 | Kapital zakladowy 200.000 PLN. > > Ta wiadomosc wraz z zalacznikami jest przeznaczona dla okreslonego > adresata i moze zawierac informacje poufne. W razie przypadkowego > otrzymania tej wiadomosci, prosimy o powiadomienie nadawcy oraz trwale jej > usuniecie; jakiekolwiek > przegladanie lub rozpowszechnianie jest zabronione. > This e-mail and any attachments may contain confidential material for the > sole use of the intended recipient(s). If you are not the intended > recipient, please contact the sender and delete all copies; any review or > distribution by > others is strictly prohibited. > > -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#48222): https://edk2.groups.io/g/devel/message/48222 Mute This Topic: https://groups.io/mt/34262001/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=-=-=-=-=-=-=-=-=-=-=-
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