Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/VtdReg.c | 30 +++++++++++++++++++++++++++--- Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmrPei.c | 73 ++++++++++++++++++++++++++++++++++++++++++++++++++----------------------- Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/VtdReg.c | 29 ++++++++++++++++++++++++++--- Silicon/Intel/IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSamplePei/PlatformVTdInfoSamplePei.c | 9 +++++---- Silicon/Intel/IntelSiliconPkg/Library/GetVtdPmrAlignmentLib/GetVtdPmrAlignmentLib.c | 164 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmrPei.inf | 5 ++++- Silicon/Intel/IntelSiliconPkg/Include/Library/GetVtdPmrAlignmentLib.h | 25 +++++++++++++++++++++++++ Silicon/Intel/IntelSiliconPkg/Include/SysMemInfoHob.h | 21 +++++++++++++++++++++ Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec | 11 +++++++++-- Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dsc | 3 ++- Silicon/Intel/IntelSiliconPkg/Library/GetVtdPmrAlignmentLib/GetVtdPmrAlignmentLib.inf | 32 ++++++++++++++++++++++++++++++++ 11 files changed, 365 insertions(+), 37 deletions(-)
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1770
1) IOMMU PMR feature should be generic to support different hardware
architecture. Platforms may request no overlap between PMR regions
and system reserve memory. Create an interface to control PLMR/PHMR
regions. It allows silicon code to adjust PLMR/PHMR region base on
the project needs.
2) DisableDMAr Function Code Optimization
Optimize the flow to follow the VT-d spec requirements.
3) Renamed InitDmar() to InitGlobalVtd()
The oringal function name is misleading
4) A new GetVtdPmrAlignmentLib for silicon code to get
PMR alignment values.
Signed-off-by: Evelyn Wang <iwen.evelyn.wang@intel.com>
Cc: Jenny Huang <jenny.huang@intel.com>
Cc: More Shih <more.shih@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Rangasai V Chaganty <rangasai.v.chaganty@intel.com>
---
Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/VtdReg.c | 30 +++++++++++++++++++++++++++---
Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmrPei.c | 73 ++++++++++++++++++++++++++++++++++++++++++++++++++-----------------------
Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/VtdReg.c | 29 ++++++++++++++++++++++++++---
Silicon/Intel/IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSamplePei/PlatformVTdInfoSamplePei.c | 9 +++++----
Silicon/Intel/IntelSiliconPkg/Library/GetVtdPmrAlignmentLib/GetVtdPmrAlignmentLib.c | 164 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmrPei.inf | 5 ++++-
Silicon/Intel/IntelSiliconPkg/Include/Library/GetVtdPmrAlignmentLib.h | 25 +++++++++++++++++++++++++
Silicon/Intel/IntelSiliconPkg/Include/SysMemInfoHob.h | 21 +++++++++++++++++++++
Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec | 11 +++++++++--
Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dsc | 3 ++-
Silicon/Intel/IntelSiliconPkg/Library/GetVtdPmrAlignmentLib/GetVtdPmrAlignmentLib.inf | 32 ++++++++++++++++++++++++++++++++
11 files changed, 365 insertions(+), 37 deletions(-)
diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/VtdReg.c b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/VtdReg.c
index 22bf821d2b..699639ba88 100644
--- a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/VtdReg.c
+++ b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/VtdReg.c
@@ -1,6 +1,6 @@
/** @file
- Copyright (c) 2017 - 2018, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
@@ -309,6 +309,8 @@ DisableDmar (
UINTN Index;
UINTN SubIndex;
UINT32 Reg32;
+ UINT32 Status;
+ UINT32 Command;
for (Index = 0; Index < mVtdUnitNumber; Index++) {
DEBUG((DEBUG_INFO, ">>>>>>DisableDmar() for engine [%d] \n", Index));
@@ -319,9 +321,31 @@ DisableDmar (
FlushWriteBuffer (Index);
//
- // Disable VTd
+ // Disable Dmar
//
- MmioWrite32 (mVtdUnitInformation[Index].VtdUnitBaseAddress + R_GCMD_REG, B_GMCD_REG_SRTP);
+ //
+ // Set TE (Translation Enable: BIT31) of Global command register to zero
+ //
+ Reg32 = MmioRead32 (mVtdUnitInformation[Index].VtdUnitBaseAddress + R_GSTS_REG);
+ Status = (Reg32 & 0x96FFFFFF); // Reset the one-shot bits
+ Command = (Status & ~B_GMCD_REG_TE);
+ MmioWrite32 (mVtdUnitInformation[Index].VtdUnitBaseAddress + R_GCMD_REG, Command);
+
+ //
+ // Poll on TE Status bit of Global status register to become zero
+ //
+ do {
+ Reg32 = MmioRead32 (mVtdUnitInformation[Index].VtdUnitBaseAddress + R_GSTS_REG);
+ } while ((Reg32 & B_GSTS_REG_TE) == B_GSTS_REG_TE);
+
+ //
+ // Set SRTP (Set Root Table Pointer: BIT30) of Global command register in order to update the root table pointerDisable VTd
+ //
+ Reg32 = MmioRead32 (mVtdUnitInformation[Index].VtdUnitBaseAddress + R_GSTS_REG);
+ Status = (Reg32 & 0x96FFFFFF); // Reset the one-shot bits
+ Command = (Status | B_GMCD_REG_SRTP);
+ MmioWrite32 (mVtdUnitInformation[Index].VtdUnitBaseAddress + R_GCMD_REG, Command);
+
do {
Reg32 = MmioRead32 (mVtdUnitInformation[Index].VtdUnitBaseAddress + R_GSTS_REG);
} while((Reg32 & B_GSTS_REG_RTPS) == 0);
diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmrPei.c b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmrPei.c
index ca099ed71d..14da18289e 100644
--- a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmrPei.c
+++ b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmrPei.c
@@ -1,6 +1,6 @@
/** @file
- Copyright (c) 2017 - 2018, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -20,7 +20,7 @@
#include <Ppi/VtdInfo.h>
#include <Ppi/MemoryDiscovered.h>
#include <Ppi/EndOfPeiPhase.h>
-
+#include <SysMemInfoHob.h>
#include "IntelVTdPmrPei.h"
EFI_GUID mVTdInfoGuid = {
@@ -424,38 +424,69 @@ InitDmaProtection (
UINTN MemoryAlignment;
UINTN LowBottom;
UINTN LowTop;
- UINTN HighBottom;
+ UINT64 HighBottom;
UINT64 HighTop;
DMA_BUFFER_INFO *DmaBufferInfo;
VOID *Hob;
EFI_PEI_PPI_DESCRIPTOR *OldDescriptor;
EDKII_IOMMU_PPI *OldIoMmuPpi;
+ SYSTEM_MEM_INFO_HOB *SysMemHob;
+ VOID *SysMemHobPtr;
+
+ SysMemHob = NULL;
+
Hob = GetFirstGuidHob (&mDmaBufferInfoGuid);
DmaBufferInfo = GET_GUID_HOB_DATA(Hob);
- DEBUG ((DEBUG_INFO, " DmaBufferSize : 0x%x\n", DmaBufferInfo->DmaBufferSize));
+ SysMemHobPtr = GetFirstGuidHob (&gSysMemInfoDataHobGuid);
+
+ if (SysMemHobPtr == NULL) {
+ //
+ // Calcuate the PMR memory alignment
+ //
+ LowMemoryAlignment = GetLowMemoryAlignment (VTdInfo, VTdInfo->EngineMask);
+ HighMemoryAlignment = GetHighMemoryAlignment (VTdInfo, VTdInfo->EngineMask);
+ if (LowMemoryAlignment < HighMemoryAlignment) {
+ MemoryAlignment = (UINTN)HighMemoryAlignment;
+ } else {
+ MemoryAlignment = LowMemoryAlignment;
+ }
+ ASSERT (DmaBufferInfo->DmaBufferSize == ALIGN_VALUE(DmaBufferInfo->DmaBufferSize, MemoryAlignment));
+
+ //
+ // Allocate memory for DMA buffer
+ //
+ DmaBufferInfo->DmaBufferBase = (UINTN)AllocateAlignedPages (EFI_SIZE_TO_PAGES(DmaBufferInfo->DmaBufferSize), MemoryAlignment);
+ ASSERT (DmaBufferInfo->DmaBufferBase != 0);
+ if (DmaBufferInfo->DmaBufferBase == 0) {
+ DEBUG ((DEBUG_INFO, " InitDmaProtection : OutOfResource\n"));
+ return EFI_OUT_OF_RESOURCES;
+ }
+
+ DmaBufferInfo->DmaBufferCurrentTop = DmaBufferInfo->DmaBufferBase + DmaBufferInfo->DmaBufferSize;
+ DmaBufferInfo->DmaBufferCurrentBottom = DmaBufferInfo->DmaBufferBase;
+ LowBottom = 0;
+ LowTop = DmaBufferInfo->DmaBufferBase;
+ HighBottom = DmaBufferInfo->DmaBufferBase + DmaBufferInfo->DmaBufferSize;
+ HighTop = LShiftU64 (1, VTdInfo->HostAddressWidth + 1);
- LowMemoryAlignment = GetLowMemoryAlignment (VTdInfo, VTdInfo->EngineMask);
- HighMemoryAlignment = GetHighMemoryAlignment (VTdInfo, VTdInfo->EngineMask);
- if (LowMemoryAlignment < HighMemoryAlignment) {
- MemoryAlignment = (UINTN)HighMemoryAlignment;
} else {
- MemoryAlignment = LowMemoryAlignment;
- }
- ASSERT (DmaBufferInfo->DmaBufferSize == ALIGN_VALUE(DmaBufferInfo->DmaBufferSize, MemoryAlignment));
- DmaBufferInfo->DmaBufferBase = (UINTN)AllocateAlignedPages (EFI_SIZE_TO_PAGES(DmaBufferInfo->DmaBufferSize), MemoryAlignment);
- ASSERT (DmaBufferInfo->DmaBufferBase != 0);
- if (DmaBufferInfo->DmaBufferBase == 0) {
- DEBUG ((DEBUG_INFO, " InitDmaProtection : OutOfResource\n"));
- return EFI_OUT_OF_RESOURCES;
+
+ //
+ // Get the PMR ranges information for the system hob
+ //
+ SysMemHob = GET_GUID_HOB_DATA (SysMemHobPtr);
+ DmaBufferInfo->DmaBufferBase = SysMemHob->ProtectedLowLimit << 20;
+ LowBottom = SysMemHob->ProtectedLowBase;
+ LowTop = SysMemHob->ProtectedLowLimit << 20;
+ HighBottom = (UINT64) BASE_4GB;
+ HighTop = (UINT64) SysMemHob->ProtectedHighLimit << 20;
}
+ DEBUG ((DEBUG_INFO, " DmaBufferSize : 0x%x\n", DmaBufferInfo->DmaBufferSize));
DEBUG ((DEBUG_INFO, " DmaBufferBase : 0x%x\n", DmaBufferInfo->DmaBufferBase));
- DmaBufferInfo->DmaBufferCurrentTop = DmaBufferInfo->DmaBufferBase + DmaBufferInfo->DmaBufferSize;
- DmaBufferInfo->DmaBufferCurrentBottom = DmaBufferInfo->DmaBufferBase;
-
//
// (Re)Install PPI.
//
@@ -472,10 +503,6 @@ InitDmaProtection (
}
ASSERT_EFI_ERROR (Status);
- LowBottom = 0;
- LowTop = DmaBufferInfo->DmaBufferBase;
- HighBottom = DmaBufferInfo->DmaBufferBase + DmaBufferInfo->DmaBufferSize;
- HighTop = LShiftU64 (1, VTdInfo->HostAddressWidth + 1);
Status = SetDmaProtectedRange (
VTdInfo,
diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/VtdReg.c b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/VtdReg.c
index 4774a2ae5b..c9669426aa 100644
--- a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/VtdReg.c
+++ b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/VtdReg.c
@@ -1,6 +1,6 @@
/** @file
- Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -197,6 +197,8 @@ DisableDmar (
)
{
UINT32 Reg32;
+ UINT32 Status;
+ UINT32 Command;
DEBUG((DEBUG_INFO, ">>>>>>DisableDmar() for engine [%x] \n", VtdUnitBaseAddress));
@@ -206,9 +208,30 @@ DisableDmar (
FlushWriteBuffer (VtdUnitBaseAddress);
//
- // Disable VTd
+ // Disable Dmar
//
- MmioWrite32 (VtdUnitBaseAddress + R_GCMD_REG, B_GMCD_REG_SRTP);
+ //
+ // Set TE (Translation Enable: BIT31) of Global command register to zero
+ //
+ Reg32 = MmioRead32 (VtdUnitBaseAddress + R_GSTS_REG);
+ Status = (Reg32 & 0x96FFFFFF); // Reset the one-shot bits
+ Command = (Status & ~B_GMCD_REG_TE);
+ MmioWrite32 (VtdUnitBaseAddress + R_GCMD_REG, Command);
+
+ //
+ // Poll on TE Status bit of Global status register to become zero
+ //
+ do {
+ Reg32 = MmioRead32 (VtdUnitBaseAddress + R_GSTS_REG);
+ } while ((Reg32 & B_GSTS_REG_TE) == B_GSTS_REG_TE);
+
+ //
+ // Set SRTP (Set Root Table Pointer: BIT30) of Global command register in order to update the root table pointerDisable VTd
+ //
+ Reg32 = MmioRead32 (VtdUnitBaseAddress + R_GSTS_REG);
+ Status = (Reg32 & 0x96FFFFFF); // Reset the one-shot bits
+ Command = (Status | B_GMCD_REG_SRTP);
+ MmioWrite32 (VtdUnitBaseAddress + R_GCMD_REG, Command);
do {
Reg32 = MmioRead32 (VtdUnitBaseAddress + R_GSTS_REG);
} while((Reg32 & B_GSTS_REG_RTPS) == 0);
diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSamplePei/PlatformVTdInfoSamplePei.c b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSamplePei/PlatformVTdInfoSamplePei.c
index 3698c3d3f1..6f6c14f7a9 100644
--- a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSamplePei/PlatformVTdInfoSamplePei.c
+++ b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSamplePei/PlatformVTdInfoSamplePei.c
@@ -1,7 +1,7 @@
/** @file
Platform VTd Info Sample PEI driver.
- Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
@@ -166,15 +166,16 @@ EFI_PEI_PPI_DESCRIPTOR mPlatformVTdNoIgdInfoSampleDesc = {
/**
Initialize VTd register.
+ Initialize the VTd hardware unit which has INCLUDE_PCI_ALL set
**/
VOID
-InitDmar (
+InitGlobalVtd (
VOID
)
{
UINT32 MchBar;
- DEBUG ((DEBUG_INFO, "InitDmar\n"));
+ DEBUG ((DEBUG_INFO, "InitGlobalVtd\n"));
MchBar = PciRead32 (PCI_LIB_ADDRESS(0, 0, 0, R_SA_MCHBAR)) & ~BIT0;
PciWrite32 (PCI_LIB_ADDRESS(0, 0, 0, R_SA_MCHBAR), 0xFED10000 | BIT0);
@@ -346,7 +347,7 @@ PlatformVTdInfoSampleInitialize (
DEBUG ((DEBUG_INFO, "SiliconInitialized - %x\n", SiliconInitialized));
if (!SiliconInitialized) {
Status = PeiServicesNotifyPpi (&mSiliconInitializedNotifyList);
- InitDmar ();
+ InitGlobalVtd ();
Status = PeiServicesInstallPpi (&mPlatformVTdNoIgdInfoSampleDesc);
ASSERT_EFI_ERROR (Status);
diff --git a/Silicon/Intel/IntelSiliconPkg/Library/GetVtdPmrAlignmentLib/GetVtdPmrAlignmentLib.c b/Silicon/Intel/IntelSiliconPkg/Library/GetVtdPmrAlignmentLib/GetVtdPmrAlignmentLib.c
new file mode 100644
index 0000000000..10fbd1d80a
--- /dev/null
+++ b/Silicon/Intel/IntelSiliconPkg/Library/GetVtdPmrAlignmentLib/GetVtdPmrAlignmentLib.c
@@ -0,0 +1,164 @@
+/** @file
+ Library to get Global VTd PMR alignment information.
+ Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+#include <PiPei.h>
+#include <Library/BaseLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/IoLib.h>
+#include <Library/DebugLib.h>
+#include <Library/GetVtdPmrAlignmentLib.h>
+#include <Library/PeiServicesLib.h>
+#include <IndustryStandard/DmaRemappingReportingTable.h>
+#include <IndustryStandard/VTd.h>
+
+typedef union {
+ struct {
+ UINT32 Low;
+ UINT32 High;
+ } Data32;
+ UINT64 Data;
+} UINT64_STRUCT;
+
+/**
+ Get protected low memory alignment.
+
+ @param HostAddressWidth The host address width.
+ @param VtdUnitBaseAddress The base address of the VTd engine.
+
+ @return protected low memory alignment.
+**/
+UINT32
+GetGlobalVTdPlmrAlignment (
+ IN UINT8 HostAddressWidth,
+ IN UINTN VtdUnitBaseAddress
+ )
+{
+ UINT32 Data32;
+
+ MmioWrite32 (VtdUnitBaseAddress + R_PMEN_LOW_BASE_REG, 0xFFFFFFFF);
+ Data32 = MmioRead32 (VtdUnitBaseAddress + R_PMEN_LOW_BASE_REG);
+ Data32 = ~Data32 + 1;
+
+ return Data32;
+}
+
+/**
+ Get protected high memory alignment.
+
+ @param HostAddressWidth The host address width.
+ @param VtdUnitBaseAddress The base address of the VTd engine.
+
+ @return protected high memory alignment.
+**/
+UINT64_STRUCT
+GetGlobalVTdPhmrAlignment (
+ IN UINT8 HostAddressWidth,
+ IN UINTN VtdUnitBaseAddress
+ )
+{
+ UINT64_STRUCT Data64;
+
+ MmioWrite64 (VtdUnitBaseAddress + R_PMEN_HIGH_BASE_REG, 0xFFFFFFFFFFFFFFFF);
+ Data64.Data = MmioRead64 (VtdUnitBaseAddress + R_PMEN_HIGH_BASE_REG);
+ Data64.Data = ~Data64.Data + 1;
+ Data64.Data = Data64.Data & (LShiftU64 (1, HostAddressWidth) - 1);
+
+ return Data64;
+}
+
+/**
+ Get Global VT-d Protected Memory Aignment.
+
+ @return protected high memory alignment.
+**/
+UINTN
+GetGlobalVtdPmrAlignment (
+)
+{
+ UINT32 LowMemoryAlignment;
+ UINT64_STRUCT HighMemoryAlignment;
+ UINTN MemoryAlignment;
+ UINT32 GlobalVTdBaseAddress;
+ EFI_STATUS Status;
+ UINTN VtdIndex;
+ EFI_ACPI_DMAR_STRUCTURE_HEADER *DmarHeader;
+ EFI_ACPI_DMAR_DRHD_HEADER *DrhdHeader;
+ EFI_ACPI_DMAR_HEADER *AcpiDmarTable;
+
+ //
+ // Initialization
+ //
+ GlobalVTdBaseAddress = 0xFFFFFFFF;
+ LowMemoryAlignment = 0;
+ HighMemoryAlignment.Data = 0;
+ MemoryAlignment = 0;
+ Status = EFI_UNSUPPORTED;
+ VtdIndex = 0;
+ DmarHeader = NULL;
+ DrhdHeader = NULL;
+ AcpiDmarTable = NULL;
+
+ //
+ // Fatch the PEI DMAR ACPU Table that created and installed in PlatformVTdInfoSamplePei.c
+ //
+ Status = PeiServicesLocatePpi (
+ &gEdkiiVTdInfoPpiGuid,
+ 0,
+ NULL,
+ (VOID **)&AcpiDmarTable
+ );
+ if (EFI_ERROR (Status)) {
+
+ DEBUG ((DEBUG_ERROR, "PeiServicesLocatePpi gEdkiiVTdInfoPpiGuid failed. Status: %r\n", Status));
+ MemoryAlignment = SIZE_1MB;
+ return MemoryAlignment;
+
+ } else {
+
+ //
+ // Seatch the DRHD structure with INCLUDE_PCI_ALL flag Set -> Global VT-d
+ //
+ DmarHeader = (EFI_ACPI_DMAR_STRUCTURE_HEADER *)((UINTN)(AcpiDmarTable + 1));
+ while ((UINTN)DmarHeader < (UINTN)AcpiDmarTable + AcpiDmarTable->Header.Length) {
+ switch (DmarHeader->Type) {
+ case EFI_ACPI_DMAR_TYPE_DRHD:
+ DrhdHeader = (EFI_ACPI_DMAR_DRHD_HEADER *) DmarHeader;
+ if ((DrhdHeader->Flags & BIT0) == BIT0) {
+ GlobalVTdBaseAddress = (UINT32)DrhdHeader->RegisterBaseAddress;
+ DEBUG ((DEBUG_INFO," GlobalVTdBaseAddress: %x\n", GlobalVTdBaseAddress));
+ }
+ VtdIndex++;
+
+ break;
+
+ default:
+ break;
+ }
+ DmarHeader = (EFI_ACPI_DMAR_STRUCTURE_HEADER *)((UINTN)DmarHeader + DmarHeader->Length);
+ }
+
+ if (GlobalVTdBaseAddress == 0xFFFFFFFF) {
+
+ DEBUG ((DEBUG_ERROR, "Error! Please set INCLUDE_PCI_ALL flag to the Global VT-d\n"));
+ MemoryAlignment = SIZE_1MB;
+
+ } else {
+ //
+ // Get the alignment information from VT-d register
+ //
+ LowMemoryAlignment = GetGlobalVTdPlmrAlignment (AcpiDmarTable->HostAddressWidth, GlobalVTdBaseAddress);
+ HighMemoryAlignment = GetGlobalVTdPhmrAlignment (AcpiDmarTable->HostAddressWidth, GlobalVTdBaseAddress);
+ if (LowMemoryAlignment < HighMemoryAlignment.Data) {
+ MemoryAlignment = (UINTN)HighMemoryAlignment.Data;
+ } else {
+ MemoryAlignment = LowMemoryAlignment;
+ }
+ }
+ }
+
+ return MemoryAlignment;
+}
diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmrPei.inf b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmrPei.inf
index 39b914cd00..2f6599d818 100644
--- a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmrPei.inf
+++ b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmrPei.inf
@@ -4,7 +4,7 @@
# This driver initializes VTd engine based upon EDKII_VTD_INFO_PPI
# and provide DMA protection in PEI.
#
-# Copyright (c) 2017 - 2018, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR>
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
##
@@ -40,6 +40,9 @@
IoLib
CacheMaintenanceLib
+[Guids]
+ gSysMemInfoDataHobGuid ## CONSUMES
+
[Ppis]
gEdkiiIoMmuPpiGuid ## PRODUCES
gEdkiiVTdInfoPpiGuid ## CONSUMES
diff --git a/Silicon/Intel/IntelSiliconPkg/Include/Library/GetVtdPmrAlignmentLib.h b/Silicon/Intel/IntelSiliconPkg/Include/Library/GetVtdPmrAlignmentLib.h
new file mode 100644
index 0000000000..0b79887851
--- /dev/null
+++ b/Silicon/Intel/IntelSiliconPkg/Include/Library/GetVtdPmrAlignmentLib.h
@@ -0,0 +1,25 @@
+/** @file
+ Get Global VTd PMR alignment information library.
+
+ Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+
+#ifndef __GET_VTD_PMR_ALIGN_LIB_H__
+#define __GET_VTD_PMR_ALIGN_LIB_H__
+#include <Library/BaseLib.h>
+
+/**
+ Get Global VT-d Protected Memory alignment.
+
+
+ @return protected high memory alignment.
+**/
+
+UINTN
+GetGlobalVtdPmrAlignment (
+);
+
+#endif // __GET_VTD_PMR_ALIGN_LIB_H__
diff --git a/Silicon/Intel/IntelSiliconPkg/Include/SysMemInfoHob.h b/Silicon/Intel/IntelSiliconPkg/Include/SysMemInfoHob.h
new file mode 100644
index 0000000000..ce40b570c7
--- /dev/null
+++ b/Silicon/Intel/IntelSiliconPkg/Include/SysMemInfoHob.h
@@ -0,0 +1,21 @@
+/** @file
+ The definition for VTD System information Hob.
+
+ Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+
+#ifndef _SYS_MEM_INFO_HOB_H_
+#define _SYS_MEM_INFO_HOB_H_
+
+typedef struct {
+ UINTN ProtectedLowBase;
+ UINTN ProtectedLowLimit;
+ UINTN ProtectedHighBase;
+ UINTN ProtectedHighLimit;
+} SYSTEM_MEM_INFO_HOB;
+
+#endif // _SYS_MEM_INFO_HOB_H_
+
diff --git a/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec b/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec
index fe5bfa0dc6..c082a59596 100644
--- a/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec
+++ b/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec
@@ -3,7 +3,7 @@
#
# This package provides common open source Intel silicon modules.
#
-# Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.<BR>
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
##
@@ -18,10 +18,14 @@
Include
[LibraryClasses.IA32, LibraryClasses.X64]
- ## @libraryclass Provides services to access Microcode region on flash device.
+ ## @libraryclass Provides services to access Microcode region on flash device.
#
MicrocodeFlashAccessLib|Include/Library/MicrocodeFlashAccessLib.h
+ ## @libraryclass Provides services to access VTd PMR information
+ #
+ GetVtdPmrAlignmentLib|Include/Library/GetVtdPmrAlignmentLib.h
+
[Guids]
## GUID for Package token space
# {A9F8D54E-1107-4F0A-ADD0-4587E7A4A735}
@@ -35,6 +39,9 @@
## Include/Guid/MicrocodeFmp.h
gMicrocodeFmpImageTypeIdGuid = { 0x96d4fdcd, 0x1502, 0x424d, { 0x9d, 0x4c, 0x9b, 0x12, 0xd2, 0xdc, 0xae, 0x5c } }
+ ## HOB GUID to get memory information after MRC is done. The hob data will be used to set the PMR ranges
+ gSysMemInfoDataHobGuid = {0x6fb61645, 0xf168, 0x46be, { 0x80, 0xec, 0xb5, 0x02, 0x38, 0x5e, 0xe7, 0xe7 } }
+
[Ppis]
gEdkiiVTdInfoPpiGuid = { 0x8a59fcb3, 0xf191, 0x400c, { 0x97, 0x67, 0x67, 0xaf, 0x2b, 0x25, 0x68, 0x4a } }
diff --git a/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dsc b/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dsc
index 58b5b656ef..77fe760aa7 100644
--- a/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dsc
+++ b/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dsc
@@ -1,7 +1,7 @@
## @file
# This package provides common open source Intel silicon modules.
#
-# Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -34,6 +34,7 @@
SerialPortLib|MdePkg/Library/BaseSerialPortLibNull/BaseSerialPortLibNull.inf
CacheMaintenanceLib|MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf
MicrocodeFlashAccessLib|IntelSiliconPkg/Feature/Capsule/Library/MicrocodeFlashAccessLibNull/MicrocodeFlashAccessLibNull.inf
+ GetVtdPmrAlignmentLib|IntelSiliconPkg/Library/GetVtdPmrAlignmentLib/GetVtdPmrAlignmentLib.inf
[LibraryClasses.common.PEIM]
PeimEntryPoint|MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf
diff --git a/Silicon/Intel/IntelSiliconPkg/Library/GetVtdPmrAlignmentLib/GetVtdPmrAlignmentLib.inf b/Silicon/Intel/IntelSiliconPkg/Library/GetVtdPmrAlignmentLib/GetVtdPmrAlignmentLib.inf
new file mode 100644
index 0000000000..6a980e00c8
--- /dev/null
+++ b/Silicon/Intel/IntelSiliconPkg/Library/GetVtdPmrAlignmentLib/GetVtdPmrAlignmentLib.inf
@@ -0,0 +1,32 @@
+## @file
+# Component INF file for the GetVtdPmrAlignment library.
+#
+# Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+INF_VERSION = 0x00010017
+BASE_NAME = GetVtdPmrAlignmentLib
+FILE_GUID = 0332BE93-0547-4D87-A7FA-0D9D76C53187
+MODULE_TYPE = BASE
+LIBRARY_CLASS = GetVtdPmrAlignmentLib
+
+[Packages]
+MdePkg/MdePkg.dec
+IntelSiliconPkg/IntelSiliconPkg.dec
+
+[Sources]
+GetVtdPmrAlignmentLib.c
+
+[LibraryClasses]
+DebugLib
+BaseMemoryLib
+MemoryAllocationLib
+BaseLib
+PeiServicesLib
+
+[Ppis]
+gEdkiiVTdInfoPpiGuid ## CONSUMES
--
2.16.2.windows.1
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Thanks Evelyn
Comments below:
1) The EFIAPI is missing in library API. Please follow EDKII coding standard.
==============
UINTN
GetGlobalVtdPmrAlignment (
);
==============
Should be:
==============
UINTN
EFIAPI
GetGlobalVtdPmrAlignment (
VOID
);
==============
2) Because you added a new library dependency, please make sure you did not break any other platform. For example, the one in KabylakeOpenBoardPkg, which will consume VTd drivers.
3) Please replace below BIT0 with meaningful MACRO, in MdePkg\Include\IndustryStandard\DmaRemappingReportingTable.h
if ((DrhdHeader->Flags & BIT0) == BIT0) {
4) GetVtdPmrAlignmentLib seems only work in PEI phase. Please rename it to be PeiGetVtdPmrAlignmentLib.
5) In IntelVTdPmrPei.c the indent should be 2 spaces.
===============
if (SysMemHobPtr == NULL) {
//
// Calcuate the PMR memory alignment
//
===============
Should be
===============
if (SysMemHobPtr == NULL) {
//
// Calcuate the PMR memory alignment
//
===============
6) I think we should follow VTd spec to defined width of below register.
==================
typedef struct {
UINTN ProtectedLowBase;
UINTN ProtectedLowLimit;
UINTN ProtectedHighBase;
UINTN ProtectedHighLimit;
} SYSTEM_MEM_INFO_HOB;
==================
Should be:
==================
typedef struct {
UINT32 ProtectedLowBase;
UINT32 ProtectedLowLimit;
UINT64 ProtectedHighBase;
UINT64 ProtectedHighLimit;
} SYSTEM_MEM_INFO_HOB;
==================
Using UINTN in PEI means you cannot set above 4G memory for PHMR in 32bit PEI.
7) I think we need use ProtectedHighBase instead of hardcode below:
HighBottom = (UINT64) BASE_4GB;
If you always hardcode BASE_4GB, the ProtectedHighBase in hob is useless.
8) Please use LShiftU64 for 64bit operation.
HighTop = (UINT64) SysMemHob->ProtectedHighLimit << 20;
Using direct shift might cause link failure in non-optimization mode.
Thank you
Yao Jiewen
> -----Original Message-----
> From: devel@edk2.groups.io [mailto:devel@edk2.groups.io] On Behalf Of
> Evelyn Wang
> Sent: Friday, August 9, 2019 5:52 AM
> To: devel@edk2.groups.io
> Cc: Huang, Jenny <jenny.huang@intel.com>; Shih, More
> <more.shih@intel.com>; Ni, Ray <ray.ni@intel.com>; Chaganty, Rangasai V
> <rangasai.v.chaganty@intel.com>
> Subject: [edk2-devel] [PATCH] IntelSiliconPkg-Vtd: A new PMR interface
>
> REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1770
>
> 1) IOMMU PMR feature should be generic to support different hardware
> architecture. Platforms may request no overlap between PMR regions
> and system reserve memory. Create an interface to control PLMR/PHMR
> regions. It allows silicon code to adjust PLMR/PHMR region base on
> the project needs.
>
> 2) DisableDMAr Function Code Optimization
> Optimize the flow to follow the VT-d spec requirements.
>
> 3) Renamed InitDmar() to InitGlobalVtd()
> The oringal function name is misleading
>
> 4) A new GetVtdPmrAlignmentLib for silicon code to get
> PMR alignment values.
>
> Signed-off-by: Evelyn Wang <iwen.evelyn.wang@intel.com>
> Cc: Jenny Huang <jenny.huang@intel.com>
> Cc: More Shih <more.shih@intel.com>
> Cc: Ray Ni <ray.ni@intel.com>
> Cc: Rangasai V Chaganty <rangasai.v.chaganty@intel.com>
> ---
> Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/VtdReg.c
> | 30 +++++++++++++++++++++++++++---
> Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmrPei.c
> | 73
> ++++++++++++++++++++++++++++++++++++++++++++++++++------------------
> -----
> Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/VtdReg.c
> | 29 ++++++++++++++++++++++++++---
>
> Silicon/Intel/IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSamplePei/Platfor
> mVTdInfoSamplePei.c | 9 +++++----
>
> Silicon/Intel/IntelSiliconPkg/Library/GetVtdPmrAlignmentLib/GetVtdPmrAlig
> nmentLib.c | 164
> ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> ++++++++++++++++++++++++++++++++++++++++
>
> Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmrPei.inf
> | 5 ++++-
> Silicon/Intel/IntelSiliconPkg/Include/Library/GetVtdPmrAlignmentLib.h
> | 25 +++++++++++++++++++++++++
> Silicon/Intel/IntelSiliconPkg/Include/SysMemInfoHob.h
> | 21 +++++++++++++++++++++
> Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec
> | 11 +++++++++--
> Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dsc
> | 3 ++-
>
> Silicon/Intel/IntelSiliconPkg/Library/GetVtdPmrAlignmentLib/GetVtdPmrAlig
> nmentLib.inf | 32 ++++++++++++++++++++++++++++++++
> 11 files changed, 365 insertions(+), 37 deletions(-)
>
> diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/VtdReg.c
> b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/VtdReg.c
> index 22bf821d2b..699639ba88 100644
> --- a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/VtdReg.c
> +++ b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/VtdReg.c
> @@ -1,6 +1,6 @@
> /** @file
>
> - Copyright (c) 2017 - 2018, Intel Corporation. All rights reserved.<BR>
> + Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR>
> SPDX-License-Identifier: BSD-2-Clause-Patent
>
> **/
> @@ -309,6 +309,8 @@ DisableDmar (
> UINTN Index;
> UINTN SubIndex;
> UINT32 Reg32;
> + UINT32 Status;
> + UINT32 Command;
>
> for (Index = 0; Index < mVtdUnitNumber; Index++) {
> DEBUG((DEBUG_INFO, ">>>>>>DisableDmar() for engine [%d] \n",
> Index));
> @@ -319,9 +321,31 @@ DisableDmar (
> FlushWriteBuffer (Index);
>
> //
> - // Disable VTd
> + // Disable Dmar
> //
> - MmioWrite32 (mVtdUnitInformation[Index].VtdUnitBaseAddress +
> R_GCMD_REG, B_GMCD_REG_SRTP);
> + //
> + // Set TE (Translation Enable: BIT31) of Global command register to
> zero
> + //
> + Reg32 = MmioRead32
> (mVtdUnitInformation[Index].VtdUnitBaseAddress + R_GSTS_REG);
> + Status = (Reg32 & 0x96FFFFFF); // Reset the one-shot bits
> + Command = (Status & ~B_GMCD_REG_TE);
> + MmioWrite32 (mVtdUnitInformation[Index].VtdUnitBaseAddress +
> R_GCMD_REG, Command);
> +
> + //
> + // Poll on TE Status bit of Global status register to become zero
> + //
> + do {
> + Reg32 = MmioRead32
> (mVtdUnitInformation[Index].VtdUnitBaseAddress + R_GSTS_REG);
> + } while ((Reg32 & B_GSTS_REG_TE) == B_GSTS_REG_TE);
> +
> + //
> + // Set SRTP (Set Root Table Pointer: BIT30) of Global command
> register in order to update the root table pointerDisable VTd
> + //
> + Reg32 = MmioRead32
> (mVtdUnitInformation[Index].VtdUnitBaseAddress + R_GSTS_REG);
> + Status = (Reg32 & 0x96FFFFFF); // Reset the one-shot bits
> + Command = (Status | B_GMCD_REG_SRTP);
> + MmioWrite32 (mVtdUnitInformation[Index].VtdUnitBaseAddress +
> R_GCMD_REG, Command);
> +
> do {
> Reg32 = MmioRead32
> (mVtdUnitInformation[Index].VtdUnitBaseAddress + R_GSTS_REG);
> } while((Reg32 & B_GSTS_REG_RTPS) == 0);
> diff --git
> a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmrPei.
> c
> b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmrPei.
> c
> index ca099ed71d..14da18289e 100644
> ---
> a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmrPei.
> c
> +++
> b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmrPei.
> c
> @@ -1,6 +1,6 @@
> /** @file
>
> - Copyright (c) 2017 - 2018, Intel Corporation. All rights reserved.<BR>
> + Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR>
>
> SPDX-License-Identifier: BSD-2-Clause-Patent
>
> @@ -20,7 +20,7 @@
> #include <Ppi/VtdInfo.h>
> #include <Ppi/MemoryDiscovered.h>
> #include <Ppi/EndOfPeiPhase.h>
> -
> +#include <SysMemInfoHob.h>
> #include "IntelVTdPmrPei.h"
>
> EFI_GUID mVTdInfoGuid = {
> @@ -424,38 +424,69 @@ InitDmaProtection (
> UINTN MemoryAlignment;
> UINTN LowBottom;
> UINTN LowTop;
> - UINTN HighBottom;
> + UINT64 HighBottom;
> UINT64 HighTop;
> DMA_BUFFER_INFO *DmaBufferInfo;
> VOID *Hob;
> EFI_PEI_PPI_DESCRIPTOR *OldDescriptor;
> EDKII_IOMMU_PPI *OldIoMmuPpi;
> + SYSTEM_MEM_INFO_HOB *SysMemHob;
> + VOID *SysMemHobPtr;
> +
> + SysMemHob = NULL;
> +
>
> Hob = GetFirstGuidHob (&mDmaBufferInfoGuid);
> DmaBufferInfo = GET_GUID_HOB_DATA(Hob);
>
> - DEBUG ((DEBUG_INFO, " DmaBufferSize : 0x%x\n",
> DmaBufferInfo->DmaBufferSize));
> + SysMemHobPtr = GetFirstGuidHob (&gSysMemInfoDataHobGuid);
> +
> + if (SysMemHobPtr == NULL) {
> + //
> + // Calcuate the PMR memory alignment
> + //
> + LowMemoryAlignment = GetLowMemoryAlignment (VTdInfo,
> VTdInfo->EngineMask);
> + HighMemoryAlignment = GetHighMemoryAlignment (VTdInfo,
> VTdInfo->EngineMask);
> + if (LowMemoryAlignment < HighMemoryAlignment) {
> + MemoryAlignment = (UINTN)HighMemoryAlignment;
> + } else {
> + MemoryAlignment = LowMemoryAlignment;
> + }
> + ASSERT (DmaBufferInfo->DmaBufferSize ==
> ALIGN_VALUE(DmaBufferInfo->DmaBufferSize, MemoryAlignment));
> +
> + //
> + // Allocate memory for DMA buffer
> + //
> + DmaBufferInfo->DmaBufferBase = (UINTN)AllocateAlignedPages
> (EFI_SIZE_TO_PAGES(DmaBufferInfo->DmaBufferSize), MemoryAlignment);
> + ASSERT (DmaBufferInfo->DmaBufferBase != 0);
> + if (DmaBufferInfo->DmaBufferBase == 0) {
> + DEBUG ((DEBUG_INFO, " InitDmaProtection :
> OutOfResource\n"));
> + return EFI_OUT_OF_RESOURCES;
> + }
> +
> + DmaBufferInfo->DmaBufferCurrentTop =
> DmaBufferInfo->DmaBufferBase + DmaBufferInfo->DmaBufferSize;
> + DmaBufferInfo->DmaBufferCurrentBottom =
> DmaBufferInfo->DmaBufferBase;
> + LowBottom = 0;
> + LowTop = DmaBufferInfo->DmaBufferBase;
> + HighBottom = DmaBufferInfo->DmaBufferBase +
> DmaBufferInfo->DmaBufferSize;
> + HighTop = LShiftU64 (1, VTdInfo->HostAddressWidth + 1);
>
> - LowMemoryAlignment = GetLowMemoryAlignment (VTdInfo,
> VTdInfo->EngineMask);
> - HighMemoryAlignment = GetHighMemoryAlignment (VTdInfo,
> VTdInfo->EngineMask);
> - if (LowMemoryAlignment < HighMemoryAlignment) {
> - MemoryAlignment = (UINTN)HighMemoryAlignment;
> } else {
> - MemoryAlignment = LowMemoryAlignment;
> - }
> - ASSERT (DmaBufferInfo->DmaBufferSize ==
> ALIGN_VALUE(DmaBufferInfo->DmaBufferSize, MemoryAlignment));
> - DmaBufferInfo->DmaBufferBase = (UINTN)AllocateAlignedPages
> (EFI_SIZE_TO_PAGES(DmaBufferInfo->DmaBufferSize), MemoryAlignment);
> - ASSERT (DmaBufferInfo->DmaBufferBase != 0);
> - if (DmaBufferInfo->DmaBufferBase == 0) {
> - DEBUG ((DEBUG_INFO, " InitDmaProtection : OutOfResource\n"));
> - return EFI_OUT_OF_RESOURCES;
> +
> + //
> + // Get the PMR ranges information for the system hob
> + //
> + SysMemHob = GET_GUID_HOB_DATA (SysMemHobPtr);
> + DmaBufferInfo->DmaBufferBase = SysMemHob->ProtectedLowLimit
> << 20;
> + LowBottom = SysMemHob->ProtectedLowBase;
> + LowTop = SysMemHob->ProtectedLowLimit << 20;
> + HighBottom = (UINT64) BASE_4GB;
> + HighTop = (UINT64) SysMemHob->ProtectedHighLimit << 20;
> }
>
> + DEBUG ((DEBUG_INFO, " DmaBufferSize : 0x%x\n",
> DmaBufferInfo->DmaBufferSize));
> DEBUG ((DEBUG_INFO, " DmaBufferBase : 0x%x\n",
> DmaBufferInfo->DmaBufferBase));
>
> - DmaBufferInfo->DmaBufferCurrentTop =
> DmaBufferInfo->DmaBufferBase + DmaBufferInfo->DmaBufferSize;
> - DmaBufferInfo->DmaBufferCurrentBottom =
> DmaBufferInfo->DmaBufferBase;
> -
> //
> // (Re)Install PPI.
> //
> @@ -472,10 +503,6 @@ InitDmaProtection (
> }
> ASSERT_EFI_ERROR (Status);
>
> - LowBottom = 0;
> - LowTop = DmaBufferInfo->DmaBufferBase;
> - HighBottom = DmaBufferInfo->DmaBufferBase +
> DmaBufferInfo->DmaBufferSize;
> - HighTop = LShiftU64 (1, VTdInfo->HostAddressWidth + 1);
>
> Status = SetDmaProtectedRange (
> VTdInfo,
> diff --git
> a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/VtdReg.c
> b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/VtdReg.c
> index 4774a2ae5b..c9669426aa 100644
> --- a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/VtdReg.c
> +++ b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/VtdReg.c
> @@ -1,6 +1,6 @@
> /** @file
>
> - Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
> + Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR>
>
> SPDX-License-Identifier: BSD-2-Clause-Patent
>
> @@ -197,6 +197,8 @@ DisableDmar (
> )
> {
> UINT32 Reg32;
> + UINT32 Status;
> + UINT32 Command;
>
> DEBUG((DEBUG_INFO, ">>>>>>DisableDmar() for engine [%x] \n",
> VtdUnitBaseAddress));
>
> @@ -206,9 +208,30 @@ DisableDmar (
> FlushWriteBuffer (VtdUnitBaseAddress);
>
> //
> - // Disable VTd
> + // Disable Dmar
> //
> - MmioWrite32 (VtdUnitBaseAddress + R_GCMD_REG,
> B_GMCD_REG_SRTP);
> + //
> + // Set TE (Translation Enable: BIT31) of Global command register to zero
> + //
> + Reg32 = MmioRead32 (VtdUnitBaseAddress + R_GSTS_REG);
> + Status = (Reg32 & 0x96FFFFFF); // Reset the one-shot bits
> + Command = (Status & ~B_GMCD_REG_TE);
> + MmioWrite32 (VtdUnitBaseAddress + R_GCMD_REG, Command);
> +
> + //
> + // Poll on TE Status bit of Global status register to become zero
> + //
> + do {
> + Reg32 = MmioRead32 (VtdUnitBaseAddress + R_GSTS_REG);
> + } while ((Reg32 & B_GSTS_REG_TE) == B_GSTS_REG_TE);
> +
> + //
> + // Set SRTP (Set Root Table Pointer: BIT30) of Global command register
> in order to update the root table pointerDisable VTd
> + //
> + Reg32 = MmioRead32 (VtdUnitBaseAddress + R_GSTS_REG);
> + Status = (Reg32 & 0x96FFFFFF); // Reset the one-shot bits
> + Command = (Status | B_GMCD_REG_SRTP);
> + MmioWrite32 (VtdUnitBaseAddress + R_GCMD_REG, Command);
> do {
> Reg32 = MmioRead32 (VtdUnitBaseAddress + R_GSTS_REG);
> } while((Reg32 & B_GSTS_REG_RTPS) == 0);
> diff --git
> a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSamplePei/Platf
> ormVTdInfoSamplePei.c
> b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSamplePei/Platf
> ormVTdInfoSamplePei.c
> index 3698c3d3f1..6f6c14f7a9 100644
> ---
> a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSamplePei/Platf
> ormVTdInfoSamplePei.c
> +++
> b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSamplePei/Platf
> ormVTdInfoSamplePei.c
> @@ -1,7 +1,7 @@
> /** @file
> Platform VTd Info Sample PEI driver.
>
> - Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
> + Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR>
> SPDX-License-Identifier: BSD-2-Clause-Patent
>
> **/
> @@ -166,15 +166,16 @@ EFI_PEI_PPI_DESCRIPTOR
> mPlatformVTdNoIgdInfoSampleDesc = {
>
> /**
> Initialize VTd register.
> + Initialize the VTd hardware unit which has INCLUDE_PCI_ALL set
> **/
> VOID
> -InitDmar (
> +InitGlobalVtd (
> VOID
> )
> {
> UINT32 MchBar;
>
> - DEBUG ((DEBUG_INFO, "InitDmar\n"));
> + DEBUG ((DEBUG_INFO, "InitGlobalVtd\n"));
>
> MchBar = PciRead32 (PCI_LIB_ADDRESS(0, 0, 0, R_SA_MCHBAR)) &
> ~BIT0;
> PciWrite32 (PCI_LIB_ADDRESS(0, 0, 0, R_SA_MCHBAR), 0xFED10000 |
> BIT0);
> @@ -346,7 +347,7 @@ PlatformVTdInfoSampleInitialize (
> DEBUG ((DEBUG_INFO, "SiliconInitialized - %x\n", SiliconInitialized));
> if (!SiliconInitialized) {
> Status = PeiServicesNotifyPpi (&mSiliconInitializedNotifyList);
> - InitDmar ();
> + InitGlobalVtd ();
>
> Status = PeiServicesInstallPpi (&mPlatformVTdNoIgdInfoSampleDesc);
> ASSERT_EFI_ERROR (Status);
> diff --git
> a/Silicon/Intel/IntelSiliconPkg/Library/GetVtdPmrAlignmentLib/GetVtdPmrAli
> gnmentLib.c
> b/Silicon/Intel/IntelSiliconPkg/Library/GetVtdPmrAlignmentLib/GetVtdPmrAli
> gnmentLib.c
> new file mode 100644
> index 0000000000..10fbd1d80a
> --- /dev/null
> +++
> b/Silicon/Intel/IntelSiliconPkg/Library/GetVtdPmrAlignmentLib/GetVtdPmrAli
> gnmentLib.c
> @@ -0,0 +1,164 @@
> +/** @file
> + Library to get Global VTd PMR alignment information.
> + Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +**/
> +#include <PiPei.h>
> +#include <Library/BaseLib.h>
> +#include <Library/BaseMemoryLib.h>
> +#include <Library/IoLib.h>
> +#include <Library/DebugLib.h>
> +#include <Library/GetVtdPmrAlignmentLib.h>
> +#include <Library/PeiServicesLib.h>
> +#include <IndustryStandard/DmaRemappingReportingTable.h>
> +#include <IndustryStandard/VTd.h>
> +
> +typedef union {
> + struct {
> + UINT32 Low;
> + UINT32 High;
> + } Data32;
> + UINT64 Data;
> +} UINT64_STRUCT;
> +
> +/**
> + Get protected low memory alignment.
> +
> + @param HostAddressWidth The host address width.
> + @param VtdUnitBaseAddress The base address of the VTd engine.
> +
> + @return protected low memory alignment.
> +**/
> +UINT32
> +GetGlobalVTdPlmrAlignment (
> + IN UINT8 HostAddressWidth,
> + IN UINTN VtdUnitBaseAddress
> + )
> +{
> + UINT32 Data32;
> +
> + MmioWrite32 (VtdUnitBaseAddress + R_PMEN_LOW_BASE_REG,
> 0xFFFFFFFF);
> + Data32 = MmioRead32 (VtdUnitBaseAddress +
> R_PMEN_LOW_BASE_REG);
> + Data32 = ~Data32 + 1;
> +
> + return Data32;
> +}
> +
> +/**
> + Get protected high memory alignment.
> +
> + @param HostAddressWidth The host address width.
> + @param VtdUnitBaseAddress The base address of the VTd engine.
> +
> + @return protected high memory alignment.
> +**/
> +UINT64_STRUCT
> +GetGlobalVTdPhmrAlignment (
> + IN UINT8 HostAddressWidth,
> + IN UINTN VtdUnitBaseAddress
> + )
> +{
> + UINT64_STRUCT Data64;
> +
> + MmioWrite64 (VtdUnitBaseAddress + R_PMEN_HIGH_BASE_REG,
> 0xFFFFFFFFFFFFFFFF);
> + Data64.Data = MmioRead64 (VtdUnitBaseAddress +
> R_PMEN_HIGH_BASE_REG);
> + Data64.Data = ~Data64.Data + 1;
> + Data64.Data = Data64.Data & (LShiftU64 (1, HostAddressWidth) - 1);
> +
> + return Data64;
> +}
> +
> +/**
> + Get Global VT-d Protected Memory Aignment.
> +
> + @return protected high memory alignment.
> +**/
> +UINTN
> +GetGlobalVtdPmrAlignment (
> +)
> +{
> + UINT32 LowMemoryAlignment;
> + UINT64_STRUCT HighMemoryAlignment;
> + UINTN MemoryAlignment;
> + UINT32 GlobalVTdBaseAddress;
> + EFI_STATUS Status;
> + UINTN VtdIndex;
> + EFI_ACPI_DMAR_STRUCTURE_HEADER *DmarHeader;
> + EFI_ACPI_DMAR_DRHD_HEADER *DrhdHeader;
> + EFI_ACPI_DMAR_HEADER *AcpiDmarTable;
> +
> + //
> + // Initialization
> + //
> + GlobalVTdBaseAddress = 0xFFFFFFFF;
> + LowMemoryAlignment = 0;
> + HighMemoryAlignment.Data = 0;
> + MemoryAlignment = 0;
> + Status = EFI_UNSUPPORTED;
> + VtdIndex = 0;
> + DmarHeader = NULL;
> + DrhdHeader = NULL;
> + AcpiDmarTable = NULL;
> +
> + //
> + // Fatch the PEI DMAR ACPU Table that created and installed in
> PlatformVTdInfoSamplePei.c
> + //
> + Status = PeiServicesLocatePpi (
> + &gEdkiiVTdInfoPpiGuid,
> + 0,
> + NULL,
> + (VOID **)&AcpiDmarTable
> + );
> + if (EFI_ERROR (Status)) {
> +
> + DEBUG ((DEBUG_ERROR, "PeiServicesLocatePpi gEdkiiVTdInfoPpiGuid
> failed. Status: %r\n", Status));
> + MemoryAlignment = SIZE_1MB;
> + return MemoryAlignment;
> +
> + } else {
> +
> + //
> + // Seatch the DRHD structure with INCLUDE_PCI_ALL flag Set -> Global
> VT-d
> + //
> + DmarHeader = (EFI_ACPI_DMAR_STRUCTURE_HEADER
> *)((UINTN)(AcpiDmarTable + 1));
> + while ((UINTN)DmarHeader < (UINTN)AcpiDmarTable +
> AcpiDmarTable->Header.Length) {
> + switch (DmarHeader->Type) {
> + case EFI_ACPI_DMAR_TYPE_DRHD:
> + DrhdHeader = (EFI_ACPI_DMAR_DRHD_HEADER *) DmarHeader;
> + if ((DrhdHeader->Flags & BIT0) == BIT0) {
> + GlobalVTdBaseAddress =
> (UINT32)DrhdHeader->RegisterBaseAddress;
> + DEBUG ((DEBUG_INFO," GlobalVTdBaseAddress: %x\n",
> GlobalVTdBaseAddress));
> + }
> + VtdIndex++;
> +
> + break;
> +
> + default:
> + break;
> + }
> + DmarHeader = (EFI_ACPI_DMAR_STRUCTURE_HEADER
> *)((UINTN)DmarHeader + DmarHeader->Length);
> + }
> +
> + if (GlobalVTdBaseAddress == 0xFFFFFFFF) {
> +
> + DEBUG ((DEBUG_ERROR, "Error! Please set INCLUDE_PCI_ALL flag
> to the Global VT-d\n"));
> + MemoryAlignment = SIZE_1MB;
> +
> + } else {
> + //
> + // Get the alignment information from VT-d register
> + //
> + LowMemoryAlignment = GetGlobalVTdPlmrAlignment
> (AcpiDmarTable->HostAddressWidth, GlobalVTdBaseAddress);
> + HighMemoryAlignment = GetGlobalVTdPhmrAlignment
> (AcpiDmarTable->HostAddressWidth, GlobalVTdBaseAddress);
> + if (LowMemoryAlignment < HighMemoryAlignment.Data) {
> + MemoryAlignment = (UINTN)HighMemoryAlignment.Data;
> + } else {
> + MemoryAlignment = LowMemoryAlignment;
> + }
> + }
> + }
> +
> + return MemoryAlignment;
> +}
> diff --git
> a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmrPei.i
> nf
> b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmrPei.i
> nf
> index 39b914cd00..2f6599d818 100644
> ---
> a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmrPei.i
> nf
> +++
> b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmrPei.i
> nf
> @@ -4,7 +4,7 @@
> # This driver initializes VTd engine based upon EDKII_VTD_INFO_PPI
> # and provide DMA protection in PEI.
> #
> -# Copyright (c) 2017 - 2018, Intel Corporation. All rights reserved.<BR>
> +# Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR>
> # SPDX-License-Identifier: BSD-2-Clause-Patent
> #
> ##
> @@ -40,6 +40,9 @@
> IoLib
> CacheMaintenanceLib
>
> +[Guids]
> + gSysMemInfoDataHobGuid ## CONSUMES
> +
> [Ppis]
> gEdkiiIoMmuPpiGuid ## PRODUCES
> gEdkiiVTdInfoPpiGuid ## CONSUMES
> diff --git
> a/Silicon/Intel/IntelSiliconPkg/Include/Library/GetVtdPmrAlignmentLib.h
> b/Silicon/Intel/IntelSiliconPkg/Include/Library/GetVtdPmrAlignmentLib.h
> new file mode 100644
> index 0000000000..0b79887851
> --- /dev/null
> +++ b/Silicon/Intel/IntelSiliconPkg/Include/Library/GetVtdPmrAlignmentLib.h
> @@ -0,0 +1,25 @@
> +/** @file
> + Get Global VTd PMR alignment information library.
> +
> + Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +**/
> +
> +
> +#ifndef __GET_VTD_PMR_ALIGN_LIB_H__
> +#define __GET_VTD_PMR_ALIGN_LIB_H__
> +#include <Library/BaseLib.h>
> +
> +/**
> + Get Global VT-d Protected Memory alignment.
> +
> +
> + @return protected high memory alignment.
> +**/
> +
> +UINTN
> +GetGlobalVtdPmrAlignment (
> +);
> +
> +#endif // __GET_VTD_PMR_ALIGN_LIB_H__
> diff --git a/Silicon/Intel/IntelSiliconPkg/Include/SysMemInfoHob.h
> b/Silicon/Intel/IntelSiliconPkg/Include/SysMemInfoHob.h
> new file mode 100644
> index 0000000000..ce40b570c7
> --- /dev/null
> +++ b/Silicon/Intel/IntelSiliconPkg/Include/SysMemInfoHob.h
> @@ -0,0 +1,21 @@
> +/** @file
> + The definition for VTD System information Hob.
> +
> + Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +**/
> +
> +
> +#ifndef _SYS_MEM_INFO_HOB_H_
> +#define _SYS_MEM_INFO_HOB_H_
> +
> +typedef struct {
> + UINTN ProtectedLowBase;
> + UINTN ProtectedLowLimit;
> + UINTN ProtectedHighBase;
> + UINTN ProtectedHighLimit;
> +} SYSTEM_MEM_INFO_HOB;
> +
> +#endif // _SYS_MEM_INFO_HOB_H_
> +
> diff --git a/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec
> b/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec
> index fe5bfa0dc6..c082a59596 100644
> --- a/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec
> +++ b/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec
> @@ -3,7 +3,7 @@
> #
> # This package provides common open source Intel silicon modules.
> #
> -# Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>
> +# Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.<BR>
> # SPDX-License-Identifier: BSD-2-Clause-Patent
> #
> ##
> @@ -18,10 +18,14 @@
> Include
>
> [LibraryClasses.IA32, LibraryClasses.X64]
> - ## @libraryclass Provides services to access Microcode region on flash
> device.
> + ## @libraryclass Provides services to access Microcode region on flash
> device.
> #
> MicrocodeFlashAccessLib|Include/Library/MicrocodeFlashAccessLib.h
>
> + ## @libraryclass Provides services to access VTd PMR information
> + #
> + GetVtdPmrAlignmentLib|Include/Library/GetVtdPmrAlignmentLib.h
> +
> [Guids]
> ## GUID for Package token space
> # {A9F8D54E-1107-4F0A-ADD0-4587E7A4A735}
> @@ -35,6 +39,9 @@
> ## Include/Guid/MicrocodeFmp.h
> gMicrocodeFmpImageTypeIdGuid = { 0x96d4fdcd, 0x1502, 0x424d,
> { 0x9d, 0x4c, 0x9b, 0x12, 0xd2, 0xdc, 0xae, 0x5c } }
>
> + ## HOB GUID to get memory information after MRC is done. The hob
> data will be used to set the PMR ranges
> + gSysMemInfoDataHobGuid = {0x6fb61645, 0xf168, 0x46be, { 0x80, 0xec,
> 0xb5, 0x02, 0x38, 0x5e, 0xe7, 0xe7 } }
> +
> [Ppis]
> gEdkiiVTdInfoPpiGuid = { 0x8a59fcb3, 0xf191, 0x400c, { 0x97, 0x67, 0x67,
> 0xaf, 0x2b, 0x25, 0x68, 0x4a } }
>
> diff --git a/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dsc
> b/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dsc
> index 58b5b656ef..77fe760aa7 100644
> --- a/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dsc
> +++ b/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dsc
> @@ -1,7 +1,7 @@
> ## @file
> # This package provides common open source Intel silicon modules.
> #
> -# Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
> +# Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR>
> #
> # SPDX-License-Identifier: BSD-2-Clause-Patent
> #
> @@ -34,6 +34,7 @@
>
> SerialPortLib|MdePkg/Library/BaseSerialPortLibNull/BaseSerialPortLibNull.in
> f
>
> CacheMaintenanceLib|MdePkg/Library/BaseCacheMaintenanceLib/BaseCac
> heMaintenanceLib.inf
>
> MicrocodeFlashAccessLib|IntelSiliconPkg/Feature/Capsule/Library/Microcod
> eFlashAccessLibNull/MicrocodeFlashAccessLibNull.inf
> +
> GetVtdPmrAlignmentLib|IntelSiliconPkg/Library/GetVtdPmrAlignmentLib/Get
> VtdPmrAlignmentLib.inf
>
> [LibraryClasses.common.PEIM]
> PeimEntryPoint|MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf
> diff --git
> a/Silicon/Intel/IntelSiliconPkg/Library/GetVtdPmrAlignmentLib/GetVtdPmrAli
> gnmentLib.inf
> b/Silicon/Intel/IntelSiliconPkg/Library/GetVtdPmrAlignmentLib/GetVtdPmrAli
> gnmentLib.inf
> new file mode 100644
> index 0000000000..6a980e00c8
> --- /dev/null
> +++
> b/Silicon/Intel/IntelSiliconPkg/Library/GetVtdPmrAlignmentLib/GetVtdPmrAli
> gnmentLib.inf
> @@ -0,0 +1,32 @@
> +## @file
> +# Component INF file for the GetVtdPmrAlignment library.
> +#
> +# Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
> +#
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +##
> +
> +[Defines]
> +INF_VERSION = 0x00010017
> +BASE_NAME = GetVtdPmrAlignmentLib
> +FILE_GUID = 0332BE93-0547-4D87-A7FA-0D9D76C53187
> +MODULE_TYPE = BASE
> +LIBRARY_CLASS = GetVtdPmrAlignmentLib
> +
> +[Packages]
> +MdePkg/MdePkg.dec
> +IntelSiliconPkg/IntelSiliconPkg.dec
> +
> +[Sources]
> +GetVtdPmrAlignmentLib.c
> +
> +[LibraryClasses]
> +DebugLib
> +BaseMemoryLib
> +MemoryAllocationLib
> +BaseLib
> +PeiServicesLib
> +
> +[Ppis]
> +gEdkiiVTdInfoPpiGuid ## CONSUMES
> --
> 2.16.2.windows.1
>
>
>
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