[edk2] [PATCH edk2-platforms v2 3/6] Hisilicon/D0x: Fix SetAtuConfig1RW bug

Ming Huang posted 6 patches 7 years, 5 months ago
There is a newer version of this series
[edk2] [PATCH edk2-platforms v2 3/6] Hisilicon/D0x: Fix SetAtuConfig1RW bug
Posted by Ming Huang 7 years, 5 months ago
The MemLimit is wrong when the Private->BusLimit equal 0xFF.
This patch fix enumerating device plug in switch cart failed issue.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ming Huang <ming.huang@linaro.org>
Signed-off-by: Heyi Guo <heyi.guo@linaro.org>
---
 Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c b/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c
index e5f66eaa4a..3f894e8eec 100644
--- a/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c
+++ b/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c
@@ -666,7 +666,7 @@ void SetAtuConfig1RW (
     )
 {
     UINTN RbPciBase = Private->RbPciBar;
-    UINT64 MemLimit = GetPcieCfgAddress (Private->Ecam, Private->BusLimit + 1, 0, 0, 0) - 1;
+    UINT64 MemLimit = GetPcieCfgAddress (Private->Ecam, Private->BusLimit, 0x1F, 0x07, 0xFFF);
     UINT64 Cfg1Base = GetPcieCfgAddress (Private->Ecam, Private->BusBase + 2, 0, 0, 0);
 
     MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_VIEW_POINT, Index);
-- 
2.17.0

_______________________________________________
edk2-devel mailing list
edk2-devel@lists.01.org
https://lists.01.org/mailman/listinfo/edk2-devel