.../AuroraGlacier/BoardInitDxe/BoardInitDxe.c | 114 ++++++++++++++++++++ .../AuroraGlacier/BoardInitDxe/BoardInitDxe.inf | 1 + .../BensonGlacier/BoardInitDxe/BoardInitDxe.c | 115 ++++++++++++++++++++- .../BensonGlacier/BoardInitDxe/BoardInitDxe.inf | 1 + .../PlatformSettings/PlatformDxe/PlatformDxe.inf | 2 +- Platform/BroxtonPlatformPkg/PlatformPkg.fdf | 5 + Silicon/BroxtonSoC/BroxtonSiPkg/SiPkgDxe.dsc | 15 ++- Silicon/BroxtonSoC/BroxtonSiPkg/SiPkgDxeLib.dsc | 6 +- .../BroxtonSiPkg/SouthCluster/Smbus/Dxe/PchSmbus.h | 2 +- .../SouthCluster/Smbus/Dxe/PchSmbusEntry.c | 2 + 10 files changed, 258 insertions(+), 5 deletions(-)
Change Bit 2 (SUSPWRDNACKCFG) of Power Sequence Configuration register (offset 0x2A) to 1.
If SUSPWRDNACKCFG is 0, SUSPWRDNACK signal is ignored. PMIC will not go to G3 when SUSPWRDNACK goes high in S4 state.
If SUSPWRDNACKCFG is 1, PMIC responses to SUSPWRDNACK signal.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: zwei4 <david.wei@intel.com>
---
.../AuroraGlacier/BoardInitDxe/BoardInitDxe.c | 114 ++++++++++++++++++++
.../AuroraGlacier/BoardInitDxe/BoardInitDxe.inf | 1 +
.../BensonGlacier/BoardInitDxe/BoardInitDxe.c | 115 ++++++++++++++++++++-
.../BensonGlacier/BoardInitDxe/BoardInitDxe.inf | 1 +
.../PlatformSettings/PlatformDxe/PlatformDxe.inf | 2 +-
Platform/BroxtonPlatformPkg/PlatformPkg.fdf | 5 +
Silicon/BroxtonSoC/BroxtonSiPkg/SiPkgDxe.dsc | 15 ++-
Silicon/BroxtonSoC/BroxtonSiPkg/SiPkgDxeLib.dsc | 6 +-
.../BroxtonSiPkg/SouthCluster/Smbus/Dxe/PchSmbus.h | 2 +-
.../SouthCluster/Smbus/Dxe/PchSmbusEntry.c | 2 +
10 files changed, 258 insertions(+), 5 deletions(-)
diff --git a/Platform/BroxtonPlatformPkg/Board/AuroraGlacier/BoardInitDxe/BoardInitDxe.c b/Platform/BroxtonPlatformPkg/Board/AuroraGlacier/BoardInitDxe/BoardInitDxe.c
index e948594c8..f06a540eb 100644
--- a/Platform/BroxtonPlatformPkg/Board/AuroraGlacier/BoardInitDxe/BoardInitDxe.c
+++ b/Platform/BroxtonPlatformPkg/Board/AuroraGlacier/BoardInitDxe/BoardInitDxe.c
@@ -15,6 +15,7 @@
**/
#include "BoardInitDxe.h"
+#include <Protocol/SmbusHc.h>
GET_BOARD_NAME mAuroraGetBoardNamePtr = AuroraGetBoardName;
@@ -38,6 +39,111 @@ AuroraGetBoardName (
}
+VOID
+EFIAPI
+AuroraProgramPmicPowerSequence (
+ EFI_EVENT Event,
+ VOID *Context
+ )
+{
+ EFI_STATUS Status;
+ EFI_SMBUS_DEVICE_ADDRESS SlaveAddress;
+ EFI_SMBUS_DEVICE_COMMAND Command;
+ UINTN Length;
+ UINT8 BufferData[1];
+ EFI_SMBUS_HC_PROTOCOL *SmbusControllerProtocol;
+
+ //
+ // Programe IDTP9810 PMIC.
+ //
+
+ DEBUG ((EFI_D_INFO, "Programe PMIC. \n"));
+
+ //
+ // Locate SMBus protocol
+ //
+ Status = gBS->LocateProtocol (&gEfiSmbusHcProtocolGuid, NULL, (VOID **)&SmbusControllerProtocol);
+ ASSERT_EFI_ERROR(Status);
+
+ SlaveAddress.SmbusDeviceAddress = (0xBC >> 1); // 0x5E
+ Command = 0x00; // Offset
+ Length = 1;
+
+ //
+ // Read one byte
+ //
+ Status = SmbusControllerProtocol->Execute (
+ SmbusControllerProtocol,
+ SlaveAddress,
+ Command,
+ EfiSmbusReadByte,
+ FALSE,
+ &Length,
+ BufferData
+ );
+
+
+ DEBUG ((EFI_D_INFO, "PMIC Vendor ID = %0x. \n", (UINT32) BufferData[0]));
+
+
+ SlaveAddress.SmbusDeviceAddress = (0xBC >> 1); // 0x5E
+ Command = 0x2A; // Offset
+ Length = 1;
+
+ //
+ // Read one byte
+ //
+ Status = SmbusControllerProtocol->Execute (
+ SmbusControllerProtocol,
+ SlaveAddress,
+ Command,
+ EfiSmbusReadByte,
+ FALSE,
+ &Length,
+ BufferData
+ );
+
+
+ DEBUG ((EFI_D_INFO, "PMIC Power Sequence Configuration Offset 0x2A PWRSEQCFG = %0x. \n", (UINT32) BufferData[0]));
+
+ //
+ // Set Bit 2 (SUSPWRDNACKCFG) of PWRSEQCFG.
+ // 0 = SUSPWRDNACK signal is ignored. PMIC will not go to G3 when SUSPWRDNACK goes high in S4 state.
+ // 1 = PMIC responses to SUSPWRDNACK signal.
+ //
+ //
+ BufferData[0] = BufferData[0] | 0x04;
+ Status = SmbusControllerProtocol->Execute (
+ SmbusControllerProtocol,
+ SlaveAddress,
+ Command,
+ EfiSmbusWriteByte,
+ FALSE,
+ &Length,
+ BufferData
+ );
+ DEBUG ((EFI_D_INFO, "PMIC Power Sequence Configuration Set Bit 2 (SUSPWRDNACKCFG) of PWRSEQCFG. \n"));
+
+
+ //
+ // Read one byte
+ //
+ Status = SmbusControllerProtocol->Execute (
+ SmbusControllerProtocol,
+ SlaveAddress,
+ Command,
+ EfiSmbusReadByte,
+ FALSE,
+ &Length,
+ BufferData
+ );
+
+
+ DEBUG ((EFI_D_INFO, "PMIC Power Sequence Configuration Offset 0x2A PWRSEQCFG = %0x. \n", (UINT32) BufferData[0]));
+}
+
+
+
/**
Set PCDs for board specific functions.
@@ -55,6 +161,7 @@ AuroraBoardInitDxeConstructor (
)
{
UINT8 BoardId;
+ EFI_EVENT ReadyToBootEvent;
BoardId = PcdGet8 (PcdBoardId);
if (BoardId != (UINT8) BOARD_ID_AURORA) {
@@ -63,6 +170,13 @@ AuroraBoardInitDxeConstructor (
PcdSet64 (PcdGetBoardNameFunc, (UINT64) mAuroraGetBoardNamePtr);
+ EfiCreateEventReadyToBootEx (
+ TPL_CALLBACK,
+ AuroraProgramPmicPowerSequence,
+ NULL,
+ &ReadyToBootEvent
+ );
+
return EFI_SUCCESS;
}
diff --git a/Platform/BroxtonPlatformPkg/Board/AuroraGlacier/BoardInitDxe/BoardInitDxe.inf b/Platform/BroxtonPlatformPkg/Board/AuroraGlacier/BoardInitDxe/BoardInitDxe.inf
index 62899f61e..5fb96438a 100644
--- a/Platform/BroxtonPlatformPkg/Board/AuroraGlacier/BoardInitDxe/BoardInitDxe.inf
+++ b/Platform/BroxtonPlatformPkg/Board/AuroraGlacier/BoardInitDxe/BoardInitDxe.inf
@@ -43,6 +43,7 @@
PrintLib
[Protocols]
+ gEfiSmbusHcProtocolGuid
[Guids]
diff --git a/Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitDxe/BoardInitDxe.c b/Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitDxe/BoardInitDxe.c
index d49d2594e..702c53c49 100644
--- a/Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitDxe/BoardInitDxe.c
+++ b/Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitDxe/BoardInitDxe.c
@@ -2,7 +2,7 @@
Board specific functions in DXE phase to be set as dynamic PCD and consumed by
commmon platform code.
- Copyright (c) 2009 - 2017, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
@@ -15,6 +15,7 @@
**/
#include "BoardInitDxe.h"
+#include <Protocol/SmbusHc.h>
GET_BOARD_NAME mBgGetBoardNamePtr = BgGetBoardName;
@@ -38,6 +39,110 @@ BgGetBoardName (
}
+VOID
+EFIAPI
+BensonProgramPmicPowerSequence (
+ EFI_EVENT Event,
+ VOID *Context
+ )
+{
+ EFI_STATUS Status;
+ EFI_SMBUS_DEVICE_ADDRESS SlaveAddress;
+ EFI_SMBUS_DEVICE_COMMAND Command;
+ UINTN Length;
+ UINT8 BufferData[1];
+ EFI_SMBUS_HC_PROTOCOL *SmbusControllerProtocol;
+
+ //
+ // Programe PMIC.
+ //
+
+ DEBUG ((EFI_D_INFO, "Programe IDTP9810 PMIC. \n"));
+
+ //
+ // Locate SMBus protocol
+ //
+ Status = gBS->LocateProtocol (&gEfiSmbusHcProtocolGuid, NULL, (VOID **)&SmbusControllerProtocol);
+ ASSERT_EFI_ERROR(Status);
+
+ SlaveAddress.SmbusDeviceAddress = (0xBC >> 1); // 0x5E
+ Command = 0x00; // Offset
+ Length = 1;
+
+ //
+ // Read one byte
+ //
+ Status = SmbusControllerProtocol->Execute (
+ SmbusControllerProtocol,
+ SlaveAddress,
+ Command,
+ EfiSmbusReadByte,
+ FALSE,
+ &Length,
+ BufferData
+ );
+
+
+ DEBUG ((EFI_D_INFO, "PMIC Vendor ID = %0x. \n", (UINT32) BufferData[0]));
+
+
+ SlaveAddress.SmbusDeviceAddress = (0xBC >> 1); // 0x5E
+ Command = 0x2A; // Offset
+ Length = 1;
+
+ //
+ // Read one byte
+ //
+ Status = SmbusControllerProtocol->Execute (
+ SmbusControllerProtocol,
+ SlaveAddress,
+ Command,
+ EfiSmbusReadByte,
+ FALSE,
+ &Length,
+ BufferData
+ );
+
+
+ DEBUG ((EFI_D_INFO, "PMIC Power Sequence Configuration Offset 0x2A PWRSEQCFG = %0x. \n", (UINT32) BufferData[0]));
+
+ //
+ // Set Bit 2 (SUSPWRDNACKCFG) of PWRSEQCFG.
+ // 0 = SUSPWRDNACK signal is ignored. PMIC will not go to G3 when SUSPWRDNACK goes high in S4 state.
+ // 1 = PMIC responses to SUSPWRDNACK signal.
+ //
+ BufferData[0] = BufferData[0] | 0x04;
+ Status = SmbusControllerProtocol->Execute (
+ SmbusControllerProtocol,
+ SlaveAddress,
+ Command,
+ EfiSmbusWriteByte,
+ FALSE,
+ &Length,
+ BufferData
+ );
+ DEBUG ((EFI_D_INFO, "PMIC Power Sequence Configuration Set Bit 2 (SUSPWRDNACKCFG) of PWRSEQCFG. \n"));
+
+
+ //
+ // Read one byte
+ //
+ Status = SmbusControllerProtocol->Execute (
+ SmbusControllerProtocol,
+ SlaveAddress,
+ Command,
+ EfiSmbusReadByte,
+ FALSE,
+ &Length,
+ BufferData
+ );
+
+
+ DEBUG ((EFI_D_INFO, "PMIC Power Sequence Configuration Offset 0x2A PWRSEQCFG = %0x. \n", (UINT32) BufferData[0]));
+}
+
+
+
/**
Set PCDs for board specific functions.
@@ -55,6 +160,7 @@ BgBoardInitDxeConstructor (
)
{
UINT8 BoardId;
+ EFI_EVENT ReadyToBootEvent;
BoardId = PcdGet8 (PcdBoardId);
if (BoardId != (UINT8) BOARD_ID_BENSON) {
@@ -63,6 +169,13 @@ BgBoardInitDxeConstructor (
PcdSet64 (PcdGetBoardNameFunc, (UINT64) mBgGetBoardNamePtr);
+ EfiCreateEventReadyToBootEx (
+ TPL_CALLBACK,
+ BensonProgramPmicPowerSequence,
+ NULL,
+ &ReadyToBootEvent
+ );
+
return EFI_SUCCESS;
}
diff --git a/Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitDxe/BoardInitDxe.inf b/Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitDxe/BoardInitDxe.inf
index d7e7400cb..2f5a1a406 100644
--- a/Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitDxe/BoardInitDxe.inf
+++ b/Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitDxe/BoardInitDxe.inf
@@ -43,6 +43,7 @@
PrintLib
[Protocols]
+ gEfiSmbusHcProtocolGuid
[Guids]
diff --git a/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformDxe/PlatformDxe.inf b/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformDxe/PlatformDxe.inf
index 8cb63e946..440071fd4 100644
--- a/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformDxe/PlatformDxe.inf
+++ b/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformDxe/PlatformDxe.inf
@@ -120,7 +120,7 @@
gEfiSeCOperationProtocolGuid
gEfiUgaDrawProtocolGuid
gEfiUgaDrawProtocolGuid |PcdUgaConsumeSupport
- gEfiShellProtocolGuid
+ gEfiShellProtocolGuid
[Pcd]
gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress
diff --git a/Platform/BroxtonPlatformPkg/PlatformPkg.fdf b/Platform/BroxtonPlatformPkg/PlatformPkg.fdf
index a037708f7..6c377553f 100644
--- a/Platform/BroxtonPlatformPkg/PlatformPkg.fdf
+++ b/Platform/BroxtonPlatformPkg/PlatformPkg.fdf
@@ -692,6 +692,11 @@ APRIORI DXE {
#
INF MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf
INF $(PLATFORM_PACKAGE_COMMON)/Features/Smbios/SmBiosMiscDxe/SmBiosMiscDxe.inf
+
+ #
+ #SM Bus
+ #
+ INF $(PLATFORM_SI_PACKAGE)/SouthCluster/Smbus/Dxe/PchSmbusDxe.inf
#
# LAN/Network
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SiPkgDxe.dsc b/Silicon/BroxtonSoC/BroxtonSiPkg/SiPkgDxe.dsc
index 4ae080302..1a9da7729 100644
--- a/Silicon/BroxtonSoC/BroxtonSiPkg/SiPkgDxe.dsc
+++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SiPkgDxe.dsc
@@ -1,7 +1,7 @@
## @file
# Component description file for the Broxton RC DXE drivers.
#
-# Copyright (c) 2004 - 2017, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2004 - 2018, Intel Corporation. All rights reserved.<BR>
#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
@@ -41,3 +41,16 @@ $(PLATFORM_SI_PACKAGE)/Hsti/Dxe/HstiSiliconDxe.inf {
}
!endif
+$(PLATFORM_SI_PACKAGE)/SouthCluster/Smbus/Dxe/PchSmbusDxe.inf {
+ <PcdsPatchableInModule>
+ gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0xFFFFFFFF
+ <PcdsFixedAtBuild>
+ gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x27
+ <LibraryClasses>
+!if $(TARGET) != RELEASE
+ DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf
+!endif
+ <BuildOptions>
+ ICC:*_*_*_CC_FLAGS = /D MDEPKG_NDEBUG
+ GCC:*_*_*_CC_FLAGS = -D MDEPKG_NDEBUG
+ }
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SiPkgDxeLib.dsc b/Silicon/BroxtonSoC/BroxtonSiPkg/SiPkgDxeLib.dsc
index ff36dccd4..935691a29 100644
--- a/Silicon/BroxtonSoC/BroxtonSiPkg/SiPkgDxeLib.dsc
+++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SiPkgDxeLib.dsc
@@ -1,7 +1,7 @@
## @file
# Component description file for the Broxton RC DXE libraries.
#
-# Copyright (c) 2004 - 2016, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2004 - 2018, Intel Corporation. All rights reserved.<BR>
#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
@@ -33,3 +33,7 @@
HeciMsgLib|$(PLATFORM_SI_PACKAGE)/Txe/Library/HeciMsgLib/DxeSmmHeciMsgLib.inf
SeCLib|$(PLATFORM_SI_PACKAGE)/Txe/Library/SeCLib/SeCLib.inf
+#
+# SMBus
+#
+ ScSmbusCommonLib|$(PLATFORM_SI_PACKAGE)/SouthCluster/Library/Private/PeiDxeSmmScSmbusCommonLib/PeiDxeSmmScSmbusCommonLib.inf
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Smbus/Dxe/PchSmbus.h b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Smbus/Dxe/PchSmbus.h
index 5e226a80d..6218de8dd 100644
--- a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Smbus/Dxe/PchSmbus.h
+++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Smbus/Dxe/PchSmbus.h
@@ -92,7 +92,7 @@ typedef struct _SMBUS_INSTANCE {
//
// Driver global data
//
-SMBUS_INSTANCE *mSmbusContext;
+extern SMBUS_INSTANCE *mSmbusContext;
//
// Prototypes
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Smbus/Dxe/PchSmbusEntry.c b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Smbus/Dxe/PchSmbusEntry.c
index 6ae16f343..021cf26c9 100644
--- a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Smbus/Dxe/PchSmbusEntry.c
+++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Smbus/Dxe/PchSmbusEntry.c
@@ -17,6 +17,8 @@
extern EFI_GUID gEfiSmbusArpMapGuid;
+SMBUS_INSTANCE *mSmbusContext;
+
/**
Execute an SMBus operation
--
2.14.1.windows.1
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