[edk2] [Patch][edk2-platforms/devel-MinnowBoard3] SPI Flash Lock.

zwei4 posted 1 patch 131 weeks ago
Failed in applying to current master (apply log)
.../PeiFspPolicyInitLib/PeiFspScPolicyInitLib.c    |  4 +-
.../Library/PeiPolicyUpdateLib/PeiScPolicyUpdate.c | 39 +-----------
.../PlatformSetupDxe/SouthClusterConfig.vfi        |  4 +-
.../BroxtonSiPkg/SouthCluster/ScInit/Dxe/ScInit.c  | 71 ----------------------
4 files changed, 5 insertions(+), 113 deletions(-)

[edk2] [Patch][edk2-platforms/devel-MinnowBoard3] SPI Flash Lock.

Posted by zwei4 131 weeks ago
Cleanup code about locking SPI Flash; Change the default value of BIOS Lock setup option to FALSE.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: David Wei <david.wei@intel.com>
---
 .../PeiFspPolicyInitLib/PeiFspScPolicyInitLib.c    |  4 +-
 .../Library/PeiPolicyUpdateLib/PeiScPolicyUpdate.c | 39 +-----------
 .../PlatformSetupDxe/SouthClusterConfig.vfi        |  4 +-
 .../BroxtonSiPkg/SouthCluster/ScInit/Dxe/ScInit.c  | 71 ----------------------
 4 files changed, 5 insertions(+), 113 deletions(-)

diff --git a/Platform/BroxtonPlatformPkg/Common/Library/PeiFspPolicyInitLib/PeiFspScPolicyInitLib.c b/Platform/BroxtonPlatformPkg/Common/Library/PeiFspPolicyInitLib/PeiFspScPolicyInitLib.c
index 47ec70600..640900688 100644
--- a/Platform/BroxtonPlatformPkg/Common/Library/PeiFspPolicyInitLib/PeiFspScPolicyInitLib.c
+++ b/Platform/BroxtonPlatformPkg/Common/Library/PeiFspPolicyInitLib/PeiFspScPolicyInitLib.c
@@ -1,7 +1,7 @@
 /** @file
   Implementation of Fsp SC Policy Initialization.
 
-  Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.<BR>
+  Copyright (c) 2015 - 2017, Intel Corporation. All rights reserved.<BR>
 
   This program and the accompanying materials
   are licensed and made available under the terms and conditions of the BSD License
@@ -601,7 +601,7 @@ PeiFspScPolicyInit (
         // Flash Protection Range Register initialization
         //
         for (Index = 0; Index < SC_FLASH_PROTECTED_RANGES; Index++) {
-          FspsUpd->FspsConfig.WriteProtectionEnable[Index]  = TRUE;
+          FspsUpd->FspsConfig.WriteProtectionEnable[Index]  = SystemConfiguration->ScBiosLock == TRUE ? TRUE : FALSE;
           FspsUpd->FspsConfig.ReadProtectionEnable[Index]   = FALSE;
         }
 
diff --git a/Platform/BroxtonPlatformPkg/Common/Library/PeiPolicyUpdateLib/PeiScPolicyUpdate.c b/Platform/BroxtonPlatformPkg/Common/Library/PeiPolicyUpdateLib/PeiScPolicyUpdate.c
index 6d9fc52de..c98a8df65 100644
--- a/Platform/BroxtonPlatformPkg/Common/Library/PeiPolicyUpdateLib/PeiScPolicyUpdate.c
+++ b/Platform/BroxtonPlatformPkg/Common/Library/PeiPolicyUpdateLib/PeiScPolicyUpdate.c
@@ -1,7 +1,7 @@
 /** @file
   This file is SampleCode of the library for Intel PCH PEI Policy initialization.
 
-  Copyright (c) 2004 - 2016, Intel Corporation. All rights reserved.<BR>
+  Copyright (c) 2004 - 2017, Intel Corporation. All rights reserved.<BR>
 
   This program and the accompanying materials
   are licensed and made available under the terms and conditions of the BSD License
@@ -277,13 +277,11 @@ UpdatePeiScPolicy (
   UINT16                          BoardId;
   UINTN                           VariableSize;
   SYSTEM_CONFIGURATION            SystemConfiguration;
-  UINT8                           Index;
   UINT8                           PortIndex;
   UINT32                          SpiHsfsReg;
   UINT32                          SpiFdodReg;
   UINT8                           DevIndex;
   UINT8                           HdaIndex;
-  BOOLEAN                         FlashProtectionEnabled;
   SC_GENERAL_CONFIG               *GeneralConfig;
   SC_SATA_CONFIG                  *SataConfig;
   SC_PCIE_CONFIG                  *PcieConfig;
@@ -729,41 +727,6 @@ UpdatePeiScPolicy (
   }
   PmConfig->PowerButterDebounceMode = SystemConfiguration.PowerButterDebounceMode;
 
-  if ((GetBxtSeries() == BxtP) && (IsSpiBoot ())) {
-    //
-    // Configure Flash Protection Range Registers
-    //
-    FlashProtectionEnabled = SystemConfiguration.FprrEnable == TRUE ? TRUE : FALSE;
-
-    //
-    // Enabling Flash Protection Range Registers
-    // Enable FPRR policy and set up ranges on non-Capsule Update flow with Flash Wear-Out Protection enabled
-    // PrintFlashProtectionConfig() dumps FPRR information during ScPrintPolicyPpi()
-    // FPRR  bit is enabled by default as per Platform policy, except that when system is in recovery mode or FDO is enabled. In this case this will be disabled as part of Firmware Update / Recovery update
-    //
-    if (FlashProtectionEnabled && (FdoEnabledGuidHob == NULL)) {
-      //
-      // Flash Protection Range Register initialization
-      //
-      for (Index = 0; Index < SC_FLASH_PROTECTED_RANGES; Index++) {
-        FlashProtectionConfig->ProtectRange[Index].WriteProtectionEnable  = TRUE;
-        FlashProtectionConfig->ProtectRange[Index].ReadProtectionEnable   = FALSE;
-      }
-
-      DEBUG ((EFI_D_INFO, "IbbOffset = %x , IbbSize = %x\n", FixedPcdGet32 (PcdFlashIbbRegionMappedBase), FixedPcdGet32 (PcdFlashIbbRegionSize)));
-      DEBUG ((EFI_D_INFO, "ObbOffset = %x , ObbSize = %x\n", FixedPcdGet32 (PcdFlashObbRegionMappedBase), FixedPcdGet32 (PcdFlashObbRegionSize)));
-
-      //
-      // Assign FPRR ranges
-      //
-      FlashProtectionConfig->ProtectRange[0].ProtectedRangeBase    = (UINT16) ((FixedPcdGet32 (PcdFlashIbbRegionMappedBase) - FixedPcdGet32 (PcdFlashAreaBaseAddress)) >> 12);
-      FlashProtectionConfig->ProtectRange[0].ProtectedRangeLimit   = (UINT16) ((FixedPcdGet32 (PcdFlashIbbRegionMappedBase) - FixedPcdGet32 (PcdFlashAreaBaseAddress) + FixedPcdGet32 (PcdFlashIbbRegionSize) - 1) >> 12);
-      FlashProtectionConfig->ProtectRange[1].ProtectedRangeBase    = (UINT16) ((FixedPcdGet32 (PcdFlashObbRegionMappedBase) - FixedPcdGet32 (PcdFlashAreaBaseAddress)) >> 12);
-      FlashProtectionConfig->ProtectRange[1].ProtectedRangeLimit   = (UINT16) ((FixedPcdGet32 (PcdFlashObbRegionMappedBase) - FixedPcdGet32 (PcdFlashAreaBaseAddress) + FixedPcdGet32 (PcdFlashObbRegionSize) - 1) >> 12);
-    } else {
-      DEBUG ((DEBUG_INFO, " BIOS FPRR is not done  -FDO ASSERT Status "));
-    }
-  }
 
   DciConfig->DciEn         = SystemConfiguration.DciEn;
   DciConfig->DciAutoDetect = SystemConfiguration.DciAutoDetect;
diff --git a/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformSetupDxe/SouthClusterConfig.vfi b/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformSetupDxe/SouthClusterConfig.vfi
index 411006b38..f2a09c236 100644
--- a/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformSetupDxe/SouthClusterConfig.vfi
+++ b/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformSetupDxe/SouthClusterConfig.vfi
@@ -145,8 +145,8 @@ form formid     = MISC_OPTIONS_FORM_ID,
   oneof varid  = Setup.ScBiosLock,
     prompt   = STRING_TOKEN(STR_PCH_BLE_PROMPT),
     help     = STRING_TOKEN(STR_PCH_BLE_HELP),
-    option text = STRING_TOKEN(STR_DISABLED), value = 0, flags = RESET_REQUIRED;
-    option text = STRING_TOKEN(STR_ENABLED), value = 1, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED;
+    option text = STRING_TOKEN(STR_DISABLED), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED;
+    option text = STRING_TOKEN(STR_ENABLED), value = 1, flags = RESET_REQUIRED;
   endoneof;
   oneof varid  = Setup.RtcLock,
     prompt   = STRING_TOKEN(STR_PCH_RTC_LOCK_PROMPT),
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/ScInit/Dxe/ScInit.c b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/ScInit/Dxe/ScInit.c
index c4a9d5088..9620dacfb 100644
--- a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/ScInit/Dxe/ScInit.c
+++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/ScInit/Dxe/ScInit.c
@@ -624,22 +624,17 @@ ScOnEndOfDxe (
   )
 {
   EFI_STATUS                 Status;
-  UINTN                      Index;
   UINT32                     FuncDisableReg;
-  UINT32                     Data32;
   UINT32                     Data32And;
   UINT32                     Data32Or;
   UINT16                     AcpiBaseAddr;
   UINT32                     PmcBase;
   UINT8                      NumOfDevltrOverride;
-  UINT32                     DlockValue;
   UINTN                      PciLpcRegBase;
   UINTN                      PciSpiRegBase;
-  UINTN                      SpiBar0;
   BXT_SERIES                 BxtSeries;
   UINT8                      Data8;
   SC_LOCK_DOWN_CONFIG        *LockDownConfig;
-  SC_FLASH_PROTECTION_CONFIG *FlashProtectionConfig;
   UINT16                     Data16And;
   UINT16                     Data16Or;
   SI_POLICY_HOB              *SiPolicyHob;
@@ -680,72 +675,6 @@ ScOnEndOfDxe (
     (VOID *) (UINTN) (PmcBase + R_PMC_PMIR)
     );
 
-  if (BxtSeries == BxtP){
-    SpiBar0 = MmioRead32 (PciSpiRegBase + R_SPI_BASE) & ~(B_SPI_BAR0_MASK);
-    Status = GetConfigBlock ((VOID *) mScPolicy, &gFlashProtectionConfigGuid, (VOID *) &FlashProtectionConfig);
-    ASSERT_EFI_ERROR (Status);
-
-    //
-    // Program the Flash Protection Range Register based on policy
-    //
-    DlockValue = MmioRead32 (SpiBar0 + R_SPI_DLOCK);
-
-    FlashProtectionConfig->ProtectRange[0].ProtectedRangeBase    = (UINT16) ((FixedPcdGet32 (PcdFlashIbbRegionMappedBase) - FixedPcdGet32 (PcdFlashAreaBaseAddress)) >> 12);
-    FlashProtectionConfig->ProtectRange[0].ProtectedRangeLimit   = (UINT16) ((FixedPcdGet32 (PcdFlashIbbRegionMappedBase) - FixedPcdGet32 (PcdFlashAreaBaseAddress) + FixedPcdGet32 (PcdFlashIbbRegionSize) - 1) >> 12);
-    FlashProtectionConfig->ProtectRange[1].ProtectedRangeBase    = (UINT16) ((FixedPcdGet32 (PcdFlashObbRegionMappedBase) - FixedPcdGet32 (PcdFlashAreaBaseAddress)) >> 12);
-    FlashProtectionConfig->ProtectRange[1].ProtectedRangeLimit   = (UINT16) ((FixedPcdGet32 (PcdFlashObbRegionMappedBase) - FixedPcdGet32 (PcdFlashAreaBaseAddress) + FixedPcdGet32 (PcdFlashObbRegionSize) - 1) >> 12);
-
-    for (Index = 0; Index < SC_FLASH_PROTECTED_RANGES; ++Index) {
-      if ((FlashProtectionConfig->ProtectRange[Index].WriteProtectionEnable ||
-           FlashProtectionConfig->ProtectRange[Index].ReadProtectionEnable) != TRUE) {
-        continue;
-      }
-
-      //
-      // Proceed to program the register after ensure it is enabled
-      //
-      Data32 = 0;
-      Data32 |= (FlashProtectionConfig->ProtectRange[Index].WriteProtectionEnable == TRUE) ? B_SPI_PRX_WPE : 0;
-      Data32 |= (FlashProtectionConfig->ProtectRange[Index].ReadProtectionEnable == TRUE) ? B_SPI_PRX_RPE : 0;
-      Data32 |= ((UINT32) FlashProtectionConfig->ProtectRange[Index].ProtectedRangeLimit << N_SPI_PRX_PRL) & B_SPI_PRX_PRL_MASK;
-      Data32 |= ((UINT32) FlashProtectionConfig->ProtectRange[Index].ProtectedRangeBase << N_SPI_PRX_PRB) & B_SPI_PRX_PRB_MASK;
-      DEBUG ((DEBUG_INFO, "Protected range %d: 0x%08x \n", Index, Data32));
-
-      DlockValue |= (UINT32) (B_SPI_DLOCK_PR0LOCKDN << Index);
-      MmioWrite32 ((UINTN) (SpiBar0 + (R_SPI_PR0 + (Index * S_SPI_PRX))), Data32);
-      S3BootScriptSaveMemWrite (
-        S3BootScriptWidthUint32,
-        (UINTN) (SpiBar0 + (R_SPI_PR0 + (Index * S_SPI_PRX))),
-        1,
-        (VOID *) (UINTN) (SpiBar0 + (R_SPI_PR0 + (Index * S_SPI_PRX)))
-        );
-    }
-
-    //
-    // Program DLOCK register
-    //
-    MmioWrite32 ((UINTN) (SpiBar0 + R_SPI_DLOCK), DlockValue);
-    S3BootScriptSaveMemWrite (
-      S3BootScriptWidthUint32,
-      (UINTN) (SpiBar0 + R_SPI_DLOCK),
-      1,
-      (VOID *) (UINTN) (SpiBar0 + R_SPI_DLOCK)
-      );
-
-    //
-    // In SPI controller the BIOS should set the Flash Configuration Lock-Down bit
-    // (SPI_BAR0 + 04[15]) at end of post.  When set to 1, those Flash Program Registers
-    // that are locked down by this FLOCKDN bit cannot be written.
-    //
-    MmioOr32 ((UINTN) (SpiBar0 + R_SPI_HSFS), (UINT32) (B_SPI_HSFS_FLOCKDN));
-    S3BootScriptSaveMemWrite (
-      EfiBootScriptWidthUint32,
-      (UINTN) (SpiBar0 + R_SPI_HSFS),
-      1,
-      (VOID *) (UINTN) (SpiBar0 + R_SPI_HSFS)
-      );
-  }
-
   Status = GetConfigBlock ((VOID *) mScPolicy, &gLockDownConfigGuid, (VOID *) &LockDownConfig);
   ASSERT_EFI_ERROR (Status);
   if (LockDownConfig->GlobalSmi == TRUE) {
-- 
2.11.0.windows.1

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