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[edk2-devel] [PATCH edk2-platforms v2 3/3] Silicon/NXP: PciHostBridgeLib: Initialize only enabled PCIe controllers

Wasim Khan posted 3 patches 5 years, 8 months ago
There is a newer version of this series
[edk2-devel] [PATCH edk2-platforms v2 3/3] Silicon/NXP: PciHostBridgeLib: Initialize only enabled PCIe controllers
Posted by Wasim Khan 5 years, 8 months ago 
From: Wasim Khan <wasim.khan@nxp.com>

Based on the serdes protocol value in reset configuration
word (RCW), different PCIe controllers are enabled.
Get SerDes protocol map and initialize only enabled PCIe
controllers.

Signed-off-by: Wasim Khan <wasim.khan@nxp.com>
---

Notes:
    Changes in V2:
    - Addressed review comments for structure, variable and function names
    - Using BIT0 instead of 0x1u

 Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.inf |  1 +
 Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.c   | 35 +++++++++++++++++++-
 2 files changed, 35 insertions(+), 1 deletion(-)

diff --git a/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.inf b/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.inf
index aa5a9dec7c34..6003da708698 100644
--- a/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.inf
+++ b/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.inf
@@ -28,6 +28,7 @@ [LibraryClasses]
   IoAccessLib
   MemoryAllocationLib
   PcdLib
+  SocLib
 
 [FeaturePcd]
   gNxpQoriqLsTokenSpaceGuid.PcdPciLutBigEndian
diff --git a/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.c b/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.c
index e5309a4f4248..8bbbaaa6e24d 100644
--- a/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.c
+++ b/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.c
@@ -15,6 +15,7 @@
 #include <Library/MemoryAllocationLib.h>
 #include <Library/PcdLib.h>
 #include <Library/PciHostBridgeLib.h>
+#include <Library/SerDes.h>
 #include <Pcie.h>
 #include <Protocol/PciHostBridgeResourceAllocation.h>
 #include <Protocol/PciRootBridgeIo.h>
@@ -721,6 +722,32 @@ PcieSetupCntrl (
 }
 
 /**
+   This function checks whether PCIe is enabled or not
+   depending upon SoC serdes protocol map
+
+   @param  PcieNum PCIe number.
+
+   @return The     PCIe number enabled in map.
+   @return FALSE   PCIe number is disabled in map.
+
+**/
+STATIC
+BOOLEAN
+IsPcieNumEnabled(
+  IN UINTN PcieNum
+  )
+{
+  UINT64 SerDesProtocolMap;
+
+  SerDesProtocolMap = 0;
+
+  // Reading serdes protocol map
+  GetSerDesProtocolMap (&SerDesProtocolMap);
+
+  return (SerDesProtocolMap & (BIT0 << (PcieNum))) != 0;
+}
+
+/**
   Return all the root bridge instances in an array.
 
   @param Count  Return the count of root bridge instances.
@@ -752,13 +779,19 @@ PciHostBridgeGetRootBridges (
     PciPhyIoAddr [Idx] =  PCI_SEG0_PHY_IO_BASE + (PCI_BASE_DIFF * Idx);
     Regs[Idx] =  PCI_SEG0_DBI_BASE + (PCI_DBI_SIZE_DIFF * Idx);
 
+    // Check is the PCIe controller is enabled
+    if (IsPcieNumEnabled (Idx + 1) == 0) {
+      DEBUG ((DEBUG_INFO, "PCIE%d reg @ 0x%lx is disabled \n", Idx + 1, Regs[Idx]));
+      continue;
+    }
+
     // Check PCIe Link
     LinkUp = PcieLinkUp(Regs[Idx], Idx);
 
     if (!LinkUp) {
       continue;
     }
-    DEBUG ((DEBUG_INFO, "PCIE%d Passed Linkup Phase\n", Idx + 1));
+    DEBUG ((DEBUG_INFO, "PCIE%d reg @ 0x%lx :Passed Linkup Phase\n", Idx + 1, Regs[Idx]));
     // Set up PCIe Controller and ATU windows
     PcieSetupCntrl (Regs[Idx],
                     PciPhyCfg0Addr[Idx],
-- 
2.7.4


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Re: [edk2-devel] [PATCH edk2-platforms v2 3/3] Silicon/NXP: PciHostBridgeLib: Initialize only enabled PCIe controllers
Posted by Leif Lindholm 5 years, 8 months ago 
On Sun, Jun 07, 2020 at 18:45:50 +0530, Wasim Khan wrote:
> From: Wasim Khan <wasim.khan@nxp.com>
> 
> Based on the serdes protocol value in reset configuration
> word (RCW), different PCIe controllers are enabled.
> Get SerDes protocol map and initialize only enabled PCIe
> controllers.
> 
> Signed-off-by: Wasim Khan <wasim.khan@nxp.com>

Reviewed-by: Leif Lindholm <leif@nuviainc.com>
For simplicity, could you send a full v3 out please?

Regards,

Leif

> ---
> 
> Notes:
>     Changes in V2:
>     - Addressed review comments for structure, variable and function names
>     - Using BIT0 instead of 0x1u
> 
>  Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.inf |  1 +
>  Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.c   | 35 +++++++++++++++++++-
>  2 files changed, 35 insertions(+), 1 deletion(-)
> 
> diff --git a/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.inf b/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.inf
> index aa5a9dec7c34..6003da708698 100644
> --- a/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.inf
> +++ b/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.inf
> @@ -28,6 +28,7 @@ [LibraryClasses]
>    IoAccessLib
>    MemoryAllocationLib
>    PcdLib
> +  SocLib
>  
>  [FeaturePcd]
>    gNxpQoriqLsTokenSpaceGuid.PcdPciLutBigEndian
> diff --git a/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.c b/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.c
> index e5309a4f4248..8bbbaaa6e24d 100644
> --- a/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.c
> +++ b/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.c
> @@ -15,6 +15,7 @@
>  #include <Library/MemoryAllocationLib.h>
>  #include <Library/PcdLib.h>
>  #include <Library/PciHostBridgeLib.h>
> +#include <Library/SerDes.h>
>  #include <Pcie.h>
>  #include <Protocol/PciHostBridgeResourceAllocation.h>
>  #include <Protocol/PciRootBridgeIo.h>
> @@ -721,6 +722,32 @@ PcieSetupCntrl (
>  }
>  
>  /**
> +   This function checks whether PCIe is enabled or not
> +   depending upon SoC serdes protocol map
> +
> +   @param  PcieNum PCIe number.
> +
> +   @return The     PCIe number enabled in map.
> +   @return FALSE   PCIe number is disabled in map.
> +
> +**/
> +STATIC
> +BOOLEAN
> +IsPcieNumEnabled(
> +  IN UINTN PcieNum
> +  )
> +{
> +  UINT64 SerDesProtocolMap;
> +
> +  SerDesProtocolMap = 0;
> +
> +  // Reading serdes protocol map
> +  GetSerDesProtocolMap (&SerDesProtocolMap);
> +
> +  return (SerDesProtocolMap & (BIT0 << (PcieNum))) != 0;
> +}
> +
> +/**
>    Return all the root bridge instances in an array.
>  
>    @param Count  Return the count of root bridge instances.
> @@ -752,13 +779,19 @@ PciHostBridgeGetRootBridges (
>      PciPhyIoAddr [Idx] =  PCI_SEG0_PHY_IO_BASE + (PCI_BASE_DIFF * Idx);
>      Regs[Idx] =  PCI_SEG0_DBI_BASE + (PCI_DBI_SIZE_DIFF * Idx);
>  
> +    // Check is the PCIe controller is enabled
> +    if (IsPcieNumEnabled (Idx + 1) == 0) {
> +      DEBUG ((DEBUG_INFO, "PCIE%d reg @ 0x%lx is disabled \n", Idx + 1, Regs[Idx]));
> +      continue;
> +    }
> +
>      // Check PCIe Link
>      LinkUp = PcieLinkUp(Regs[Idx], Idx);
>  
>      if (!LinkUp) {
>        continue;
>      }
> -    DEBUG ((DEBUG_INFO, "PCIE%d Passed Linkup Phase\n", Idx + 1));
> +    DEBUG ((DEBUG_INFO, "PCIE%d reg @ 0x%lx :Passed Linkup Phase\n", Idx + 1, Regs[Idx]));
>      // Set up PCIe Controller and ATU windows
>      PcieSetupCntrl (Regs[Idx],
>                      PciPhyCfg0Addr[Idx],
> -- 
> 2.7.4
> 

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