[v2] Add PCIe Support

[edk2-devel] [PATCH edk2-platforms v2 00/16] Add PCIe Support

Posted by Wasim Khan 3 years, 11 months ago

From: Wasim Khan <wasim.khan@nxp.com>

Add PCIe Support for NXP Layerscape SoC which supports
different PCIe controllers.
Use generic PCIe drivers and wire up PciHostBridgeLib,
PciSegmentLib and PciCpuIo2Dxe driver for controller
specific implementation.

V1 Series can be referred here:
https://edk2.groups.io/g/devel/message/60116?p=,,,20,0,0,0::relevance,,PCIe+Support,20,2,0,74395799


Changes in V2:
- Addressed review comments received on V1.

Meenakshi Aggarwal (1):
  Platform/NXP: LS1043aRdbPkg: Enable NetworkPkg

Wasim Khan (15):
  Silicon/NXP/NxpQoriqLs.dec: Add PCIe related PCDs.
  Silicon/NXP: LS1043A: Define PCIe related PCDs
  Silicon/NXP: Implement PciHostBridgeLib support
  Silicon/NXP: PciHostBridgeLib: CFG Shift feature support for PCIeLS
    Ctrl
  Silicon/NXP: PciHostBridgeLib: Setup PCIe LsGen4 Controller and ATU
    Windows
  Silicon/NXP: PciHostBridgeLib: add Workaround for A-011451
  Silicon/NXP: PciHostBridgeLib: Dump Layerscale Gen4 ATU windows
  Silicon/NXP: PciHostBridgeLib: Dump Layerscale iATU windows
  Silicon/NXP: Implement PciSegmentLib for PCIe Layerscape Controller
  Silicon/NXP: PciSegmentLib: Add ECAM config support for PCIe LS
    Controller
  Silicon/NXP: PciSegmentLib: Add support PCIe LsGen4 Controller
  Silicon/NXP: PciSegmentLib: LsGen4Ctrl: Add Workaround for A-011264
  Silicon/NXP/Drivers: Implement PciCpuIo2Dxe Driver
  Platform/NXP: LS1043aRdbPkg: Enable PCIE support
  Platform/NXP: LS1043aRdbPkg : Increase fv image size

 Silicon/NXP/NxpQoriqLs.dec                                |  12 +
 Silicon/NXP/LS1043A/LS1043A.dsc.inc                       |   7 +
 Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc              |  20 +
 Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf              |  20 +-
 Silicon/NXP/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.inf         |  40 +
 Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.inf |  43 +
 Silicon/NXP/Library/PciSegmentLib/PciSegmentLib.inf       |  36 +
 Silicon/NXP/Include/Pcie.h                                | 228 ++++++
 Silicon/NXP/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.c           | 628 +++++++++++++++
 Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.c   | 830 ++++++++++++++++++++
 Silicon/NXP/Library/PciSegmentLib/PciSegmentLib.c         | 699 +++++++++++++++++
 11 files changed, 2560 insertions(+), 3 deletions(-)
 create mode 100755 Silicon/NXP/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.inf
 create mode 100644 Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.inf
 create mode 100755 Silicon/NXP/Library/PciSegmentLib/PciSegmentLib.inf
 create mode 100755 Silicon/NXP/Include/Pcie.h
 create mode 100755 Silicon/NXP/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.c
 create mode 100644 Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.c
 create mode 100755 Silicon/NXP/Library/PciSegmentLib/PciSegmentLib.c

-- 
2.7.4


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Re: [edk2-devel] [PATCH edk2-platforms v2 00/16] Add PCIe Support

Posted by Ard Biesheuvel 3 years, 11 months ago

On 5/26/20 10:37 AM, Wasim Khan wrote:
> From: Wasim Khan <wasim.khan@nxp.com>
> 
> Add PCIe Support for NXP Layerscape SoC which supports
> different PCIe controllers.
> Use generic PCIe drivers and wire up PciHostBridgeLib,
> PciSegmentLib and PciCpuIo2Dxe driver for controller
> specific implementation.
> 
> V1 Series can be referred here:
> https://edk2.groups.io/g/devel/message/60116?p=,,,20,0,0,0::relevance,,PCIe+Support,20,2,0,74395799
> 
> 
> Changes in V2:
> - Addressed review comments received on V1.
> 

Thanks Wasim

Reviewed-by: Ard Biesheuvel <ard.biesheuvel@arm.com>

I took some liberties with the PciSegmentLib code to get rid of the 
inline functions in Pcie.h - please double check whether that code is 
still correct, and rebase your code before sending new work that applies 
on top of these changes.

Also, I failed to spot this in review, but preprocessor macros that 
resolve to values that are used in arithmetic expressions should really 
all contain outer (), or you will be pulling your hair out figuring out 
where the unexpected values are coming from. I fixed this up while 
committing (all in Pcie.h)

Pushed as 7a4035e9efd8..7121691cfcbc


> Meenakshi Aggarwal (1):
>    Platform/NXP: LS1043aRdbPkg: Enable NetworkPkg
> 
> Wasim Khan (15):
>    Silicon/NXP/NxpQoriqLs.dec: Add PCIe related PCDs.
>    Silicon/NXP: LS1043A: Define PCIe related PCDs
>    Silicon/NXP: Implement PciHostBridgeLib support
>    Silicon/NXP: PciHostBridgeLib: CFG Shift feature support for PCIeLS
>      Ctrl
>    Silicon/NXP: PciHostBridgeLib: Setup PCIe LsGen4 Controller and ATU
>      Windows
>    Silicon/NXP: PciHostBridgeLib: add Workaround for A-011451
>    Silicon/NXP: PciHostBridgeLib: Dump Layerscale Gen4 ATU windows
>    Silicon/NXP: PciHostBridgeLib: Dump Layerscale iATU windows
>    Silicon/NXP: Implement PciSegmentLib for PCIe Layerscape Controller
>    Silicon/NXP: PciSegmentLib: Add ECAM config support for PCIe LS
>      Controller
>    Silicon/NXP: PciSegmentLib: Add support PCIe LsGen4 Controller
>    Silicon/NXP: PciSegmentLib: LsGen4Ctrl: Add Workaround for A-011264
>    Silicon/NXP/Drivers: Implement PciCpuIo2Dxe Driver
>    Platform/NXP: LS1043aRdbPkg: Enable PCIE support
>    Platform/NXP: LS1043aRdbPkg : Increase fv image size
> 
>   Silicon/NXP/NxpQoriqLs.dec                                |  12 +
>   Silicon/NXP/LS1043A/LS1043A.dsc.inc                       |   7 +
>   Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc              |  20 +
>   Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf              |  20 +-
>   Silicon/NXP/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.inf         |  40 +
>   Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.inf |  43 +
>   Silicon/NXP/Library/PciSegmentLib/PciSegmentLib.inf       |  36 +
>   Silicon/NXP/Include/Pcie.h                                | 228 ++++++
>   Silicon/NXP/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.c           | 628 +++++++++++++++
>   Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.c   | 830 ++++++++++++++++++++
>   Silicon/NXP/Library/PciSegmentLib/PciSegmentLib.c         | 699 +++++++++++++++++
>   11 files changed, 2560 insertions(+), 3 deletions(-)
>   create mode 100755 Silicon/NXP/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.inf
>   create mode 100644 Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.inf
>   create mode 100755 Silicon/NXP/Library/PciSegmentLib/PciSegmentLib.inf
>   create mode 100755 Silicon/NXP/Include/Pcie.h
>   create mode 100755 Silicon/NXP/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.c
>   create mode 100644 Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.c
>   create mode 100755 Silicon/NXP/Library/PciSegmentLib/PciSegmentLib.c
> 


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Re: [edk2-devel] [PATCH edk2-platforms v2 00/16] Add PCIe Support

Posted by Ard Biesheuvel 3 years, 11 months ago

On 5/26/20 11:53 AM, Ard Biesheuvel wrote:
> On 5/26/20 10:37 AM, Wasim Khan wrote:
>> From: Wasim Khan <wasim.khan@nxp.com>
>>
>> Add PCIe Support for NXP Layerscape SoC which supports
>> different PCIe controllers.
>> Use generic PCIe drivers and wire up PciHostBridgeLib,
>> PciSegmentLib and PciCpuIo2Dxe driver for controller
>> specific implementation.
>>
>> V1 Series can be referred here:
>> https://edk2.groups.io/g/devel/message/60116?p=,,,20,0,0,0::relevance,,PCIe+Support,20,2,0,74395799 
>>
>>
>>
>> Changes in V2:
>> - Addressed review comments received on V1.
>>
> 
> Thanks Wasim
> 
> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@arm.com>
> 
> I took some liberties with the PciSegmentLib code to get rid of the 
> inline functions in Pcie.h - please double check whether that code is 
> still correct, and rebase your code before sending new work that applies 
> on top of these changes.
> 
> Also, I failed to spot this in review, but preprocessor macros that 
> resolve to values that are used in arithmetic expressions should really 
> all contain outer (), or you will be pulling your hair out figuring out 
> where the unexpected values are coming from. I fixed this up while 
> committing (all in Pcie.h)
> 
> Pushed as 7a4035e9efd8..7121691cfcbc
> 

One thing I realized is that this method of accessing config space is 
not reentrant. This could potentially cause problems, e.g., when some 
notification callback accesses the PCI config space, and reprograms some 
of these windows. If such a callback interrupts an ordinary config space 
access between the time it programs the window and the time it does the 
access, you may be accessing the wrong part of config space.

The usual way of dealing with this is to raise the TPL (Thread Priority 
Level) to TPL_NOTIFY while performing the accesses. So please take this 
into consideration for a followup series.


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