Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc | 19 +- Platform/Marvell/Armada70x0Db/Armada70x0Db.dsc | 4 +- Platform/Marvell/Armada80x0Db/Armada80x0Db.dsc | 4 +- Platform/SolidRun/Armada80x0McBin/Armada80x0McBin.dsc | 4 +- Silicon/Marvell/Armada7k8k/Armada7k8k.fdf | 5 + Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db.inf | 1 + Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db.inf | 1 + Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin.inf | 1 + Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciExpressLib/PciExpressLib.inf | 42 + Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciHostBridgeLib/PciHostBridgeLib.inf | 52 + Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db/Pcie.h | 26 + Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db/Pcie.h | 26 + Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Pcie.h | 26 + Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciHostBridgeLib/PciHostBridgeLibConstructor.h | 95 ++ Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.h | 6 + Silicon/Marvell/Include/Library/ArmadaBoardDescLib.h | 46 + Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h | 20 + Silicon/Marvell/Include/Library/MvGpioLib.h | 1 + Silicon/Marvell/Include/Protocol/BoardDesc.h | 22 + Platform/Marvell/Armada70x0Db/Armada70x0DbBoardDescLib/Armada70x0DbBoardDescLib.c | 48 + Platform/Marvell/Armada70x0Db/NonDiscoverableInitLib/NonDiscoverableInitLib.c | 4 + Platform/Marvell/Armada80x0Db/Armada80x0DbBoardDescLib/Armada80x0DbBoardDescLib.c | 48 + Platform/Marvell/Armada80x0Db/NonDiscoverableInitLib/NonDiscoverableInitLib.c | 6 + Platform/SolidRun/Armada80x0McBin/Armada80x0McBinBoardDescLib/Armada80x0McBinBoardDescLib.c | 54 + Platform/SolidRun/Armada80x0McBin/NonDiscoverableInitLib/NonDiscoverableInitLib.c | 1 + Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciExpressLib/PciExpressLib.c | 1531 ++++++++++++++++++++ Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciHostBridgeLib/PciHostBridgeLib.c | 265 ++++ Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciHostBridgeLib/PciHostBridgeLibConstructor.c | 345 +++++ Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.c | 44 + Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.c | 86 ++ Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db/Dsdt.asl | 108 ++ Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db/Mcfg.aslc | 47 + Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db/Dsdt.asl | 108 ++ Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db/Mcfg.aslc | 47 + Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Dsdt.asl | 108 ++ Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Mcfg.aslc | 47 + Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040-mcbin.dts | 3 + 37 files changed, 3290 insertions(+), 11 deletions(-) create mode 100644 Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciExpressLib/PciExpressLib.inf create mode 100644 Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciHostBridgeLib/PciHostBridgeLib.inf create mode 100644 Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db/Pcie.h create mode 100644 Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db/Pcie.h create mode 100644 Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Pcie.h create mode 100644 Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciHostBridgeLib/PciHostBridgeLibConstructor.h create mode 100644 Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciExpressLib/PciExpressLib.c create mode 100644 Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciHostBridgeLib/PciHostBridgeLib.c create mode 100644 Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciHostBridgeLib/PciHostBridgeLibConstructor.c create mode 100644 Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db/Mcfg.aslc create mode 100644 Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db/Mcfg.aslc create mode 100644 Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Mcfg.aslc
Hi, Thank you for thorough review of v1. I submit second version of the Armada7k8k PCIE support. I addressed all comments. There is no functional change to initial patchset, but mostly clean-up and improvements - please refer to the changelog below. The patches are available in the github: https://github.com/MarvellEmbeddedProcessors/edk2-open-platform/commits/pcie-upstream-r20190520 I'm looking forward to your comments or remarks. Best regards, Marcin Changelog: v1->v2: *All - s/PcieBaseAddress/PcieDbiAdress/ *2/14 - fix alignment in comment * 3/14 - add CONST** to library callback * 4/14 - add missing reset GPIO to McBin description * 5/15 - add CONST** to protocol callback * 6/14 - cleanup all casting in file - use MAX_UINTx macros - add Linaro copyright - use MmioWrite8 instead of volatile in PciExpressReadBuffer - correct commient in IgnoreBusDeviceFunction () - fix typo in commit message * 7/10 - correct line endings - use temporary variable for memory description in PciHostBridgeResourceConflict - use MAX_UINTx macros - add comments around stalls and MemoryFence in GPIO reset - keep the reset active for 150ms - assign translation values instead of asserting *8/14 - assign gArmTokenSpaceGuid.PcdPciIoTranslation value in .dsc * 9-11/14 - correct line endings - remove unused methods - extend commit messages with 32k shift description Ard Biesheuvel (1): Marvell/Armada7k8k: Add PciExpressLib implementation Marcin Wojtas (13): Marvell/Library: MvGpioLib: Extend GPIO pin description Marvell/Library: ArmadaSoCDescLib: Add PCIE information Marvell/Library: ArmadaBoardDescLib: Add PCIE information Marvell/Armada7k8k: Extend board description libraries with PCIE Marvell/Armada7k8k: MvBoardDesc: Extend protocol with PCIE support Marvell/Armada7k8k: Implement PciHostBridgeLib Marvell/Armada7k8k: Enable PCIE support Marvell/Armada80x0McBin: Enable ACPI PCIE support Marvell/Armada80x0Db: Enable ACPI PCIE support Marvell/Armada70x0Db: Enable ACPI PCIE support Marvell/Armada80x0McBin: DeviceTree: Use pci-host-generic driver Marvell/Armada7k8k: Remove duplication in .dsc files Marvell/Armada7k8: Add 'acpiview' shell command to build Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc | 19 +- Platform/Marvell/Armada70x0Db/Armada70x0Db.dsc | 4 +- Platform/Marvell/Armada80x0Db/Armada80x0Db.dsc | 4 +- Platform/SolidRun/Armada80x0McBin/Armada80x0McBin.dsc | 4 +- Silicon/Marvell/Armada7k8k/Armada7k8k.fdf | 5 + Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db.inf | 1 + Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db.inf | 1 + Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin.inf | 1 + Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciExpressLib/PciExpressLib.inf | 42 + Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciHostBridgeLib/PciHostBridgeLib.inf | 52 + Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db/Pcie.h | 26 + Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db/Pcie.h | 26 + Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Pcie.h | 26 + Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciHostBridgeLib/PciHostBridgeLibConstructor.h | 95 ++ Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.h | 6 + Silicon/Marvell/Include/Library/ArmadaBoardDescLib.h | 46 + Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h | 20 + Silicon/Marvell/Include/Library/MvGpioLib.h | 1 + Silicon/Marvell/Include/Protocol/BoardDesc.h | 22 + Platform/Marvell/Armada70x0Db/Armada70x0DbBoardDescLib/Armada70x0DbBoardDescLib.c | 48 + Platform/Marvell/Armada70x0Db/NonDiscoverableInitLib/NonDiscoverableInitLib.c | 4 + Platform/Marvell/Armada80x0Db/Armada80x0DbBoardDescLib/Armada80x0DbBoardDescLib.c | 48 + Platform/Marvell/Armada80x0Db/NonDiscoverableInitLib/NonDiscoverableInitLib.c | 6 + Platform/SolidRun/Armada80x0McBin/Armada80x0McBinBoardDescLib/Armada80x0McBinBoardDescLib.c | 54 + Platform/SolidRun/Armada80x0McBin/NonDiscoverableInitLib/NonDiscoverableInitLib.c | 1 + Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciExpressLib/PciExpressLib.c | 1531 ++++++++++++++++++++ Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciHostBridgeLib/PciHostBridgeLib.c | 265 ++++ Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciHostBridgeLib/PciHostBridgeLibConstructor.c | 345 +++++ Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.c | 44 + Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.c | 86 ++ Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db/Dsdt.asl | 108 ++ Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db/Mcfg.aslc | 47 + Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db/Dsdt.asl | 108 ++ Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db/Mcfg.aslc | 47 + Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Dsdt.asl | 108 ++ Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Mcfg.aslc | 47 + Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040-mcbin.dts | 3 + 37 files changed, 3290 insertions(+), 11 deletions(-) create mode 100644 Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciExpressLib/PciExpressLib.inf create mode 100644 Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciHostBridgeLib/PciHostBridgeLib.inf create mode 100644 Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db/Pcie.h create mode 100644 Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db/Pcie.h create mode 100644 Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Pcie.h create mode 100644 Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciHostBridgeLib/PciHostBridgeLibConstructor.h create mode 100644 Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciExpressLib/PciExpressLib.c create mode 100644 Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciHostBridgeLib/PciHostBridgeLib.c create mode 100644 Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciHostBridgeLib/PciHostBridgeLibConstructor.c create mode 100644 Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db/Mcfg.aslc create mode 100644 Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db/Mcfg.aslc create mode 100644 Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Mcfg.aslc -- 2.7.4 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#41067): https://edk2.groups.io/g/devel/message/41067 Mute This Topic: https://groups.io/mt/31686565/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=-=-=-=-=-=-=-=-=-=-=-
> From: Marcin Wojtas <mw@semihalf.com> > Date: Mon, 20 May 2019 17:27:13 +0200 > > Hi, > > Thank you for thorough review of v1. I submit second > version of the Armada7k8k PCIE support. I addressed > all comments. There is no functional change to initial > patchset, but mostly clean-up and improvements - please > refer to the changelog below. > > The patches are available in the github: > https://github.com/MarvellEmbeddedProcessors/edk2-open-platform/commits/pcie-upstream-r20190520 > > I'm looking forward to your comments or remarks. > > Best regards, > Marcin Tested this on my mcbin running OpenBSD. It incovers a small issue in our kernel which I'm fixing. Otherwise this seems to work fine. So tested-by: Mark Kettenis <kettenis@openbsd.org> if that matters. Cheers, Mark > Changelog: > v1->v2: > *All > - s/PcieBaseAddress/PcieDbiAdress/ > > *2/14 > - fix alignment in comment > > * 3/14 > - add CONST** to library callback > > * 4/14 > - add missing reset GPIO to McBin description > > * 5/15 > - add CONST** to protocol callback > > * 6/14 > - cleanup all casting in file > - use MAX_UINTx macros > - add Linaro copyright > - use MmioWrite8 instead of volatile in PciExpressReadBuffer > - correct commient in IgnoreBusDeviceFunction () > - fix typo in commit message > > * 7/10 > - correct line endings > - use temporary variable for memory description in PciHostBridgeResourceConflict > - use MAX_UINTx macros > - add comments around stalls and MemoryFence in GPIO reset > - keep the reset active for 150ms > - assign translation values instead of asserting > > *8/14 > - assign gArmTokenSpaceGuid.PcdPciIoTranslation value in .dsc > > * 9-11/14 > - correct line endings > - remove unused methods > - extend commit messages with 32k shift description > > Ard Biesheuvel (1): > Marvell/Armada7k8k: Add PciExpressLib implementation > > Marcin Wojtas (13): > Marvell/Library: MvGpioLib: Extend GPIO pin description > Marvell/Library: ArmadaSoCDescLib: Add PCIE information > Marvell/Library: ArmadaBoardDescLib: Add PCIE information > Marvell/Armada7k8k: Extend board description libraries with PCIE > Marvell/Armada7k8k: MvBoardDesc: Extend protocol with PCIE support > Marvell/Armada7k8k: Implement PciHostBridgeLib > Marvell/Armada7k8k: Enable PCIE support > Marvell/Armada80x0McBin: Enable ACPI PCIE support > Marvell/Armada80x0Db: Enable ACPI PCIE support > Marvell/Armada70x0Db: Enable ACPI PCIE support > Marvell/Armada80x0McBin: DeviceTree: Use pci-host-generic driver > Marvell/Armada7k8k: Remove duplication in .dsc files > Marvell/Armada7k8: Add 'acpiview' shell command to build > > Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc | 19 +- > Platform/Marvell/Armada70x0Db/Armada70x0Db.dsc | 4 +- > Platform/Marvell/Armada80x0Db/Armada80x0Db.dsc | 4 +- > Platform/SolidRun/Armada80x0McBin/Armada80x0McBin.dsc | 4 +- > Silicon/Marvell/Armada7k8k/Armada7k8k.fdf | 5 + > Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db.inf | 1 + > Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db.inf | 1 + > Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin.inf | 1 + > Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciExpressLib/PciExpressLib.inf | 42 + > Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciHostBridgeLib/PciHostBridgeLib.inf | 52 + > Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db/Pcie.h | 26 + > Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db/Pcie.h | 26 + > Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Pcie.h | 26 + > Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciHostBridgeLib/PciHostBridgeLibConstructor.h | 95 ++ > Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.h | 6 + > Silicon/Marvell/Include/Library/ArmadaBoardDescLib.h | 46 + > Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h | 20 + > Silicon/Marvell/Include/Library/MvGpioLib.h | 1 + > Silicon/Marvell/Include/Protocol/BoardDesc.h | 22 + > Platform/Marvell/Armada70x0Db/Armada70x0DbBoardDescLib/Armada70x0DbBoardDescLib.c | 48 + > Platform/Marvell/Armada70x0Db/NonDiscoverableInitLib/NonDiscoverableInitLib.c | 4 + > Platform/Marvell/Armada80x0Db/Armada80x0DbBoardDescLib/Armada80x0DbBoardDescLib.c | 48 + > Platform/Marvell/Armada80x0Db/NonDiscoverableInitLib/NonDiscoverableInitLib.c | 6 + > Platform/SolidRun/Armada80x0McBin/Armada80x0McBinBoardDescLib/Armada80x0McBinBoardDescLib.c | 54 + > Platform/SolidRun/Armada80x0McBin/NonDiscoverableInitLib/NonDiscoverableInitLib.c | 1 + > Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciExpressLib/PciExpressLib.c | 1531 ++++++++++++++++++++ > Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciHostBridgeLib/PciHostBridgeLib.c | 265 ++++ > Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciHostBridgeLib/PciHostBridgeLibConstructor.c | 345 +++++ > Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.c | 44 + > Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.c | 86 ++ > Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db/Dsdt.asl | 108 ++ > Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db/Mcfg.aslc | 47 + > Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db/Dsdt.asl | 108 ++ > Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db/Mcfg.aslc | 47 + > Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Dsdt.asl | 108 ++ > Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Mcfg.aslc | 47 + > Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040-mcbin.dts | 3 + > 37 files changed, 3290 insertions(+), 11 deletions(-) > create mode 100644 Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciExpressLib/PciExpressLib.inf > create mode 100644 Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciHostBridgeLib/PciHostBridgeLib.inf > create mode 100644 Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db/Pcie.h > create mode 100644 Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db/Pcie.h > create mode 100644 Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Pcie.h > create mode 100644 Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciHostBridgeLib/PciHostBridgeLibConstructor.h > create mode 100644 Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciExpressLib/PciExpressLib.c > create mode 100644 Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciHostBridgeLib/PciHostBridgeLib.c > create mode 100644 Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciHostBridgeLib/PciHostBridgeLibConstructor.c > create mode 100644 Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db/Mcfg.aslc > create mode 100644 Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db/Mcfg.aslc > create mode 100644 Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Mcfg.aslc > > -- > 2.7.4 > -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. 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On Thu, May 23, 2019 at 03:27:47PM +0200, Mark Kettenis wrote: > > From: Marcin Wojtas <mw@semihalf.com> > > Date: Mon, 20 May 2019 17:27:13 +0200 > > > > Hi, > > > > Thank you for thorough review of v1. I submit second > > version of the Armada7k8k PCIE support. I addressed > > all comments. There is no functional change to initial > > patchset, but mostly clean-up and improvements - please > > refer to the changelog below. > > > > The patches are available in the github: > > https://github.com/MarvellEmbeddedProcessors/edk2-open-platform/commits/pcie-upstream-r20190520 > > > > I'm looking forward to your comments or remarks. > > > > Best regards, > > Marcin > > Tested this on my mcbin running OpenBSD. It incovers a small issue in > our kernel which I'm fixing. Otherwise this seems to work fine. > > So tested-by: Mark Kettenis <kettenis@openbsd.org> if that matters. Always helpful, thanks. Out of interest, what was the issue? Could I still expect the 6.5 installer to run on this hardware/firmware combo? Regards, Leif > Cheers, > > Mark > > > Changelog: > > v1->v2: > > *All > > - s/PcieBaseAddress/PcieDbiAdress/ > > > > *2/14 > > - fix alignment in comment > > > > * 3/14 > > - add CONST** to library callback > > > > * 4/14 > > - add missing reset GPIO to McBin description > > > > * 5/15 > > - add CONST** to protocol callback > > > > * 6/14 > > - cleanup all casting in file > > - use MAX_UINTx macros > > - add Linaro copyright > > - use MmioWrite8 instead of volatile in PciExpressReadBuffer > > - correct commient in IgnoreBusDeviceFunction () > > - fix typo in commit message > > > > * 7/10 > > - correct line endings > > - use temporary variable for memory description in PciHostBridgeResourceConflict > > - use MAX_UINTx macros > > - add comments around stalls and MemoryFence in GPIO reset > > - keep the reset active for 150ms > > - assign translation values instead of asserting > > > > *8/14 > > - assign gArmTokenSpaceGuid.PcdPciIoTranslation value in .dsc > > > > * 9-11/14 > > - correct line endings > > - remove unused methods > > - extend commit messages with 32k shift description > > > > Ard Biesheuvel (1): > > Marvell/Armada7k8k: Add PciExpressLib implementation > > > > Marcin Wojtas (13): > > Marvell/Library: MvGpioLib: Extend GPIO pin description > > Marvell/Library: ArmadaSoCDescLib: Add PCIE information > > Marvell/Library: ArmadaBoardDescLib: Add PCIE information > > Marvell/Armada7k8k: Extend board description libraries with PCIE > > Marvell/Armada7k8k: MvBoardDesc: Extend protocol with PCIE support > > Marvell/Armada7k8k: Implement PciHostBridgeLib > > Marvell/Armada7k8k: Enable PCIE support > > Marvell/Armada80x0McBin: Enable ACPI PCIE support > > Marvell/Armada80x0Db: Enable ACPI PCIE support > > Marvell/Armada70x0Db: Enable ACPI PCIE support > > Marvell/Armada80x0McBin: DeviceTree: Use pci-host-generic driver > > Marvell/Armada7k8k: Remove duplication in .dsc files > > Marvell/Armada7k8: Add 'acpiview' shell command to build > > > > Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc | 19 +- > > Platform/Marvell/Armada70x0Db/Armada70x0Db.dsc | 4 +- > > Platform/Marvell/Armada80x0Db/Armada80x0Db.dsc | 4 +- > > Platform/SolidRun/Armada80x0McBin/Armada80x0McBin.dsc | 4 +- > > Silicon/Marvell/Armada7k8k/Armada7k8k.fdf | 5 + > > Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db.inf | 1 + > > Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db.inf | 1 + > > Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin.inf | 1 + > > Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciExpressLib/PciExpressLib.inf | 42 + > > Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciHostBridgeLib/PciHostBridgeLib.inf | 52 + > > Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db/Pcie.h | 26 + > > Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db/Pcie.h | 26 + > > Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Pcie.h | 26 + > > Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciHostBridgeLib/PciHostBridgeLibConstructor.h | 95 ++ > > Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.h | 6 + > > Silicon/Marvell/Include/Library/ArmadaBoardDescLib.h | 46 + > > Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h | 20 + > > Silicon/Marvell/Include/Library/MvGpioLib.h | 1 + > > Silicon/Marvell/Include/Protocol/BoardDesc.h | 22 + > > Platform/Marvell/Armada70x0Db/Armada70x0DbBoardDescLib/Armada70x0DbBoardDescLib.c | 48 + > > Platform/Marvell/Armada70x0Db/NonDiscoverableInitLib/NonDiscoverableInitLib.c | 4 + > > Platform/Marvell/Armada80x0Db/Armada80x0DbBoardDescLib/Armada80x0DbBoardDescLib.c | 48 + > > Platform/Marvell/Armada80x0Db/NonDiscoverableInitLib/NonDiscoverableInitLib.c | 6 + > > Platform/SolidRun/Armada80x0McBin/Armada80x0McBinBoardDescLib/Armada80x0McBinBoardDescLib.c | 54 + > > Platform/SolidRun/Armada80x0McBin/NonDiscoverableInitLib/NonDiscoverableInitLib.c | 1 + > > Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciExpressLib/PciExpressLib.c | 1531 ++++++++++++++++++++ > > Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciHostBridgeLib/PciHostBridgeLib.c | 265 ++++ > > Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciHostBridgeLib/PciHostBridgeLibConstructor.c | 345 +++++ > > Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.c | 44 + > > Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.c | 86 ++ > > Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db/Dsdt.asl | 108 ++ > > Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db/Mcfg.aslc | 47 + > > Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db/Dsdt.asl | 108 ++ > > Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db/Mcfg.aslc | 47 + > > Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Dsdt.asl | 108 ++ > > Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Mcfg.aslc | 47 + > > Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040-mcbin.dts | 3 + > > 37 files changed, 3290 insertions(+), 11 deletions(-) > > create mode 100644 Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciExpressLib/PciExpressLib.inf > > create mode 100644 Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciHostBridgeLib/PciHostBridgeLib.inf > > create mode 100644 Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db/Pcie.h > > create mode 100644 Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db/Pcie.h > > create mode 100644 Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Pcie.h > > create mode 100644 Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciHostBridgeLib/PciHostBridgeLibConstructor.h > > create mode 100644 Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciExpressLib/PciExpressLib.c > > create mode 100644 Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciHostBridgeLib/PciHostBridgeLib.c > > create mode 100644 Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciHostBridgeLib/PciHostBridgeLibConstructor.c > > create mode 100644 Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db/Mcfg.aslc > > create mode 100644 Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db/Mcfg.aslc > > create mode 100644 Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Mcfg.aslc > > > > -- > > 2.7.4 > > -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. 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> Date: Thu, 23 May 2019 15:14:27 +0100 > From: Leif Lindholm <leif.lindholm@linaro.org> > > On Thu, May 23, 2019 at 03:27:47PM +0200, Mark Kettenis wrote: > > > From: Marcin Wojtas <mw@semihalf.com> > > > Date: Mon, 20 May 2019 17:27:13 +0200 > > > > > > Hi, > > > > > > Thank you for thorough review of v1. I submit second > > > version of the Armada7k8k PCIE support. I addressed > > > all comments. There is no functional change to initial > > > patchset, but mostly clean-up and improvements - please > > > refer to the changelog below. > > > > > > The patches are available in the github: > > > https://github.com/MarvellEmbeddedProcessors/edk2-open-platform/commits/pcie-upstream-r20190520 > > > > > > I'm looking forward to your comments or remarks. > > > > > > Best regards, > > > Marcin > > > > Tested this on my mcbin running OpenBSD. It incovers a small issue in > > our kernel which I'm fixing. Otherwise this seems to work fine. > > > > So tested-by: Mark Kettenis <kettenis@openbsd.org> if that matters. > > Always helpful, thanks. > > Out of interest, what was the issue? > Could I still expect the 6.5 installer to run on this > hardware/firmware combo? That should still work fine. The issue is with mapping PCI ROMS, which currently fails with the new firmware due to an oversight in the OpenBSD code. There are only a few OpenBSD drivers that attempt to map the PCI ROM. But one of those is radeondrm(4) and I stuck an AMD graphics card into the PCIe slot on my machine. There is a bit of a firmware angle to this though. The issue happens because the PCI ROM address register has been set to 0xfffe0000. All the writable address bits in the register are set to 1. While it is possible that the hardware comes up in that state, I suspect this is done by an attempt by the firmware to determine the size of the ROM that doesn't properly restore the original contents of the register. It may be related to the following messages that are printed by the firmware: Image type X64 can't be loaded on AARCH64 UEFI system. Unloading driver at 0x00000000000 Connect: PcieRoot(0x0)/Pci(0x0,0x0): Not Found Hmm, that's actually interesting. Maybe I should play with the X86 emulator that Ard added recently to see if that gives me a framebuffer console. Cheers, Mark > > Cheers, > > > > Mark > > > > > Changelog: > > > v1->v2: > > > *All > > > - s/PcieBaseAddress/PcieDbiAdress/ > > > > > > *2/14 > > > - fix alignment in comment > > > > > > * 3/14 > > > - add CONST** to library callback > > > > > > * 4/14 > > > - add missing reset GPIO to McBin description > > > > > > * 5/15 > > > - add CONST** to protocol callback > > > > > > * 6/14 > > > - cleanup all casting in file > > > - use MAX_UINTx macros > > > - add Linaro copyright > > > - use MmioWrite8 instead of volatile in PciExpressReadBuffer > > > - correct commient in IgnoreBusDeviceFunction () > > > - fix typo in commit message > > > > > > * 7/10 > > > - correct line endings > > > - use temporary variable for memory description in PciHostBridgeResourceConflict > > > - use MAX_UINTx macros > > > - add comments around stalls and MemoryFence in GPIO reset > > > - keep the reset active for 150ms > > > - assign translation values instead of asserting > > > > > > *8/14 > > > - assign gArmTokenSpaceGuid.PcdPciIoTranslation value in .dsc > > > > > > * 9-11/14 > > > - correct line endings > > > - remove unused methods > > > - extend commit messages with 32k shift description > > > > > > Ard Biesheuvel (1): > > > Marvell/Armada7k8k: Add PciExpressLib implementation > > > > > > Marcin Wojtas (13): > > > Marvell/Library: MvGpioLib: Extend GPIO pin description > > > Marvell/Library: ArmadaSoCDescLib: Add PCIE information > > > Marvell/Library: ArmadaBoardDescLib: Add PCIE information > > > Marvell/Armada7k8k: Extend board description libraries with PCIE > > > Marvell/Armada7k8k: MvBoardDesc: Extend protocol with PCIE support > > > Marvell/Armada7k8k: Implement PciHostBridgeLib > > > Marvell/Armada7k8k: Enable PCIE support > > > Marvell/Armada80x0McBin: Enable ACPI PCIE support > > > Marvell/Armada80x0Db: Enable ACPI PCIE support > > > Marvell/Armada70x0Db: Enable ACPI PCIE support > > > Marvell/Armada80x0McBin: DeviceTree: Use pci-host-generic driver > > > Marvell/Armada7k8k: Remove duplication in .dsc files > > > Marvell/Armada7k8: Add 'acpiview' shell command to build > > > > > > Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc | 19 +- > > > Platform/Marvell/Armada70x0Db/Armada70x0Db.dsc | 4 +- > > > Platform/Marvell/Armada80x0Db/Armada80x0Db.dsc | 4 +- > > > Platform/SolidRun/Armada80x0McBin/Armada80x0McBin.dsc | 4 +- > > > Silicon/Marvell/Armada7k8k/Armada7k8k.fdf | 5 + > > > Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db.inf | 1 + > > > Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db.inf | 1 + > > > Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin.inf | 1 + > > > Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciExpressLib/PciExpressLib.inf | 42 + > > > Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciHostBridgeLib/PciHostBridgeLib.inf | 52 + > > > Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db/Pcie.h | 26 + > > > Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db/Pcie.h | 26 + > > > Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Pcie.h | 26 + > > > Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciHostBridgeLib/PciHostBridgeLibConstructor.h | 95 ++ > > > Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.h | 6 + > > > Silicon/Marvell/Include/Library/ArmadaBoardDescLib.h | 46 + > > > Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h | 20 + > > > Silicon/Marvell/Include/Library/MvGpioLib.h | 1 + > > > Silicon/Marvell/Include/Protocol/BoardDesc.h | 22 + > > > Platform/Marvell/Armada70x0Db/Armada70x0DbBoardDescLib/Armada70x0DbBoardDescLib.c | 48 + > > > Platform/Marvell/Armada70x0Db/NonDiscoverableInitLib/NonDiscoverableInitLib.c | 4 + > > > Platform/Marvell/Armada80x0Db/Armada80x0DbBoardDescLib/Armada80x0DbBoardDescLib.c | 48 + > > > Platform/Marvell/Armada80x0Db/NonDiscoverableInitLib/NonDiscoverableInitLib.c | 6 + > > > Platform/SolidRun/Armada80x0McBin/Armada80x0McBinBoardDescLib/Armada80x0McBinBoardDescLib.c | 54 + > > > Platform/SolidRun/Armada80x0McBin/NonDiscoverableInitLib/NonDiscoverableInitLib.c | 1 + > > > Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciExpressLib/PciExpressLib.c | 1531 ++++++++++++++++++++ > > > Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciHostBridgeLib/PciHostBridgeLib.c | 265 ++++ > > > Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciHostBridgeLib/PciHostBridgeLibConstructor.c | 345 +++++ > > > Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.c | 44 + > > > Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.c | 86 ++ > > > Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db/Dsdt.asl | 108 ++ > > > Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db/Mcfg.aslc | 47 + > > > Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db/Dsdt.asl | 108 ++ > > > Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db/Mcfg.aslc | 47 + > > > Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Dsdt.asl | 108 ++ > > > Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Mcfg.aslc | 47 + > > > Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040-mcbin.dts | 3 + > > > 37 files changed, 3290 insertions(+), 11 deletions(-) > > > create mode 100644 Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciExpressLib/PciExpressLib.inf > > > create mode 100644 Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciHostBridgeLib/PciHostBridgeLib.inf > > > create mode 100644 Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db/Pcie.h > > > create mode 100644 Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db/Pcie.h > > > create mode 100644 Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Pcie.h > > > create mode 100644 Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciHostBridgeLib/PciHostBridgeLibConstructor.h > > > create mode 100644 Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciExpressLib/PciExpressLib.c > > > create mode 100644 Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciHostBridgeLib/PciHostBridgeLib.c > > > create mode 100644 Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciHostBridgeLib/PciHostBridgeLibConstructor.c > > > create mode 100644 Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db/Mcfg.aslc > > > create mode 100644 Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db/Mcfg.aslc > > > create mode 100644 Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Mcfg.aslc > > > > > > -- > > > 2.7.4 > > > > -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. 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On Thu, 23 May 2019 at 19:02, Mark Kettenis <kettenis@jive.eu> wrote: > > > Date: Thu, 23 May 2019 15:14:27 +0100 > > From: Leif Lindholm <leif.lindholm@linaro.org> > > > > On Thu, May 23, 2019 at 03:27:47PM +0200, Mark Kettenis wrote: > > > > From: Marcin Wojtas <mw@semihalf.com> > > > > Date: Mon, 20 May 2019 17:27:13 +0200 > > > > > > > > Hi, > > > > > > > > Thank you for thorough review of v1. I submit second > > > > version of the Armada7k8k PCIE support. I addressed > > > > all comments. There is no functional change to initial > > > > patchset, but mostly clean-up and improvements - please > > > > refer to the changelog below. > > > > > > > > The patches are available in the github: > > > > https://github.com/MarvellEmbeddedProcessors/edk2-open-platform/commits/pcie-upstream-r20190520 > > > > > > > > I'm looking forward to your comments or remarks. > > > > > > > > Best regards, > > > > Marcin > > > > > > Tested this on my mcbin running OpenBSD. It incovers a small issue in > > > our kernel which I'm fixing. Otherwise this seems to work fine. > > > > > > So tested-by: Mark Kettenis <kettenis@openbsd.org> if that matters. > > > > Always helpful, thanks. > > > > Out of interest, what was the issue? > > Could I still expect the 6.5 installer to run on this > > hardware/firmware combo? > > That should still work fine. > > The issue is with mapping PCI ROMS, which currently fails with the new > firmware due to an oversight in the OpenBSD code. There are only a > few OpenBSD drivers that attempt to map the PCI ROM. But one of those > is radeondrm(4) and I stuck an AMD graphics card into the PCIe slot on > my machine. > > There is a bit of a firmware angle to this though. The issue happens > because the PCI ROM address register has been set to 0xfffe0000. All > the writable address bits in the register are set to 1. While it is > possible that the hardware comes up in that state, I suspect this is > done by an attempt by the firmware to determine the size of the ROM > that doesn't properly restore the original contents of the register. UEFI deliberately leaves the ROM BARs unassigned, in order to avoid wasting valuable 32-bit PCI MMIO space. It enables the BAR temporarily to load the ROM, and dispatches it if it can. After that, it changes the BAR back to the old unassigned value. > It may be related to the following messages that are printed by the > firmware: > > Image type X64 can't be loaded on AARCH64 UEFI system. > Unloading driver at 0x00000000000 That address value is quite unexpected. > Connect: PcieRoot(0x0)/Pci(0x0,0x0): Not Found > > Hmm, that's actually interesting. Maybe I should play with the X86 > emulator that Ard added recently to see if that gives me a framebuffer > console. > Yes, if you add edk2-staging to your PACKAGES_PATH env variable, all you need to do is add -D X64EMU_ENABLE to the build command line. If you do end up testing this, could you please report back with the result, i.e., the type of card, PCI PID/VID and whether it all worked as expected? Thanks. -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#41292): https://edk2.groups.io/g/devel/message/41292 Mute This Topic: https://groups.io/mt/31686565/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=-=-=-=-=-=-=-=-=-=-=-
On Thu, May 23, 2019 at 07:13:20PM +0100, Ard Biesheuvel wrote:
> > Connect: PcieRoot(0x0)/Pci(0x0,0x0): Not Found
> >
> > Hmm, that's actually interesting. Maybe I should play with the X86
> > emulator that Ard added recently to see if that gives me a framebuffer
> > console.
> >
>
> Yes, if you add edk2-staging to your PACKAGES_PATH env variable, all
> you need to do is add -D X64EMU_ENABLE to the build command line.
You mean edk2-non-osi, right?
/
Leif
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On Thu, 23 May 2019 at 21:11, Leif Lindholm <leif.lindholm@linaro.org> wrote: > > On Thu, May 23, 2019 at 07:13:20PM +0100, Ard Biesheuvel wrote: > > > Connect: PcieRoot(0x0)/Pci(0x0,0x0): Not Found > > > > > > Hmm, that's actually interesting. Maybe I should play with the X86 > > > emulator that Ard added recently to see if that gives me a framebuffer > > > console. > > > > > > > Yes, if you add edk2-staging to your PACKAGES_PATH env variable, all > > you need to do is add -D X64EMU_ENABLE to the build command line. > > You mean edk2-non-osi, right? > Of course :-) -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#41295): https://edk2.groups.io/g/devel/message/41295 Mute This Topic: https://groups.io/mt/31686565/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=-=-=-=-=-=-=-=-=-=-=-
Hi Ard, czw., 23 maj 2019 o 22:24 Ard Biesheuvel <ard.biesheuvel@linaro.org> napisał(a): > > On Thu, 23 May 2019 at 21:11, Leif Lindholm <leif.lindholm@linaro.org> wrote: > > > > On Thu, May 23, 2019 at 07:13:20PM +0100, Ard Biesheuvel wrote: > > > > Connect: PcieRoot(0x0)/Pci(0x0,0x0): Not Found > > > > > > > > Hmm, that's actually interesting. Maybe I should play with the X86 > > > > emulator that Ard added recently to see if that gives me a framebuffer > > > > console. > > > > > > > > > > Yes, if you add edk2-staging to your PACKAGES_PATH env variable, all > > > you need to do is add -D X64EMU_ENABLE to the build command line. > > > > You mean edk2-non-osi, right? > > > > Of course :-) The video is not perfect (taken in Semihalf lab), but here's an output from GT630 directly from UEFI and your X64 emulation (thanks for it!): https://drive.google.com/file/d/1l8gyPI6boMtPaO89W7U9rn0ztQi_zrwZ/view Actually that may be first ever launch of it on this board :) Once the PCIe series gets merged, I'm considering some better footage booting to distro with GPU and promote a bit via my company's SM. Best regards, Marcin -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#41332): https://edk2.groups.io/g/devel/message/41332 Mute This Topic: https://groups.io/mt/31686565/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=-=-=-=-=-=-=-=-=-=-=-
On Fri, 24 May 2019 at 15:08, Marcin Wojtas <mw@semihalf.com> wrote: > > Hi Ard, > > czw., 23 maj 2019 o 22:24 Ard Biesheuvel <ard.biesheuvel@linaro.org> napisał(a): > > > > On Thu, 23 May 2019 at 21:11, Leif Lindholm <leif.lindholm@linaro.org> wrote: > > > > > > On Thu, May 23, 2019 at 07:13:20PM +0100, Ard Biesheuvel wrote: > > > > > Connect: PcieRoot(0x0)/Pci(0x0,0x0): Not Found > > > > > > > > > > Hmm, that's actually interesting. Maybe I should play with the X86 > > > > > emulator that Ard added recently to see if that gives me a framebuffer > > > > > console. > > > > > > > > > > > > > Yes, if you add edk2-staging to your PACKAGES_PATH env variable, all > > > > you need to do is add -D X64EMU_ENABLE to the build command line. > > > > > > You mean edk2-non-osi, right? > > > > > > > Of course :-) > > The video is not perfect (taken in Semihalf lab), but here's an output > from GT630 directly from UEFI and your X64 emulation (thanks for it!): > https://drive.google.com/file/d/1l8gyPI6boMtPaO89W7U9rn0ztQi_zrwZ/view Thanks! So GT630 is Nvidia Geforce, right? > Actually that may be first ever launch of it on this board :) Launch of what? The emulator? I've had that running on MacchiatoBin for years :-) > Once the > PCIe series gets merged, I'm considering some better footage booting > to distro with GPU and promote a bit via my company's SM. > > Best regards, > Marcin -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#41333): https://edk2.groups.io/g/devel/message/41333 Mute This Topic: https://groups.io/mt/31686565/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=-=-=-=-=-=-=-=-=-=-=-
pt., 24 maj 2019 o 15:12 Ard Biesheuvel <ard.biesheuvel@linaro.org> napisał(a): > > On Fri, 24 May 2019 at 15:08, Marcin Wojtas <mw@semihalf.com> wrote: > > > > Hi Ard, > > > > czw., 23 maj 2019 o 22:24 Ard Biesheuvel <ard.biesheuvel@linaro.org> napisał(a): > > > > > > On Thu, 23 May 2019 at 21:11, Leif Lindholm <leif.lindholm@linaro.org> wrote: > > > > > > > > On Thu, May 23, 2019 at 07:13:20PM +0100, Ard Biesheuvel wrote: > > > > > > Connect: PcieRoot(0x0)/Pci(0x0,0x0): Not Found > > > > > > > > > > > > Hmm, that's actually interesting. Maybe I should play with the X86 > > > > > > emulator that Ard added recently to see if that gives me a framebuffer > > > > > > console. > > > > > > > > > > > > > > > > Yes, if you add edk2-staging to your PACKAGES_PATH env variable, all > > > > > you need to do is add -D X64EMU_ENABLE to the build command line. > > > > > > > > You mean edk2-non-osi, right? > > > > > > > > > > Of course :-) > > > > The video is not perfect (taken in Semihalf lab), but here's an output > > from GT630 directly from UEFI and your X64 emulation (thanks for it!): > > https://drive.google.com/file/d/1l8gyPI6boMtPaO89W7U9rn0ztQi_zrwZ/view > > Thanks! So GT630 is Nvidia Geforce, right? Yes. > > > Actually that may be first ever launch of it on this board :) > > Launch of what? The emulator? I've had that running on MacchiatoBin > for years :-) > So first one on my board ;) Thanks, Marcin -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#41334): https://edk2.groups.io/g/devel/message/41334 Mute This Topic: https://groups.io/mt/31686565/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=-=-=-=-=-=-=-=-=-=-=-
> From: Ard Biesheuvel <ard.biesheuvel@linaro.org>
> Date: Thu, 23 May 2019 19:13:20 +0100
> Cc: Leif Lindholm <leif.lindholm@linaro.org>, Marcin Wojtas <mw@semihalf.com>,
> edk2-devel-groups-io <devel@edk2.groups.io>,
> Jan Dąbroś <jsd@semihalf.com>,
> Grzegorz Jaszczyk <jaz@semihalf.com>,
> Kostya Porotchkin <kostap@marvell.com>, Jici Gao <Jici.Gao@arm.com>,
> Rebecca Cran <rebecca@bluestop.org>, kettenis@openbsd.org
> Content-Type: text/plain; charset="UTF-8"
>
> On Thu, 23 May 2019 at 19:02, Mark Kettenis <kettenis@jive.eu> wrote:
> >
> > > Date: Thu, 23 May 2019 15:14:27 +0100
> > > From: Leif Lindholm <leif.lindholm@linaro.org>
> > >
> > > On Thu, May 23, 2019 at 03:27:47PM +0200, Mark Kettenis wrote:
> > > > > From: Marcin Wojtas <mw@semihalf.com>
> > > > > Date: Mon, 20 May 2019 17:27:13 +0200
> > > > >
> > > > > Hi,
> > > > >
> > > > > Thank you for thorough review of v1. I submit second
> > > > > version of the Armada7k8k PCIE support. I addressed
> > > > > all comments. There is no functional change to initial
> > > > > patchset, but mostly clean-up and improvements - please
> > > > > refer to the changelog below.
> > > > >
> > > > > The patches are available in the github:
> > > > > https://github.com/MarvellEmbeddedProcessors/edk2-open-platform/commits/pcie-upstream-r20190520
> > > > >
> > > > > I'm looking forward to your comments or remarks.
> > > > >
> > > > > Best regards,
> > > > > Marcin
> > > >
> > > > Tested this on my mcbin running OpenBSD. It incovers a small issue in
> > > > our kernel which I'm fixing. Otherwise this seems to work fine.
> > > >
> > > > So tested-by: Mark Kettenis <kettenis@openbsd.org> if that matters.
> > >
> > > Always helpful, thanks.
> > >
> > > Out of interest, what was the issue?
> > > Could I still expect the 6.5 installer to run on this
> > > hardware/firmware combo?
> >
> > That should still work fine.
> >
> > The issue is with mapping PCI ROMS, which currently fails with the new
> > firmware due to an oversight in the OpenBSD code. There are only a
> > few OpenBSD drivers that attempt to map the PCI ROM. But one of those
> > is radeondrm(4) and I stuck an AMD graphics card into the PCIe slot on
> > my machine.
> >
> > There is a bit of a firmware angle to this though. The issue happens
> > because the PCI ROM address register has been set to 0xfffe0000. All
> > the writable address bits in the register are set to 1. While it is
> > possible that the hardware comes up in that state, I suspect this is
> > done by an attempt by the firmware to determine the size of the ROM
> > that doesn't properly restore the original contents of the register.
>
> UEFI deliberately leaves the ROM BARs unassigned, in order to avoid
> wasting valuable 32-bit PCI MMIO space. It enables the BAR temporarily
> to load the ROM, and dispatches it if it can. After that, it changes
> the BAR back to the old unassigned value.
It seems that that last bit isn't working...
> > It may be related to the following messages that are printed by the
> > firmware:
> >
> > Image type X64 can't be loaded on AARCH64 UEFI system.
> > Unloading driver at 0x00000000000
>
> That address value is quite unexpected.
>
> > Connect: PcieRoot(0x0)/Pci(0x0,0x0): Not Found
> >
> > Hmm, that's actually interesting. Maybe I should play with the X86
> > emulator that Ard added recently to see if that gives me a framebuffer
> > console.
> >
>
> Yes, if you add edk2-staging to your PACKAGES_PATH env variable, all
> you need to do is add -D X64EMU_ENABLE to the build command line.
>
> If you do end up testing this, could you please report back with the
> result, i.e., the type of card, PCI PID/VID and whether it all worked
> as expected? Thanks.
Seems to work fine. The EFI shell and OpenBSD bootloader prompt show
up on both the framebuffer and the serial console. Here is a dmesg:
OpenBSD 6.5-current (GENERIC.MP) #2: Fri May 24 12:25:38 CEST 2019
kettenis@caldara.sibelius.xs4all.nl:/usr/src/sys/arch/arm64/compile/GENERIC.MP
real mem = 4095279104 (3905MB)
avail mem = 3936260096 (3753MB)
mainbus0 at root: ACPI
cpu0 at mainbus0 mpidr 0: ARM Cortex-A72 r0p1
cpu0: 48KB 64b/line 3-way L1 PIPT I-cache, 32KB 64b/line 2-way L1 D-cache
cpu0: 512KB 64b/line 16-way L2 cache
efi0 at mainbus0: UEFI 2.7
efi0: EDK II rev 0x10000
apm0 at mainbus0
psci0 at mainbus0: PSCI 1.1, SMCCC 1.1
ampintc0 at mainbus0 nirq 352, ncpu 4 ipi: 0, 1: "interrupt-controller"
ampintcmsi0 at ampintc0: nspi 32
ampintcmsi1 at ampintc0: nspi 32
ampintcmsi2 at ampintc0: nspi 32
ampintcmsi3 at ampintc0: nspi 32
agtimer0 at mainbus0: tick rate 25000 KHz
acpi0 at mainbus0: rev 2
acpi0: sleep states
acpi0: tables DSDT FACP MCFG GTDT APIC PPTT SPCR VFCT
acpi0: wakeup devices
acpimcfg0 at acpi0
acpimcfg0: addr 0xe0008000, bus 0-0
"ACPI0007" at acpi0 not configured
"ACPI0007" at acpi0 not configured
"ACPI0007" at acpi0 not configured
"ACPI0007" at acpi0 not configured
ahci0 at acpi0 AHC0 addr 0xf2540000/0x2000 irq 114: AHCI 1.0
scsibus0 at ahci0: 32 targets
ahci1 at acpi0 AHC1 addr 0xf4540000/0x2000 irq 338: AHCI 1.0
ahci1: port busy after first PMP probe FIS
ahci1: port busy after first PMP probe FIS
ahci1: port 1: 6.0Gb/s
scsibus1 at ahci1: 32 targets
sd0 at scsibus1 targ 1 lun 0: <ATA, Samsung SSD 850, EMT0> SCSI3 0/direct fixed naa.5002538d42110a27
sd0: 238475MB, 512 bytes/sector, 488397168 sectors, thin
xhci0 at acpi0 XHC0 addr 0xf2500000/0x4000 irq 113, xHCI 1.0
usb0 at xhci0: USB revision 3.0
uhub0 at usb0 configuration 1 interface 0 "Generic xHCI root hub" rev 3.00/1.00 addr 1
xhci1 at acpi0 XHC1 addr 0xf2510000/0x4000 irq 112, xHCI 1.0
usb1 at xhci1: USB revision 3.0
uhub1 at usb1 configuration 1 interface 0 "Generic xHCI root hub" rev 3.00/1.00 addr 1
xhci2 at acpi0 XHC2 addr 0xf4500000/0x4000 irq 337, xHCI 1.0
usb2 at xhci2: USB revision 3.0
uhub2 at usb2 configuration 1 interface 0 "Generic xHCI root hub" rev 3.00/1.00 addr 1
com0 at acpi0 COM1 addr 0xf0512000/0x100 irq 51: ns16550, no working fifo
com0: console
"MRVL0110" at acpi0 not configured
"MRVL0110" at acpi0 not configured
"PRP0001" at acpi0 not configured
"PRP0001" at acpi0 not configured
acpipci0 at acpi0 PCI0
pci0 at acpipci0
0:0:0: mem address conflict 0xfffe0000/0x20000
radeondrm0 at pci0 dev 0 function 0 "ATI Radeon HD 7450" rev 0x00
drm0 at radeondrm0
radeondrm0: msi
"ATI Radeon HD 6400 Audio" rev 0x00 at pci0 dev 0 function 1 not configured
"framebuffer" at mainbus0 not configured
cpu1 at mainbus0 mpidr 1: ARM Cortex-A72 r0p1
cpu1: 48KB 64b/line 3-way L1 PIPT I-cache, 32KB 64b/line 2-way L1 D-cache
cpu1: 512KB 64b/line 16-way L2 cache
cpu2 at mainbus0 mpidr 100: ARM Cortex-A72 r0p1
cpu2: 48KB 64b/line 3-way L1 PIPT I-cache, 32KB 64b/line 2-way L1 D-cache
cpu2: 512KB 64b/line 16-way L2 cache
cpu3 at mainbus0 mpidr 101: ARM Cortex-A72 r0p1
cpu3: 48KB 64b/line 3-way L1 PIPT I-cache, 32KB 64b/line 2-way L1 D-cache
cpu3: 512KB 64b/line 16-way L2 cache
cdce0 at uhub2 port 2 configuration 2 interface 0 "TP-LINK USB 10/100/1000 LAN" rev 2.10/30.00 addr 2
cdce0: address f4:f2:6d:18:1a:e2
vscsi0 at root
scsibus2 at vscsi0: 256 targets
softraid0 at root
scsibus3 at softraid0: 256 targets
bootfile: sd0a:/bsd
boot device: sd0
root on sd0a (8b9b61adc6331423.a) swap on sd0b dump on sd0b
initializing kernel modesetting (CAICOS 0x1002:0x677B 0x1043:0x3025 0x00).
radeondrm0: 1920x1080, 32bpp
wsdisplay0 at radeondrm0 mux 1
wsdisplay0: screen 0-5 added (std, vt100 emulation)
the
"framebuffer" at mainbus0 not configured
line comes up because radeondrm(4) takes over and kicks out the UEFI
framebuffer. If I disable radeondrm(4) I get:
...
pci0 at acpipci0
0:0:0: mem address conflict 0xfffe0000/0x20000
"ATI Radeon HD 7450" rev 0x00 at pci0 dev 0 function 0 not configured
"ATI Radeon HD 6400 Audio" rev 0x00 at pci0 dev 0 function 1 not configured
simplefb0 at mainbus0: 800x600, 32bpp
wsdisplay0 at simplefb0 mux 1
wsdisplay0: screen 0-5 added (std, vt100 emulation)
...
instead.
This is a Radeon R5 230 card; here is some basic PCI info:
Domain /dev/pci0:
0:0:0: ATI Radeon HD 7450
0x0000: Vendor ID: 1002, Product ID: 677b
0x0004: Command: 0007, Status: 0010
0x0008: Class: 03 Display, Subclass: 00 VGA,
Interface: 00, Revision: 00
0x000c: BIST: 00, Header Type: 80, Latency Timer: 00,
Cache Line Size: 00
0x0010: BAR mem prefetchable 64bit addr: 0x0000000800000000/0x10000000
0x0018: BAR mem 64bit addr: 0x0000000810000000/0x00020000
0x0020: BAR io addr: 0x00000000/0x0100
0x0024: BAR empty (00000000)
0x0028: Cardbus CIS: 00000000
0x002c: Subsystem Vendor ID: 1043 Product ID: 3025
0x0030: Expansion ROM Base Address: c0000000
0x0038: 00000000
0x003c: Interrupt Pin: 01 Line: ff Min Gnt: 00 Max Lat: 00
0x0050: Capability 0x01: Power Management
State: D0
0x0058: Capability 0x10: PCI Express
Link Speed: 5.0 / 5.0 GT/s, Link Width: x4 / x16
0x0100: Enhanced Capability 0x0b: Vendor-Specific
0x0150: Enhanced Capability 0x01: Advanced Error Reporting
0x00a0: Capability 0x05: Message Signalled Interrupts (MSI)
Enabled: yes
0:0:1: ATI Radeon HD 6400 Audio
0x0000: Vendor ID: 1002, Product ID: aa98
0x0004: Command: 0000, Status: 0010
0x0008: Class: 04 (unknown), Subclass: 03 (unknown),
Interface: 00, Revision: 00
0x000c: BIST: 00, Header Type: 80, Latency Timer: 00,
Cache Line Size: 00
0x0010: BAR mem 64bit addr: 0x0000000810020000/0x00004000
0x0018: BAR empty (00000000)
0x001c: BAR empty (00000000)
0x0020: BAR empty (00000000)
0x0024: BAR empty (00000000)
0x0028: Cardbus CIS: 00000000
0x002c: Subsystem Vendor ID: 1043 Product ID: aa98
0x0030: Expansion ROM Base Address: 00000000
0x0038: 00000000
0x003c: Interrupt Pin: 02 Line: ff Min Gnt: 00 Max Lat: 00
0x0050: Capability 0x01: Power Management
State: D0
0x0058: Capability 0x10: PCI Express
Link Speed: 5.0 / 5.0 GT/s, Link Width: x4 / x16
0x0100: Enhanced Capability 0x0b: Vendor-Specific
0x0150: Enhanced Capability 0x01: Advanced Error Reporting
0x00a0: Capability 0x05: Message Signalled Interrupts (MSI)
Enabled: no
X11 works to some extent, but there are artifacts. Half the
characters in my xterms are missing, and there are some random
characters in places where they shouldn't be. That may very well be
an OpenBSD issue though. Strangely enough 3D acceleration seems to
work fine.
Cheers,
Mark
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On Sat, 25 May 2019 at 00:16, Mark Kettenis <mark.kettenis@xs4all.nl> wrote: > > > From: Ard Biesheuvel <ard.biesheuvel@linaro.org> > > Date: Thu, 23 May 2019 19:13:20 +0100 > > Cc: Leif Lindholm <leif.lindholm@linaro.org>, Marcin Wojtas <mw@semihalf.com>, > > edk2-devel-groups-io <devel@edk2.groups.io>, > > Jan Dąbroś <jsd@semihalf.com>, > > Grzegorz Jaszczyk <jaz@semihalf.com>, > > Kostya Porotchkin <kostap@marvell.com>, Jici Gao <Jici.Gao@arm.com>, > > Rebecca Cran <rebecca@bluestop.org>, kettenis@openbsd.org > > Content-Type: text/plain; charset="UTF-8" > > > > On Thu, 23 May 2019 at 19:02, Mark Kettenis <kettenis@jive.eu> wrote: > > > > > > > Date: Thu, 23 May 2019 15:14:27 +0100 > > > > From: Leif Lindholm <leif.lindholm@linaro.org> > > > > > > > > On Thu, May 23, 2019 at 03:27:47PM +0200, Mark Kettenis wrote: > > > > > > From: Marcin Wojtas <mw@semihalf.com> > > > > > > Date: Mon, 20 May 2019 17:27:13 +0200 > > > > > > > > > > > > Hi, > > > > > > > > > > > > Thank you for thorough review of v1. I submit second > > > > > > version of the Armada7k8k PCIE support. I addressed > > > > > > all comments. There is no functional change to initial > > > > > > patchset, but mostly clean-up and improvements - please > > > > > > refer to the changelog below. > > > > > > > > > > > > The patches are available in the github: > > > > > > https://github.com/MarvellEmbeddedProcessors/edk2-open-platform/commits/pcie-upstream-r20190520 > > > > > > > > > > > > I'm looking forward to your comments or remarks. > > > > > > > > > > > > Best regards, > > > > > > Marcin > > > > > > > > > > Tested this on my mcbin running OpenBSD. It incovers a small issue in > > > > > our kernel which I'm fixing. Otherwise this seems to work fine. > > > > > > > > > > So tested-by: Mark Kettenis <kettenis@openbsd.org> if that matters. > > > > > > > > Always helpful, thanks. > > > > > > > > Out of interest, what was the issue? > > > > Could I still expect the 6.5 installer to run on this > > > > hardware/firmware combo? > > > > > > That should still work fine. > > > > > > The issue is with mapping PCI ROMS, which currently fails with the new > > > firmware due to an oversight in the OpenBSD code. There are only a > > > few OpenBSD drivers that attempt to map the PCI ROM. But one of those > > > is radeondrm(4) and I stuck an AMD graphics card into the PCIe slot on > > > my machine. > > > > > > There is a bit of a firmware angle to this though. The issue happens > > > because the PCI ROM address register has been set to 0xfffe0000. All > > > the writable address bits in the register are set to 1. While it is > > > possible that the hardware comes up in that state, I suspect this is > > > done by an attempt by the firmware to determine the size of the ROM > > > that doesn't properly restore the original contents of the register. > > > > UEFI deliberately leaves the ROM BARs unassigned, in order to avoid > > wasting valuable 32-bit PCI MMIO space. It enables the BAR temporarily > > to load the ROM, and dispatches it if it can. After that, it changes > > the BAR back to the old unassigned value. > > It seems that that last bit isn't working... > > > > It may be related to the following messages that are printed by the > > > firmware: > > > > > > Image type X64 can't be loaded on AARCH64 UEFI system. > > > Unloading driver at 0x00000000000 > > > > That address value is quite unexpected. > > > > > Connect: PcieRoot(0x0)/Pci(0x0,0x0): Not Found > > > > > > Hmm, that's actually interesting. Maybe I should play with the X86 > > > emulator that Ard added recently to see if that gives me a framebuffer > > > console. > > > > > > > Yes, if you add edk2-staging to your PACKAGES_PATH env variable, all > > you need to do is add -D X64EMU_ENABLE to the build command line. > > > > If you do end up testing this, could you please report back with the > > result, i.e., the type of card, PCI PID/VID and whether it all worked > > as expected? Thanks. > > Seems to work fine. The EFI shell and OpenBSD bootloader prompt show > up on both the framebuffer and the serial console. Thanks for the report. ... > X11 works to some extent, but there are artifacts. Half the > characters in my xterms are missing, and there are some random > characters in places where they shouldn't be. That may very well be > an OpenBSD issue though. Strangely enough 3D acceleration seems to > work fine. > This smells like a DMA coherency issue. I recently disabled an optimization in the linux version of the radeon/amdgpu drivers that resulted in similar issues: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=e02f5c1bb2283cfcee68f2f0feddcc06150f13aa -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#41372): https://edk2.groups.io/g/devel/message/41372 Mute This Topic: https://groups.io/mt/31686565/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=-=-=-=-=-=-=-=-=-=-=-
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