From: Wasim Khan <wasim.khan@nxp.com>
Add support of ArmPlatformLib for NXP LS2088ARDB board
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Wasim Khan <wasim.khan@nxp.com>
Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
---
.../Library/PlatformLib/ArmPlatformLib.c | 106 ++++++++++++
.../Library/PlatformLib/ArmPlatformLib.inf | 77 +++++++++
.../Library/PlatformLib/NxpQoriqLsHelper.S | 35 ++++
.../Library/PlatformLib/NxpQoriqLsMem.c | 189 +++++++++++++++++++++
4 files changed, 407 insertions(+)
create mode 100644 Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/ArmPlatformLib.c
create mode 100644 Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
create mode 100644 Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/NxpQoriqLsHelper.S
create mode 100644 Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c
diff --git a/Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/ArmPlatformLib.c b/Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/ArmPlatformLib.c
new file mode 100644
index 0000000..90f14ba
--- /dev/null
+++ b/Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/ArmPlatformLib.c
@@ -0,0 +1,106 @@
+/** ArmPlatformLib.c
+*
+* Contains board initialization functions.
+*
+* Based on BeagleBoardPkg/Library/BeagleBoardLib/BeagleBoard.c
+*
+* Copyright (c) 2011-2012, ARM Limited. All rights reserved.
+* Copyright (c) 2016, Freescale Semiconductor, Inc. All rights reserved.
+* Copyright 2017 NXP
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include <Library/ArmPlatformLib.h>
+#include <Ppi/ArmMpCoreInfo.h>
+
+extern VOID SocInit (VOID);
+
+/**
+ Return the current Boot Mode
+
+ This function returns the boot reason on the platform
+
+**/
+EFI_BOOT_MODE
+ArmPlatformGetBootMode (
+ VOID
+ )
+{
+ return BOOT_WITH_FULL_CONFIGURATION;
+}
+
+/**
+ Placeholder for Platform Initialization
+
+**/
+EFI_STATUS
+ArmPlatformInitialize (
+ IN UINTN MpId
+ )
+{
+ SocInit ();
+
+ return EFI_SUCCESS;
+}
+
+ARM_CORE_INFO LS2088aMpCoreInfoCTA72x4[] = {
+ {
+ // Cluster 0, Core 0
+ 0x0, 0x0,
+
+ // MP Core MailBox Set/Get/Clear Addresses and Clear Value
+ (EFI_PHYSICAL_ADDRESS)0,
+ (EFI_PHYSICAL_ADDRESS)0,
+ (EFI_PHYSICAL_ADDRESS)0,
+ (UINT64)0xFFFFFFFF
+ },
+};
+
+EFI_STATUS
+PrePeiCoreGetMpCoreInfo (
+ OUT UINTN *CoreCount,
+ OUT ARM_CORE_INFO **ArmCoreTable
+ )
+{
+ *CoreCount = sizeof (LS2088aMpCoreInfoCTA72x4) / sizeof (ARM_CORE_INFO);
+ *ArmCoreTable = LS2088aMpCoreInfoCTA72x4;
+
+ return EFI_SUCCESS;
+}
+
+ARM_MP_CORE_INFO_PPI mMpCoreInfoPpi = { PrePeiCoreGetMpCoreInfo };
+
+EFI_PEI_PPI_DESCRIPTOR gPlatformPpiTable[] = {
+ {
+ EFI_PEI_PPI_DESCRIPTOR_PPI,
+ &gArmMpCoreInfoPpiGuid,
+ &mMpCoreInfoPpi
+ }
+};
+
+VOID
+ArmPlatformGetPlatformPpiList (
+ OUT UINTN *PpiListSize,
+ OUT EFI_PEI_PPI_DESCRIPTOR **PpiList
+ )
+{
+ *PpiListSize = sizeof (gPlatformPpiTable);
+ *PpiList = gPlatformPpiTable;
+}
+
+
+UINTN
+ArmPlatformGetCorePosition (
+ IN UINTN MpId
+ )
+{
+ return 1;
+}
diff --git a/Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf b/Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
new file mode 100644
index 0000000..f5e5abd
--- /dev/null
+++ b/Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
@@ -0,0 +1,77 @@
+#/** @file
+#
+# Copyright (c) 2016, Freescale Semiconductor, Inc. All rights reserved.
+# Copyright 2017 NXP
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#**/
+
+[Defines]
+ INF_VERSION = 0x0001001A
+ BASE_NAME = PlatformLib
+ FILE_GUID = d1361285-8a47-421c-9efd-6b262c9093fc
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = ArmPlatformLib
+
+[Packages]
+ ArmPkg/ArmPkg.dec
+ ArmPlatformPkg/ArmPlatformPkg.dec
+ EmbeddedPkg/EmbeddedPkg.dec
+ MdePkg/MdePkg.dec
+ Silicon/NXP/NxpQoriqLs.dec
+
+[LibraryClasses]
+ ArmLib
+ SocLib
+
+[Sources.common]
+ ArmPlatformLib.c
+ NxpQoriqLsHelper.S | GCC
+ NxpQoriqLsMem.c
+
+
+[Ppis]
+ gArmMpCoreInfoPpiGuid
+
+[FixedPcd]
+ gArmTokenSpaceGuid.PcdArmPrimaryCore
+ gNxpQoriqLsTokenSpaceGuid.PcdCcsrBaseAddr
+ gNxpQoriqLsTokenSpaceGuid.PcdCcsrSize
+ gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1BaseAddr
+ gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1Size
+ gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2BaseAddr
+ gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2Size
+ gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionBaseAddr
+ gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionSize
+ gNxpQoriqLsTokenSpaceGuid.PcdQspiRegion2BaseAddr
+ gNxpQoriqLsTokenSpaceGuid.PcdQspiRegion2Size
+ gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseAddr
+ gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseSize
+ gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseAddr
+ gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseSize
+ gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseAddr
+ gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseSize
+ gNxpQoriqLsTokenSpaceGuid.PcdPciExp4BaseAddr
+ gNxpQoriqLsTokenSpaceGuid.PcdPciExp4BaseSize
+ gNxpQoriqLsTokenSpaceGuid.PcdDram1BaseAddr
+ gNxpQoriqLsTokenSpaceGuid.PcdDram1Size
+ gNxpQoriqLsTokenSpaceGuid.PcdDramMemSize
+ gNxpQoriqLsTokenSpaceGuid.PcdDram2BaseAddr
+ gNxpQoriqLsTokenSpaceGuid.PcdDram2Size
+ gNxpQoriqLsTokenSpaceGuid.PcdMcHighMemSupport
+ gNxpQoriqLsTokenSpaceGuid.PcdDpaa2McRamSize
+ gNxpQoriqLsTokenSpaceGuid.PcdDpaa2McPortalBaseAddr
+ gNxpQoriqLsTokenSpaceGuid.PcdDpaa2McPortalSize
+ gNxpQoriqLsTokenSpaceGuid.PcdDpaa2NiPortalsBaseAddr
+ gNxpQoriqLsTokenSpaceGuid.PcdDpaa2NiPortalsSize
+ gNxpQoriqLsTokenSpaceGuid.PcdDpaa2QBmanPortalsBaseAddr
+ gNxpQoriqLsTokenSpaceGuid.PcdDpaa2QBmanPortalSize
+ gNxpQoriqLsTokenSpaceGuid.PcdDpaa2QBmanPortalsCacheSize
+
diff --git a/Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/NxpQoriqLsHelper.S b/Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/NxpQoriqLsHelper.S
new file mode 100644
index 0000000..1917b02
--- /dev/null
+++ b/Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/NxpQoriqLsHelper.S
@@ -0,0 +1,35 @@
+#/** @file
+#
+# Copyright (c) 2012-2013, ARM Limited. All rights reserved.
+# Copyright 2017 NXP
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+#include <AsmMacroIoLibV8.h>
+#include <AutoGen.h>
+
+.text
+.align 2
+
+GCC_ASM_IMPORT(ArmReadMpidr)
+
+ASM_FUNC(ArmPlatformIsPrimaryCore)
+ tst x0, #3
+ cset x0, eq
+ ret
+
+ASM_FUNC(ArmPlatformPeiBootAction)
+ ret
+
+ASM_FUNC(ArmPlatformGetPrimaryCoreMpId)
+ MOV32 (x0, FixedPcdGet32(PcdArmPrimaryCore))
+ ldrh w0, [x0]
+ ret
diff --git a/Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c b/Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c
new file mode 100644
index 0000000..ccb49f6
--- /dev/null
+++ b/Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c
@@ -0,0 +1,189 @@
+/** NxpQoriqLsMem.c
+*
+* Board memory specific Library.
+*
+* Based on BeagleBoardPkg/Library/BeagleBoardLib/BeagleBoardMem.c
+*
+* Copyright (c) 2011, ARM Limited. All rights reserved.
+* Copyright (c) 2016, Freescale Semiconductor, Inc. All rights reserved.
+* Copyright 2017 NXP
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include <Library/ArmPlatformLib.h>
+#include <Library/DebugLib.h>
+#include <Library/PcdLib.h>
+#include <Library/MemoryAllocationLib.h>
+
+#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 25
+
+//
+// Calculate the MC (Management Complex) base address and DDR size based on
+// if the MC is loaded in DDR low memory region or in DDR high memory region.
+//
+#if FixedPcdGetBool (PcdMcHighMemSupport)
+#define DDR_MEM_SIZE FixedPcdGet64 (PcdDramMemSize) - FixedPcdGet64 (PcdDpaa2McRamSize)
+#define MC_BASE_ADDR FixedPcdGet64 (PcdDram2BaseAddr) + DDR_MEM_SIZE
+#else
+#define DDR_MEM_SIZE FixedPcdGet64 (PcdDramMemSize)
+#define MC_BASE_ADDR FixedPcdGet64 (PcdDram1BaseAddr) - FixedPcdGet64 (PcdDpaa2McRamSize)
+#endif
+
+
+/**
+ Return the Virtual Memory Map of your platform
+
+ This Virtual Memory Map is used by MemoryInitPei Module to initialize the MMU on your platform.
+
+ @param VirtualMemoryMap Array of ARM_MEMORY_REGION_DESCRIPTOR describing a Physical-to-
+ Virtual Memory mapping. This array must be ended by a zero-filled
+ entry
+
+**/
+
+VOID
+ArmPlatformGetVirtualMemoryMap (
+ IN ARM_MEMORY_REGION_DESCRIPTOR ** VirtualMemoryMap
+ )
+{
+ UINTN Index;
+ ARM_MEMORY_REGION_DESCRIPTOR *VirtualMemoryTable;
+
+ Index = 0;
+
+ ASSERT (VirtualMemoryMap != NULL);
+
+ VirtualMemoryTable = (ARM_MEMORY_REGION_DESCRIPTOR*)AllocatePages (
+ EFI_SIZE_TO_PAGES (sizeof (ARM_MEMORY_REGION_DESCRIPTOR) * MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS));
+
+ if (VirtualMemoryTable == NULL) {
+ return;
+ }
+
+ // DRAM1 (Must be 1st entry)
+ VirtualMemoryTable[Index].PhysicalBase = FixedPcdGet64 (PcdDram1BaseAddr);
+ VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdDram1BaseAddr);
+ VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdDram1Size);
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK ;
+
+ // CCSR Space
+ VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdCcsrBaseAddr);
+ VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdCcsrBaseAddr);
+ VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdCcsrSize);
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+
+ // IFC region 1
+ //
+ // A-009241 : Unaligned write transactions to IFC may result in corruption of data
+ // Affects : IFC
+ // Description: 16 byte unaligned write from system bus to IFC may result in extra unintended
+ // writes on external IFC interface that can corrupt data on external flash.
+ // Impact : Data corruption on external flash may happen in case of unaligned writes to
+ // IFC memory space.
+ // Workaround: Following are the workarounds:
+ // For write transactions from core, IFC interface memories (including IFC SRAM)
+ // should be configured as device type memory in MMU.
+ // For write transactions from non-core masters (like system DMA), the address
+ // should be 16 byte aligned and the data size should be multiple of 16 bytes.
+ //
+ VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdIfcRegion1BaseAddr);
+ VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdIfcRegion1BaseAddr);
+ VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdIfcRegion1Size);
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+
+ // IFC region 2
+ VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdIfcRegion2BaseAddr);
+ VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdIfcRegion2BaseAddr);
+ VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdIfcRegion2Size);
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+
+ // QSPI region 1
+ VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdQspiRegionBaseAddr);
+ VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdQspiRegionBaseAddr);
+ VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdQspiRegionSize);
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED;
+
+ // QSPI region 2
+ VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdQspiRegion2BaseAddr);
+ VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdQspiRegion2BaseAddr);
+ VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdQspiRegion2Size);
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED;
+
+ // DRAM2
+ VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdDram2BaseAddr);
+ VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdDram2BaseAddr);
+ VirtualMemoryTable[Index].Length = DDR_MEM_SIZE;
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK ;
+
+ // MC private DRAM
+ VirtualMemoryTable[++Index].PhysicalBase = MC_BASE_ADDR;
+ VirtualMemoryTable[Index].VirtualBase = MC_BASE_ADDR;
+ VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdDpaa2McRamSize);
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+
+ // PCIe1
+ VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdPciExp1BaseAddr);
+ VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdPciExp1BaseAddr);
+ VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdPciExp1BaseSize);
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+
+ // PCIe2
+ VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdPciExp2BaseAddr);
+ VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdPciExp2BaseAddr);
+ VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdPciExp2BaseSize);
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+
+ // PCIe3
+ VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdPciExp3BaseAddr);
+ VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdPciExp3BaseAddr);
+ VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdPciExp3BaseSize);
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+
+ // PCIe4
+ VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdPciExp4BaseAddr);
+ VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdPciExp4BaseAddr);
+ VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdPciExp4BaseSize);
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+
+ // DPAA2 MC Portals region
+ VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdDpaa2McPortalBaseAddr);
+ VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdDpaa2McPortalBaseAddr);
+ VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdDpaa2McPortalSize);
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+
+ // DPAA2 NI Portals region
+ VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdDpaa2NiPortalsBaseAddr);
+ VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdDpaa2NiPortalsBaseAddr);
+ VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdDpaa2NiPortalsSize);
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+
+ // DPAA2 QBMAN Portals - cache enabled region
+ VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdDpaa2QBmanPortalsBaseAddr);
+ VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdDpaa2QBmanPortalsBaseAddr);
+ VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdDpaa2QBmanPortalsCacheSize);
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK ;
+
+ // DPAA2 QBMAN Portals - cache inhibited region
+ VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdDpaa2QBmanPortalsBaseAddr) + FixedPcdGet64 (PcdDpaa2QBmanPortalsCacheSize);
+ VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdDpaa2QBmanPortalsBaseAddr) + FixedPcdGet64 (PcdDpaa2QBmanPortalsCacheSize);
+ VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdDpaa2QBmanPortalSize) - FixedPcdGet64 (PcdDpaa2QBmanPortalsCacheSize);
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+
+ // End of Table
+ VirtualMemoryTable[++Index].PhysicalBase = 0;
+ VirtualMemoryTable[Index].VirtualBase = 0;
+ VirtualMemoryTable[Index].Length = 0;
+ VirtualMemoryTable[Index].Attributes = (ARM_MEMORY_REGION_ATTRIBUTES)0;
+
+ ASSERT ((Index + 1) <= MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS);
+
+ *VirtualMemoryMap = VirtualMemoryTable;
+}
--
1.9.1
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On Fri, Feb 16, 2018 at 02:20:21PM +0530, Meenakshi wrote:
> From: Wasim Khan <wasim.khan@nxp.com>
>
> Add support of ArmPlatformLib for NXP LS2088ARDB board
>
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Wasim Khan <wasim.khan@nxp.com>
> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
> ---
> .../Library/PlatformLib/ArmPlatformLib.c | 106 ++++++++++++
> .../Library/PlatformLib/ArmPlatformLib.inf | 77 +++++++++
> .../Library/PlatformLib/NxpQoriqLsHelper.S | 35 ++++
> .../Library/PlatformLib/NxpQoriqLsMem.c | 189 +++++++++++++++++++++
> 4 files changed, 407 insertions(+)
> create mode 100644 Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/ArmPlatformLib.c
> create mode 100644 Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
> create mode 100644 Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/NxpQoriqLsHelper.S
> create mode 100644 Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c
>
> diff --git a/Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/ArmPlatformLib.c b/Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/ArmPlatformLib.c
> new file mode 100644
> index 0000000..90f14ba
> --- /dev/null
> +++ b/Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/ArmPlatformLib.c
> @@ -0,0 +1,106 @@
> +/** ArmPlatformLib.c
> +*
> +* Contains board initialization functions.
> +*
> +* Based on BeagleBoardPkg/Library/BeagleBoardLib/BeagleBoard.c
> +*
> +* Copyright (c) 2011-2012, ARM Limited. All rights reserved.
> +* Copyright (c) 2016, Freescale Semiconductor, Inc. All rights reserved.
> +* Copyright 2017 NXP
> +*
> +* This program and the accompanying materials
> +* are licensed and made available under the terms and conditions of the BSD License
> +* which accompanies this distribution. The full text of the license may be found at
> +* http://opensource.org/licenses/bsd-license.php
> +*
> +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +*
> +**/
> +
> +#include <Library/ArmPlatformLib.h>
> +#include <Ppi/ArmMpCoreInfo.h>
> +
> +extern VOID SocInit (VOID);
> +
> +/**
> + Return the current Boot Mode
> +
> + This function returns the boot reason on the platform
> +
> +**/
> +EFI_BOOT_MODE
> +ArmPlatformGetBootMode (
> + VOID
> + )
> +{
> + return BOOT_WITH_FULL_CONFIGURATION;
> +}
> +
> +/**
> + Placeholder for Platform Initialization
> +
> +**/
> +EFI_STATUS
> +ArmPlatformInitialize (
> + IN UINTN MpId
> + )
> +{
> + SocInit ();
> +
> + return EFI_SUCCESS;
> +}
> +
> +ARM_CORE_INFO LS2088aMpCoreInfoCTA72x4[] = {
> + {
> + // Cluster 0, Core 0
> + 0x0, 0x0,
> +
> + // MP Core MailBox Set/Get/Clear Addresses and Clear Value
> + (EFI_PHYSICAL_ADDRESS)0,
> + (EFI_PHYSICAL_ADDRESS)0,
> + (EFI_PHYSICAL_ADDRESS)0,
> + (UINT64)0xFFFFFFFF
> + },
> +};
> +
> +EFI_STATUS
> +PrePeiCoreGetMpCoreInfo (
> + OUT UINTN *CoreCount,
> + OUT ARM_CORE_INFO **ArmCoreTable
> + )
> +{
> + *CoreCount = sizeof (LS2088aMpCoreInfoCTA72x4) / sizeof (ARM_CORE_INFO);
> + *ArmCoreTable = LS2088aMpCoreInfoCTA72x4;
> +
> + return EFI_SUCCESS;
> +}
> +
> +ARM_MP_CORE_INFO_PPI mMpCoreInfoPpi = { PrePeiCoreGetMpCoreInfo };
> +
> +EFI_PEI_PPI_DESCRIPTOR gPlatformPpiTable[] = {
> + {
> + EFI_PEI_PPI_DESCRIPTOR_PPI,
> + &gArmMpCoreInfoPpiGuid,
> + &mMpCoreInfoPpi
> + }
> +};
> +
> +VOID
> +ArmPlatformGetPlatformPpiList (
> + OUT UINTN *PpiListSize,
> + OUT EFI_PEI_PPI_DESCRIPTOR **PpiList
> + )
> +{
> + *PpiListSize = sizeof (gPlatformPpiTable);
> + *PpiList = gPlatformPpiTable;
> +}
> +
> +
> +UINTN
> +ArmPlatformGetCorePosition (
> + IN UINTN MpId
> + )
> +{
> + return 1;
> +}
> diff --git a/Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf b/Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
> new file mode 100644
> index 0000000..f5e5abd
> --- /dev/null
> +++ b/Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
> @@ -0,0 +1,77 @@
> +#/** @file
> +#
> +# Copyright (c) 2016, Freescale Semiconductor, Inc. All rights reserved.
> +# Copyright 2017 NXP
> +#
> +# This program and the accompanying materials
> +# are licensed and made available under the terms and conditions of the BSD License
> +# which accompanies this distribution. The full text of the license may be found at
> +# http://opensource.org/licenses/bsd-license.php
> +#
> +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +#**/
> +
> +[Defines]
> + INF_VERSION = 0x0001001A
> + BASE_NAME = PlatformLib
> + FILE_GUID = d1361285-8a47-421c-9efd-6b262c9093fc
> + MODULE_TYPE = BASE
> + VERSION_STRING = 1.0
> + LIBRARY_CLASS = ArmPlatformLib
> +
> +[Packages]
> + ArmPkg/ArmPkg.dec
> + ArmPlatformPkg/ArmPlatformPkg.dec
> + EmbeddedPkg/EmbeddedPkg.dec
> + MdePkg/MdePkg.dec
> + Silicon/NXP/NxpQoriqLs.dec
> +
> +[LibraryClasses]
> + ArmLib
> + SocLib
> +
> +[Sources.common]
> + ArmPlatformLib.c
> + NxpQoriqLsHelper.S | GCC
> + NxpQoriqLsMem.c
> +
> +
> +[Ppis]
> + gArmMpCoreInfoPpiGuid
> +
> +[FixedPcd]
> + gArmTokenSpaceGuid.PcdArmPrimaryCore
> + gNxpQoriqLsTokenSpaceGuid.PcdCcsrBaseAddr
> + gNxpQoriqLsTokenSpaceGuid.PcdCcsrSize
> + gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1BaseAddr
> + gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1Size
> + gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2BaseAddr
> + gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2Size
> + gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionBaseAddr
> + gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionSize
> + gNxpQoriqLsTokenSpaceGuid.PcdQspiRegion2BaseAddr
> + gNxpQoriqLsTokenSpaceGuid.PcdQspiRegion2Size
> + gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseAddr
> + gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseSize
> + gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseAddr
> + gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseSize
> + gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseAddr
> + gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseSize
> + gNxpQoriqLsTokenSpaceGuid.PcdPciExp4BaseAddr
> + gNxpQoriqLsTokenSpaceGuid.PcdPciExp4BaseSize
> + gNxpQoriqLsTokenSpaceGuid.PcdDram1BaseAddr
> + gNxpQoriqLsTokenSpaceGuid.PcdDram1Size
> + gNxpQoriqLsTokenSpaceGuid.PcdDramMemSize
> + gNxpQoriqLsTokenSpaceGuid.PcdDram2BaseAddr
> + gNxpQoriqLsTokenSpaceGuid.PcdDram2Size
> + gNxpQoriqLsTokenSpaceGuid.PcdMcHighMemSupport
> + gNxpQoriqLsTokenSpaceGuid.PcdDpaa2McRamSize
> + gNxpQoriqLsTokenSpaceGuid.PcdDpaa2McPortalBaseAddr
> + gNxpQoriqLsTokenSpaceGuid.PcdDpaa2McPortalSize
> + gNxpQoriqLsTokenSpaceGuid.PcdDpaa2NiPortalsBaseAddr
> + gNxpQoriqLsTokenSpaceGuid.PcdDpaa2NiPortalsSize
> + gNxpQoriqLsTokenSpaceGuid.PcdDpaa2QBmanPortalsBaseAddr
> + gNxpQoriqLsTokenSpaceGuid.PcdDpaa2QBmanPortalSize
> + gNxpQoriqLsTokenSpaceGuid.PcdDpaa2QBmanPortalsCacheSize
> +
> diff --git a/Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/NxpQoriqLsHelper.S b/Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/NxpQoriqLsHelper.S
> new file mode 100644
> index 0000000..1917b02
> --- /dev/null
> +++ b/Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/NxpQoriqLsHelper.S
> @@ -0,0 +1,35 @@
> +#/** @file
> +#
> +# Copyright (c) 2012-2013, ARM Limited. All rights reserved.
> +# Copyright 2017 NXP
> +#
> +# This program and the accompanying materials
> +# are licensed and made available under the terms and conditions of the BSD License
> +# which accompanies this distribution. The full text of the license may be found at
> +# http://opensource.org/licenses/bsd-license.php
> +#
> +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +#
> +#**/
> +
> +#include <AsmMacroIoLibV8.h>
> +#include <AutoGen.h>
> +
> +.text
> +.align 2
> +
> +GCC_ASM_IMPORT(ArmReadMpidr)
> +
> +ASM_FUNC(ArmPlatformIsPrimaryCore)
> + tst x0, #3
> + cset x0, eq
> + ret
> +
> +ASM_FUNC(ArmPlatformPeiBootAction)
> + ret
> +
> +ASM_FUNC(ArmPlatformGetPrimaryCoreMpId)
> + MOV32 (x0, FixedPcdGet32(PcdArmPrimaryCore))
> + ldrh w0, [x0]
> + ret
> diff --git a/Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c b/Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c
> new file mode 100644
> index 0000000..ccb49f6
> --- /dev/null
> +++ b/Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c
> @@ -0,0 +1,189 @@
> +/** NxpQoriqLsMem.c
> +*
> +* Board memory specific Library.
> +*
> +* Based on BeagleBoardPkg/Library/BeagleBoardLib/BeagleBoardMem.c
> +*
> +* Copyright (c) 2011, ARM Limited. All rights reserved.
> +* Copyright (c) 2016, Freescale Semiconductor, Inc. All rights reserved.
> +* Copyright 2017 NXP
> +*
> +* This program and the accompanying materials
> +* are licensed and made available under the terms and conditions of the BSD License
> +* which accompanies this distribution. The full text of the license may be found at
> +* http://opensource.org/licenses/bsd-license.php
> +*
> +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +*
> +**/
> +
> +#include <Library/ArmPlatformLib.h>
> +#include <Library/DebugLib.h>
> +#include <Library/PcdLib.h>
> +#include <Library/MemoryAllocationLib.h>
> +
> +#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 25
> +
> +//
> +// Calculate the MC (Management Complex) base address and DDR size based on
> +// if the MC is loaded in DDR low memory region or in DDR high memory region.
> +//
> +#if FixedPcdGetBool (PcdMcHighMemSupport)
> +#define DDR_MEM_SIZE FixedPcdGet64 (PcdDramMemSize) - FixedPcdGet64 (PcdDpaa2McRamSize)
> +#define MC_BASE_ADDR FixedPcdGet64 (PcdDram2BaseAddr) + DDR_MEM_SIZE
> +#else
> +#define DDR_MEM_SIZE FixedPcdGet64 (PcdDramMemSize)
> +#define MC_BASE_ADDR FixedPcdGet64 (PcdDram1BaseAddr) - FixedPcdGet64 (PcdDpaa2McRamSize)
> +#endif
> +
> +
> +/**
> + Return the Virtual Memory Map of your platform
> +
> + This Virtual Memory Map is used by MemoryInitPei Module to initialize the MMU on your platform.
> +
> + @param VirtualMemoryMap Array of ARM_MEMORY_REGION_DESCRIPTOR describing a Physical-to-
> + Virtual Memory mapping. This array must be ended by a zero-filled
> + entry
> +
> +**/
> +
> +VOID
> +ArmPlatformGetVirtualMemoryMap (
> + IN ARM_MEMORY_REGION_DESCRIPTOR ** VirtualMemoryMap
> + )
> +{
> + UINTN Index;
> + ARM_MEMORY_REGION_DESCRIPTOR *VirtualMemoryTable;
> +
> + Index = 0;
> +
> + ASSERT (VirtualMemoryMap != NULL);
> +
> + VirtualMemoryTable = (ARM_MEMORY_REGION_DESCRIPTOR*)AllocatePages (
> + EFI_SIZE_TO_PAGES (sizeof (ARM_MEMORY_REGION_DESCRIPTOR) * MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS));
> +
> + if (VirtualMemoryTable == NULL) {
> + return;
> + }
> +
> + // DRAM1 (Must be 1st entry)
> + VirtualMemoryTable[Index].PhysicalBase = FixedPcdGet64 (PcdDram1BaseAddr);
> + VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdDram1BaseAddr);
> + VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdDram1Size);
> + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK ;
> +
> + // CCSR Space
> + VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdCcsrBaseAddr);
> + VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdCcsrBaseAddr);
> + VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdCcsrSize);
> + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
> +
> + // IFC region 1
> + //
> + // A-009241 : Unaligned write transactions to IFC may result in corruption of data
> + // Affects : IFC
> + // Description: 16 byte unaligned write from system bus to IFC may result in extra unintended
> + // writes on external IFC interface that can corrupt data on external flash.
> + // Impact : Data corruption on external flash may happen in case of unaligned writes to
> + // IFC memory space.
> + // Workaround: Following are the workarounds:
> + // For write transactions from core, IFC interface memories (including IFC SRAM)
> + // should be configured as device type memory in MMU.
> + // For write transactions from non-core masters (like system DMA), the address
> + // should be 16 byte aligned and the data size should be multiple of 16 bytes.
> + //
> + VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdIfcRegion1BaseAddr);
> + VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdIfcRegion1BaseAddr);
> + VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdIfcRegion1Size);
> + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
> +
> + // IFC region 2
> + VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdIfcRegion2BaseAddr);
> + VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdIfcRegion2BaseAddr);
> + VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdIfcRegion2Size);
> + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
> +
> + // QSPI region 1
> + VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdQspiRegionBaseAddr);
> + VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdQspiRegionBaseAddr);
> + VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdQspiRegionSize);
> + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED;
> +
> + // QSPI region 2
> + VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdQspiRegion2BaseAddr);
> + VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdQspiRegion2BaseAddr);
> + VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdQspiRegion2Size);
> + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED;
> +
> + // DRAM2
> + VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdDram2BaseAddr);
> + VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdDram2BaseAddr);
> + VirtualMemoryTable[Index].Length = DDR_MEM_SIZE;
> + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK ;
> +
> + // MC private DRAM
> + VirtualMemoryTable[++Index].PhysicalBase = MC_BASE_ADDR;
> + VirtualMemoryTable[Index].VirtualBase = MC_BASE_ADDR;
> + VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdDpaa2McRamSize);
> + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
> +
> + // PCIe1
> + VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdPciExp1BaseAddr);
> + VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdPciExp1BaseAddr);
> + VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdPciExp1BaseSize);
> + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
> +
> + // PCIe2
> + VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdPciExp2BaseAddr);
> + VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdPciExp2BaseAddr);
> + VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdPciExp2BaseSize);
> + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
> +
> + // PCIe3
> + VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdPciExp3BaseAddr);
> + VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdPciExp3BaseAddr);
> + VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdPciExp3BaseSize);
> + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
> +
> + // PCIe4
> + VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdPciExp4BaseAddr);
> + VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdPciExp4BaseAddr);
> + VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdPciExp4BaseSize);
> + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
> +
> + // DPAA2 MC Portals region
> + VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdDpaa2McPortalBaseAddr);
> + VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdDpaa2McPortalBaseAddr);
> + VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdDpaa2McPortalSize);
> + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
> +
> + // DPAA2 NI Portals region
> + VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdDpaa2NiPortalsBaseAddr);
> + VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdDpaa2NiPortalsBaseAddr);
> + VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdDpaa2NiPortalsSize);
> + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
> +
> + // DPAA2 QBMAN Portals - cache enabled region
> + VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdDpaa2QBmanPortalsBaseAddr);
> + VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdDpaa2QBmanPortalsBaseAddr);
> + VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdDpaa2QBmanPortalsCacheSize);
> + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK ;
> +
> + // DPAA2 QBMAN Portals - cache inhibited region
> + VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdDpaa2QBmanPortalsBaseAddr) + FixedPcdGet64 (PcdDpaa2QBmanPortalsCacheSize);
> + VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdDpaa2QBmanPortalsBaseAddr) + FixedPcdGet64 (PcdDpaa2QBmanPortalsCacheSize);
> + VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdDpaa2QBmanPortalSize) - FixedPcdGet64 (PcdDpaa2QBmanPortalsCacheSize);
> + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
> +
> + // End of Table
> + VirtualMemoryTable[++Index].PhysicalBase = 0;
> + VirtualMemoryTable[Index].VirtualBase = 0;
> + VirtualMemoryTable[Index].Length = 0;
> + VirtualMemoryTable[Index].Attributes = (ARM_MEMORY_REGION_ATTRIBUTES)0;
> +
> + ASSERT ((Index + 1) <= MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS);
> +
> + *VirtualMemoryMap = VirtualMemoryTable;
> +}
> --
> 1.9.1
>
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