From: Ming Huang <huangming23@huawei.com>

On D05 PCIe now, 2p NA PCIe2 and 2p NB PCIe0's pci domain addresses are
0x20000000 and 0x30000000 based. These addresses overlap with the DDR
memory range 0-1G. In this situation, on the inbound direction, our pcie
will drop the DDR address access that are located in the pci range window
and lead to a dataflow error.

Modify 2p NA PCIe2 and 2p NB PCIe0's pci domain addresses to 0x40000000
and decrease PciRegion Size accordingly.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ming Huang <huangming23@huawei.com>
Signed-off-by: Heyi Guo <heyi.guo@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
---
 Platform/Hisilicon/D05/D05.dsc                         | 12 ++++++------
 Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl |  8 ++++----
 2 files changed, 10 insertions(+), 10 deletions(-)

diff --git a/Platform/Hisilicon/D05/D05.dsc b/Platform/Hisilicon/D05/D05.dsc
index 01defe0..64101a7 100644
--- a/Platform/Hisilicon/D05/D05.dsc
+++ b/Platform/Hisilicon/D05/D05.dsc
@@ -329,12 +329,12 @@
   gHisiTokenSpaceGuid.PcdHb1Rb0PciRegionSize|0xbf0000
   gHisiTokenSpaceGuid.PcdHb1Rb1PciRegionBaseAddress|0x400a9400000
   gHisiTokenSpaceGuid.PcdHb1Rb1PciRegionSize|0xbf0000
-  gHisiTokenSpaceGuid.PcdHb1Rb2PciRegionBaseAddress|0x20000000
-  gHisiTokenSpaceGuid.PcdHb1Rb2PciRegionSize|0xd0000000
+  gHisiTokenSpaceGuid.PcdHb1Rb2PciRegionBaseAddress|0x40000000
+  gHisiTokenSpaceGuid.PcdHb1Rb2PciRegionSize|0xb0000000
   gHisiTokenSpaceGuid.PcdHb1Rb3PciRegionBaseAddress|0x400ab400000
   gHisiTokenSpaceGuid.PcdHb1Rb3PciRegionSize|0xbf0000
-  gHisiTokenSpaceGuid.PcdHb1Rb4PciRegionBaseAddress|0x30000000
-  gHisiTokenSpaceGuid.PcdHb1Rb4PciRegionSize|0xc0000000
+  gHisiTokenSpaceGuid.PcdHb1Rb4PciRegionBaseAddress|0x40000000
+  gHisiTokenSpaceGuid.PcdHb1Rb4PciRegionSize|0xb0000000
   gHisiTokenSpaceGuid.PcdHb1Rb5PciRegionBaseAddress|0x40000000
   gHisiTokenSpaceGuid.PcdHb1Rb5PciRegionSize|0xb0000000
   gHisiTokenSpaceGuid.PcdHb1Rb6PciRegionBaseAddress|0x408aa400000
@@ -352,9 +352,9 @@
   gHisiTokenSpaceGuid.PcdHb0Rb7CpuMemRegionBase|0x8B9800000
   gHisiTokenSpaceGuid.PcdHb1Rb0CpuMemRegionBase|0x400A8400000
   gHisiTokenSpaceGuid.PcdHb1Rb1CpuMemRegionBase|0x400A9400000
-  gHisiTokenSpaceGuid.PcdHb1Rb2CpuMemRegionBase|0x65020000000
+  gHisiTokenSpaceGuid.PcdHb1Rb2CpuMemRegionBase|0x65040000000
   gHisiTokenSpaceGuid.PcdHb1Rb3CpuMemRegionBase|0x400AB400000
-  gHisiTokenSpaceGuid.PcdHb1Rb4CpuMemRegionBase|0x75030000000
+  gHisiTokenSpaceGuid.PcdHb1Rb4CpuMemRegionBase|0x75040000000
   gHisiTokenSpaceGuid.PcdHb1Rb5CpuMemRegionBase|0x79040000000
   gHisiTokenSpaceGuid.PcdHb1Rb6CpuMemRegionBase|0x408AA400000
   gHisiTokenSpaceGuid.PcdHb1Rb7CpuMemRegionBase|0x408AB400000
diff --git a/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl b/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl
index 79267e5..55c7f50 100644
--- a/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl
+++ b/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl
@@ -646,10 +646,10 @@ Scope(_SB)
           Cacheable,
           ReadWrite,
           0x0, // Granularity
-          0x20000000, // Min Base Address
+          0x40000000, // Min Base Address
           0xefffffff, // Max Base Address
           0x65000000000, // Translate
-          0xd0000000 // Length
+          0xb0000000 // Length
         )
         QWordIO (
           ResourceProducer,
@@ -766,10 +766,10 @@ Scope(_SB)
           Cacheable,
           ReadWrite,
           0x0, // Granularity
-          0x30000000, // Min Base Address
+          0x40000000, // Min Base Address
           0xefffffff, // Max Base Address
           0x75000000000, // Translate
-          0xc0000000 // Length
+          0xb0000000 // Length
         )
         QWordIO (
           ResourceProducer,
-- 
1.9.1

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