Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Jeff Fan <jeff.fan@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Cc: Brijesh Singh <brijesh.singh@amd.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Leo Duran <leo.duran@amd.com>
---
UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c | 130 +++++++++++++++------
.../BaseXApicX2ApicLib/BaseXApicX2ApicLib.c | 130 +++++++++++++++------
2 files changed, 184 insertions(+), 76 deletions(-)
mode change 100644 => 100755 UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c
diff --git a/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c b/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c
old mode 100644
new mode 100755
index f81bbb2..02dfabc
--- a/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c
+++ b/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c
@@ -4,6 +4,8 @@
This local APIC library instance supports xAPIC mode only.
Copyright (c) 2010 - 2016, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2017, AMD Inc. All rights reserved.<BR>
+
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@@ -15,6 +17,7 @@
**/
#include <Register/Cpuid.h>
+#include <Register/Amd/Cpuid.h>
#include <Register/Msr.h>
#include <Register/LocalApic.h>
@@ -966,20 +969,29 @@ GetProcessorLocationByApicId (
OUT UINT32 *Thread OPTIONAL
)
{
- BOOLEAN TopologyLeafSupported;
- UINTN ThreadBits;
- UINTN CoreBits;
- CPUID_VERSION_INFO_EBX VersionInfoEbx;
- CPUID_VERSION_INFO_EDX VersionInfoEdx;
- CPUID_CACHE_PARAMS_EAX CacheParamsEax;
- CPUID_EXTENDED_TOPOLOGY_EAX ExtendedTopologyEax;
- CPUID_EXTENDED_TOPOLOGY_EBX ExtendedTopologyEbx;
- CPUID_EXTENDED_TOPOLOGY_ECX ExtendedTopologyEcx;
- UINT32 MaxCpuIdIndex;
- UINT32 SubIndex;
- UINTN LevelType;
- UINT32 MaxLogicProcessorsPerPackage;
- UINT32 MaxCoresPerPackage;
+ CPUID_VERSION_INFO_EBX VersionInfoEbx;
+ CPUID_VERSION_INFO_EDX VersionInfoEdx;
+ CPUID_CACHE_PARAMS_EAX CacheParamsEax;
+ CPUID_EXTENDED_TOPOLOGY_EAX ExtendedTopologyEax;
+ CPUID_EXTENDED_TOPOLOGY_EBX ExtendedTopologyEbx;
+ CPUID_EXTENDED_TOPOLOGY_ECX ExtendedTopologyEcx;
+ CPUID_AMD_EXTENDED_CPU_SIG_ECX AmdExtendedCpuSigEcx;
+ CPUID_AMD_PROCESSOR_TOPOLOGY_EBX AmdProcessorTopologyEbx;
+ CPUID_AMD_PROCESSOR_TOPOLOGY_ECX AmdProcessorTopologyEcx;
+ CPUID_AMD_VIR_PHY_ADDRESS_SIZE_ECX AmdVirPhyAddressSizeEcx;
+ UINT32 MaxStandardCpuIdIndex;
+ UINT32 MaxExtendedCpuIdIndex;
+ UINT32 SubIndex;
+ UINTN LevelType;
+ UINT32 MaxLogicProcessorsPerPackage;
+ UINT32 MaxCoresPerPackage;
+ UINT32 MaxThreadPerPackageMask;
+ UINT32 ActualThreadPerPackageMask;
+ UINT32 MaxCoresPerNode;
+ UINT32 CorePerNodeMask;
+ UINT32 ApicIdShift;
+ UINTN ThreadBits;
+ UINTN CoreBits;
//
// Check if the processor is capable of supporting more than one logical processor.
@@ -987,10 +999,10 @@ GetProcessorLocationByApicId (
AsmCpuid(CPUID_VERSION_INFO, NULL, NULL, NULL, &VersionInfoEdx.Uint32);
if (VersionInfoEdx.Bits.HTT == 0) {
if (Thread != NULL) {
- *Thread = 0;
+ *Thread = 0;
}
if (Core != NULL) {
- *Core = 0;
+ *Core = 0;
}
if (Package != NULL) {
*Package = 0;
@@ -1002,20 +1014,16 @@ GetProcessorLocationByApicId (
CoreBits = 0;
//
- // Assume three-level mapping of APIC ID: Package:Core:SMT.
+ // Get the max index of CPUID
//
- TopologyLeafSupported = FALSE;
-
- //
- // Get the max index of basic CPUID
- //
- AsmCpuid(CPUID_SIGNATURE, &MaxCpuIdIndex, NULL, NULL, NULL);
+ AsmCpuid(CPUID_SIGNATURE, &MaxStandardCpuIdIndex, NULL, NULL, NULL);
+ AsmCpuid(CPUID_EXTENDED_FUNCTION, &MaxExtendedCpuIdIndex, NULL, NULL, NULL);
//
// If the extended topology enumeration leaf is available, it
// is the preferred mechanism for enumerating topology.
//
- if (MaxCpuIdIndex >= CPUID_EXTENDED_TOPOLOGY) {
+ if (MaxStandardCpuIdIndex >= CPUID_EXTENDED_TOPOLOGY) {
AsmCpuidEx(
CPUID_EXTENDED_TOPOLOGY,
0,
@@ -1030,8 +1038,6 @@ GetProcessorLocationByApicId (
// supported on that processor.
//
if (ExtendedTopologyEbx.Uint32 != 0) {
- TopologyLeafSupported = TRUE;
-
//
// Sub-leaf index 0 (ECX= 0 as input) provides enumeration parameters to extract
// the SMT sub-field of x2APIC ID.
@@ -1061,31 +1067,79 @@ GetProcessorLocationByApicId (
}
SubIndex++;
} while (LevelType != CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID);
+ goto GetLocation;
}
}
- if (!TopologyLeafSupported) {
- AsmCpuid(CPUID_VERSION_INFO, NULL, &VersionInfoEbx.Uint32, NULL, NULL);
- MaxLogicProcessorsPerPackage = VersionInfoEbx.Bits.MaximumAddressableIdsForLogicalProcessors;
- if (MaxCpuIdIndex >= CPUID_CACHE_PARAMS) {
- AsmCpuidEx(CPUID_CACHE_PARAMS, 0, &CacheParamsEax.Uint32, NULL, NULL, NULL);
+ AsmCpuid(CPUID_VERSION_INFO, NULL, &VersionInfoEbx.Uint32, NULL, NULL);
+ MaxLogicProcessorsPerPackage = VersionInfoEbx.Bits.MaximumAddressableIdsForLogicalProcessors;
+
+ if (MaxStandardCpuIdIndex >= CPUID_CACHE_PARAMS) {
+ AsmCpuidEx(CPUID_CACHE_PARAMS, 0, &CacheParamsEax.Uint32, NULL, NULL, NULL);
+ if (CacheParamsEax.Uint32 != 0) {
MaxCoresPerPackage = CacheParamsEax.Bits.MaximumAddressableIdsForLogicalProcessors + 1;
+ goto GetBits;
}
- else {
+ }
+
+ if (MaxExtendedCpuIdIndex >= CPUID_AMD_PROCESSOR_TOPOLOGY) {
+ AsmCpuid(CPUID_EXTENDED_CPU_SIG, NULL, NULL, &AmdExtendedCpuSigEcx.Uint32, NULL);
+ if (AmdExtendedCpuSigEcx.Bits.TopologyExtensions != 0) {
+ AsmCpuid(CPUID_AMD_PROCESSOR_TOPOLOGY, NULL, &AmdProcessorTopologyEbx.Uint32,
+ &AmdProcessorTopologyEcx.Uint32, NULL);
+
+ MaxCoresPerPackage = MaxLogicProcessorsPerPackage / (AmdProcessorTopologyEbx.Bits.ThreadsPerCore + 1);
+
//
- // Must be a single-core processor.
+ // Account for actual thread count (e.g., SMT disabled)
//
- MaxCoresPerPackage = 1;
+ AsmCpuid(CPUID_VIR_PHY_ADDRESS_SIZE, NULL, NULL, &AmdVirPhyAddressSizeEcx.Uint32, NULL);
+ MaxThreadPerPackageMask = 1 << AmdVirPhyAddressSizeEcx.Bits.ApicIdCoreIdSize;
+ ActualThreadPerPackageMask = 1;
+ while (ActualThreadPerPackageMask < MaxLogicProcessorsPerPackage) {
+ ActualThreadPerPackageMask <<= 1;
+ }
+
+ if (ActualThreadPerPackageMask < MaxThreadPerPackageMask) {
+ MaxCoresPerNode = MaxCoresPerPackage / (AmdProcessorTopologyEcx.Bits.NodesPerProcessor + 1);
+
+ CorePerNodeMask = 1;
+ while (CorePerNodeMask < MaxCoresPerNode) {
+ CorePerNodeMask <<= 1;
+ }
+ CorePerNodeMask -= 1;
+
+ ApicIdShift = 0;
+ do {
+ ApicIdShift += 1;
+ ActualThreadPerPackageMask <<= 1;
+ } while (ActualThreadPerPackageMask < MaxThreadPerPackageMask);
+
+ //
+ // Adjust APIC Id to report concatenation of Package|Core|Thread.
+ //
+ InitialApicId = ((InitialApicId & ~CorePerNodeMask) >> ApicIdShift) | (InitialApicId & CorePerNodeMask);
+ }
+
+ goto GetBits;
}
+ }
+
+ //
+ // Must be a single-core processor.
+ //
+ MaxCoresPerPackage = 1;
- ThreadBits = (UINTN)(HighBitSet32(MaxLogicProcessorsPerPackage / MaxCoresPerPackage - 1) + 1);
- CoreBits = (UINTN)(HighBitSet32(MaxCoresPerPackage - 1) + 1); }
+GetBits:
+ ThreadBits = (UINTN)(HighBitSet32(MaxLogicProcessorsPerPackage / MaxCoresPerPackage - 1) + 1);
+ CoreBits = (UINTN)(HighBitSet32(MaxCoresPerPackage - 1) + 1);
+GetLocation:
if (Thread != NULL) {
- *Thread = InitialApicId & ((1 << ThreadBits) - 1);
+ *Thread = InitialApicId & ((1 << ThreadBits) - 1);
}
if (Core != NULL) {
- *Core = (InitialApicId >> ThreadBits) & ((1 << CoreBits) - 1);
+ *Core = (InitialApicId >> ThreadBits) & ((1 << CoreBits) - 1);
}
if (Package != NULL) {
*Package = (InitialApicId >> (ThreadBits + CoreBits));
diff --git a/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c b/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c
index e690d2a..726e1e0 100644
--- a/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c
+++ b/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c
@@ -5,6 +5,8 @@
which have xAPIC and x2APIC modes.
Copyright (c) 2010 - 2016, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2017, AMD Inc. All rights reserved.<BR>
+
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@@ -16,6 +18,7 @@
**/
#include <Register/Cpuid.h>
+#include <Register/Amd/Cpuid.h>
#include <Register/Msr.h>
#include <Register/LocalApic.h>
@@ -1061,20 +1064,29 @@ GetProcessorLocationByApicId (
OUT UINT32 *Thread OPTIONAL
)
{
- BOOLEAN TopologyLeafSupported;
- UINTN ThreadBits;
- UINTN CoreBits;
- CPUID_VERSION_INFO_EBX VersionInfoEbx;
- CPUID_VERSION_INFO_EDX VersionInfoEdx;
- CPUID_CACHE_PARAMS_EAX CacheParamsEax;
- CPUID_EXTENDED_TOPOLOGY_EAX ExtendedTopologyEax;
- CPUID_EXTENDED_TOPOLOGY_EBX ExtendedTopologyEbx;
- CPUID_EXTENDED_TOPOLOGY_ECX ExtendedTopologyEcx;
- UINT32 MaxCpuIdIndex;
- UINT32 SubIndex;
- UINTN LevelType;
- UINT32 MaxLogicProcessorsPerPackage;
- UINT32 MaxCoresPerPackage;
+ CPUID_VERSION_INFO_EBX VersionInfoEbx;
+ CPUID_VERSION_INFO_EDX VersionInfoEdx;
+ CPUID_CACHE_PARAMS_EAX CacheParamsEax;
+ CPUID_EXTENDED_TOPOLOGY_EAX ExtendedTopologyEax;
+ CPUID_EXTENDED_TOPOLOGY_EBX ExtendedTopologyEbx;
+ CPUID_EXTENDED_TOPOLOGY_ECX ExtendedTopologyEcx;
+ CPUID_AMD_EXTENDED_CPU_SIG_ECX AmdExtendedCpuSigEcx;
+ CPUID_AMD_PROCESSOR_TOPOLOGY_EBX AmdProcessorTopologyEbx;
+ CPUID_AMD_PROCESSOR_TOPOLOGY_ECX AmdProcessorTopologyEcx;
+ CPUID_AMD_VIR_PHY_ADDRESS_SIZE_ECX AmdVirPhyAddressSizeEcx;
+ UINT32 MaxStandardCpuIdIndex;
+ UINT32 MaxExtendedCpuIdIndex;
+ UINT32 SubIndex;
+ UINTN LevelType;
+ UINT32 MaxLogicProcessorsPerPackage;
+ UINT32 MaxCoresPerPackage;
+ UINT32 MaxThreadPerPackageMask;
+ UINT32 ActualThreadPerPackageMask;
+ UINT32 MaxCoresPerNode;
+ UINT32 CorePerNodeMask;
+ UINT32 ApicIdShift;
+ UINTN ThreadBits;
+ UINTN CoreBits;
//
// Check if the processor is capable of supporting more than one logical processor.
@@ -1082,10 +1094,10 @@ GetProcessorLocationByApicId (
AsmCpuid(CPUID_VERSION_INFO, NULL, NULL, NULL, &VersionInfoEdx.Uint32);
if (VersionInfoEdx.Bits.HTT == 0) {
if (Thread != NULL) {
- *Thread = 0;
+ *Thread = 0;
}
if (Core != NULL) {
- *Core = 0;
+ *Core = 0;
}
if (Package != NULL) {
*Package = 0;
@@ -1097,20 +1109,16 @@ GetProcessorLocationByApicId (
CoreBits = 0;
//
- // Assume three-level mapping of APIC ID: Package:Core:SMT.
+ // Get the max index of CPUID
//
- TopologyLeafSupported = FALSE;
-
- //
- // Get the max index of basic CPUID
- //
- AsmCpuid(CPUID_SIGNATURE, &MaxCpuIdIndex, NULL, NULL, NULL);
+ AsmCpuid(CPUID_SIGNATURE, &MaxStandardCpuIdIndex, NULL, NULL, NULL);
+ AsmCpuid(CPUID_EXTENDED_FUNCTION, &MaxExtendedCpuIdIndex, NULL, NULL, NULL);
//
// If the extended topology enumeration leaf is available, it
// is the preferred mechanism for enumerating topology.
//
- if (MaxCpuIdIndex >= CPUID_EXTENDED_TOPOLOGY) {
+ if (MaxStandardCpuIdIndex >= CPUID_EXTENDED_TOPOLOGY) {
AsmCpuidEx(
CPUID_EXTENDED_TOPOLOGY,
0,
@@ -1125,8 +1133,6 @@ GetProcessorLocationByApicId (
// supported on that processor.
//
if (ExtendedTopologyEbx.Uint32 != 0) {
- TopologyLeafSupported = TRUE;
-
//
// Sub-leaf index 0 (ECX= 0 as input) provides enumeration parameters to extract
// the SMT sub-field of x2APIC ID.
@@ -1156,31 +1162,79 @@ GetProcessorLocationByApicId (
}
SubIndex++;
} while (LevelType != CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID);
+ goto GetLocation;
}
}
- if (!TopologyLeafSupported) {
- AsmCpuid(CPUID_VERSION_INFO, NULL, &VersionInfoEbx.Uint32, NULL, NULL);
- MaxLogicProcessorsPerPackage = VersionInfoEbx.Bits.MaximumAddressableIdsForLogicalProcessors;
- if (MaxCpuIdIndex >= CPUID_CACHE_PARAMS) {
- AsmCpuidEx(CPUID_CACHE_PARAMS, 0, &CacheParamsEax.Uint32, NULL, NULL, NULL);
+ AsmCpuid(CPUID_VERSION_INFO, NULL, &VersionInfoEbx.Uint32, NULL, NULL);
+ MaxLogicProcessorsPerPackage = VersionInfoEbx.Bits.MaximumAddressableIdsForLogicalProcessors;
+
+ if (MaxStandardCpuIdIndex >= CPUID_CACHE_PARAMS) {
+ AsmCpuidEx(CPUID_CACHE_PARAMS, 0, &CacheParamsEax.Uint32, NULL, NULL, NULL);
+ if (CacheParamsEax.Uint32 != 0) {
MaxCoresPerPackage = CacheParamsEax.Bits.MaximumAddressableIdsForLogicalProcessors + 1;
+ goto GetBits;
}
- else {
+ }
+
+ if (MaxExtendedCpuIdIndex >= CPUID_AMD_PROCESSOR_TOPOLOGY) {
+ AsmCpuid(CPUID_EXTENDED_CPU_SIG, NULL, NULL, &AmdExtendedCpuSigEcx.Uint32, NULL);
+ if (AmdExtendedCpuSigEcx.Bits.TopologyExtensions != 0) {
+ AsmCpuid(CPUID_AMD_PROCESSOR_TOPOLOGY, NULL, &AmdProcessorTopologyEbx.Uint32,
+ &AmdProcessorTopologyEcx.Uint32, NULL);
+
+ MaxCoresPerPackage = MaxLogicProcessorsPerPackage / (AmdProcessorTopologyEbx.Bits.ThreadsPerCore + 1);
+
//
- // Must be a single-core processor.
+ // Account for actual thread count (e.g., SMT disabled)
//
- MaxCoresPerPackage = 1;
+ AsmCpuid(CPUID_VIR_PHY_ADDRESS_SIZE, NULL, NULL, &AmdVirPhyAddressSizeEcx.Uint32, NULL);
+ MaxThreadPerPackageMask = 1 << AmdVirPhyAddressSizeEcx.Bits.ApicIdCoreIdSize;
+ ActualThreadPerPackageMask = 1;
+ while (ActualThreadPerPackageMask < MaxLogicProcessorsPerPackage) {
+ ActualThreadPerPackageMask <<= 1;
+ }
+
+ if (ActualThreadPerPackageMask < MaxThreadPerPackageMask) {
+ MaxCoresPerNode = MaxCoresPerPackage / (AmdProcessorTopologyEcx.Bits.NodesPerProcessor + 1);
+
+ CorePerNodeMask = 1;
+ while (CorePerNodeMask < MaxCoresPerNode) {
+ CorePerNodeMask <<= 1;
+ }
+ CorePerNodeMask -= 1;
+
+ ApicIdShift = 0;
+ do {
+ ApicIdShift += 1;
+ ActualThreadPerPackageMask <<= 1;
+ } while (ActualThreadPerPackageMask < MaxThreadPerPackageMask);
+
+ //
+ // Adjust APIC Id to report concatenation of Package|Core|Thread.
+ //
+ InitialApicId = ((InitialApicId & ~CorePerNodeMask) >> ApicIdShift) | (InitialApicId & CorePerNodeMask);
+ }
+
+ goto GetBits;
}
+ }
+
+ //
+ // Must be a single-core processor.
+ //
+ MaxCoresPerPackage = 1;
- ThreadBits = (UINTN)(HighBitSet32(MaxLogicProcessorsPerPackage / MaxCoresPerPackage - 1) + 1);
- CoreBits = (UINTN)(HighBitSet32(MaxCoresPerPackage - 1) + 1); }
+GetBits:
+ ThreadBits = (UINTN)(HighBitSet32(MaxLogicProcessorsPerPackage / MaxCoresPerPackage - 1) + 1);
+ CoreBits = (UINTN)(HighBitSet32(MaxCoresPerPackage - 1) + 1);
+GetLocation:
if (Thread != NULL) {
- *Thread = InitialApicId & ((1 << ThreadBits) - 1);
+ *Thread = InitialApicId & ((1 << ThreadBits) - 1);
}
if (Core != NULL) {
- *Core = (InitialApicId >> ThreadBits) & ((1 << CoreBits) - 1);
+ *Core = (InitialApicId >> ThreadBits) & ((1 << CoreBits) - 1);
}
if (Package != NULL) {
*Package = (InitialApicId >> (ThreadBits + CoreBits));
--
2.7.4
_______________________________________________
edk2-devel mailing list
edk2-devel@lists.01.org
https://lists.01.org/mailman/listinfo/edk2-devel
Leo,
1. If Intel SDM supports the ExtendedCpuIdIndex >= CPUID_AMD_PROCESSOR_TOPOLOGY(0x in the future, the following code may cause expected result for Intel processor.
if (MaxExtendedCpuIdIndex >= CPUID_AMD_PROCESSOR_TOPOLOGY)
May we use another way to check AMD or Intel processor?
2. Goto Statements should not be used (in general) except for error handling (https://github.com/tianocore-docs/Docs/raw/master/Specifications/CCS_2_1_Draft.pdf)
Thanks!
Jeff
-----Original Message-----
From: Leo Duran [mailto:leo.duran@amd.com]
Sent: Tuesday, June 06, 2017 11:59 PM
To: edk2-devel@lists.01.org
Cc: Leo Duran; Justen, Jordan L; Fan, Jeff; Gao, Liming; Brijesh Singh
Subject: [PATCH v3 2/2] UefiCpuPkg: Modify GetProcessorLocationByApicId() to support AMD.
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Jeff Fan <jeff.fan@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Cc: Brijesh Singh <brijesh.singh@amd.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Leo Duran <leo.duran@amd.com>
---
UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c | 130 +++++++++++++++------
.../BaseXApicX2ApicLib/BaseXApicX2ApicLib.c | 130 +++++++++++++++------
2 files changed, 184 insertions(+), 76 deletions(-)
mode change 100644 => 100755 UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c
diff --git a/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c b/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c
old mode 100644
new mode 100755
index f81bbb2..02dfabc
--- a/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c
+++ b/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c
@@ -4,6 +4,8 @@
This local APIC library instance supports xAPIC mode only.
Copyright (c) 2010 - 2016, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2017, AMD Inc. All rights reserved.<BR>
+
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@@ -15,6 +17,7 @@
**/
#include <Register/Cpuid.h>
+#include <Register/Amd/Cpuid.h>
#include <Register/Msr.h>
#include <Register/LocalApic.h>
@@ -966,20 +969,29 @@ GetProcessorLocationByApicId (
OUT UINT32 *Thread OPTIONAL
)
{
- BOOLEAN TopologyLeafSupported;
- UINTN ThreadBits;
- UINTN CoreBits;
- CPUID_VERSION_INFO_EBX VersionInfoEbx;
- CPUID_VERSION_INFO_EDX VersionInfoEdx;
- CPUID_CACHE_PARAMS_EAX CacheParamsEax;
- CPUID_EXTENDED_TOPOLOGY_EAX ExtendedTopologyEax;
- CPUID_EXTENDED_TOPOLOGY_EBX ExtendedTopologyEbx;
- CPUID_EXTENDED_TOPOLOGY_ECX ExtendedTopologyEcx;
- UINT32 MaxCpuIdIndex;
- UINT32 SubIndex;
- UINTN LevelType;
- UINT32 MaxLogicProcessorsPerPackage;
- UINT32 MaxCoresPerPackage;
+ CPUID_VERSION_INFO_EBX VersionInfoEbx;
+ CPUID_VERSION_INFO_EDX VersionInfoEdx;
+ CPUID_CACHE_PARAMS_EAX CacheParamsEax;
+ CPUID_EXTENDED_TOPOLOGY_EAX ExtendedTopologyEax;
+ CPUID_EXTENDED_TOPOLOGY_EBX ExtendedTopologyEbx;
+ CPUID_EXTENDED_TOPOLOGY_ECX ExtendedTopologyEcx;
+ CPUID_AMD_EXTENDED_CPU_SIG_ECX AmdExtendedCpuSigEcx;
+ CPUID_AMD_PROCESSOR_TOPOLOGY_EBX AmdProcessorTopologyEbx;
+ CPUID_AMD_PROCESSOR_TOPOLOGY_ECX AmdProcessorTopologyEcx;
+ CPUID_AMD_VIR_PHY_ADDRESS_SIZE_ECX AmdVirPhyAddressSizeEcx;
+ UINT32 MaxStandardCpuIdIndex;
+ UINT32 MaxExtendedCpuIdIndex;
+ UINT32 SubIndex;
+ UINTN LevelType;
+ UINT32 MaxLogicProcessorsPerPackage;
+ UINT32 MaxCoresPerPackage;
+ UINT32 MaxThreadPerPackageMask;
+ UINT32 ActualThreadPerPackageMask;
+ UINT32 MaxCoresPerNode;
+ UINT32 CorePerNodeMask;
+ UINT32 ApicIdShift;
+ UINTN ThreadBits;
+ UINTN CoreBits;
//
// Check if the processor is capable of supporting more than one logical processor.
@@ -987,10 +999,10 @@ GetProcessorLocationByApicId (
AsmCpuid(CPUID_VERSION_INFO, NULL, NULL, NULL, &VersionInfoEdx.Uint32);
if (VersionInfoEdx.Bits.HTT == 0) {
if (Thread != NULL) {
- *Thread = 0;
+ *Thread = 0;
}
if (Core != NULL) {
- *Core = 0;
+ *Core = 0;
}
if (Package != NULL) {
*Package = 0;
@@ -1002,20 +1014,16 @@ GetProcessorLocationByApicId (
CoreBits = 0;
//
- // Assume three-level mapping of APIC ID: Package:Core:SMT.
+ // Get the max index of CPUID
//
- TopologyLeafSupported = FALSE;
-
- //
- // Get the max index of basic CPUID
- //
- AsmCpuid(CPUID_SIGNATURE, &MaxCpuIdIndex, NULL, NULL, NULL);
+ AsmCpuid(CPUID_SIGNATURE, &MaxStandardCpuIdIndex, NULL, NULL, NULL);
+ AsmCpuid(CPUID_EXTENDED_FUNCTION, &MaxExtendedCpuIdIndex, NULL, NULL, NULL);
//
// If the extended topology enumeration leaf is available, it
// is the preferred mechanism for enumerating topology.
//
- if (MaxCpuIdIndex >= CPUID_EXTENDED_TOPOLOGY) {
+ if (MaxStandardCpuIdIndex >= CPUID_EXTENDED_TOPOLOGY) {
AsmCpuidEx(
CPUID_EXTENDED_TOPOLOGY,
0,
@@ -1030,8 +1038,6 @@ GetProcessorLocationByApicId (
// supported on that processor.
//
if (ExtendedTopologyEbx.Uint32 != 0) {
- TopologyLeafSupported = TRUE;
-
//
// Sub-leaf index 0 (ECX= 0 as input) provides enumeration parameters to extract
// the SMT sub-field of x2APIC ID.
@@ -1061,31 +1067,79 @@ GetProcessorLocationByApicId (
}
SubIndex++;
} while (LevelType != CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID);
+ goto GetLocation;
}
}
- if (!TopologyLeafSupported) {
- AsmCpuid(CPUID_VERSION_INFO, NULL, &VersionInfoEbx.Uint32, NULL, NULL);
- MaxLogicProcessorsPerPackage = VersionInfoEbx.Bits.MaximumAddressableIdsForLogicalProcessors;
- if (MaxCpuIdIndex >= CPUID_CACHE_PARAMS) {
- AsmCpuidEx(CPUID_CACHE_PARAMS, 0, &CacheParamsEax.Uint32, NULL, NULL, NULL);
+ AsmCpuid(CPUID_VERSION_INFO, NULL, &VersionInfoEbx.Uint32, NULL, NULL);
+ MaxLogicProcessorsPerPackage = VersionInfoEbx.Bits.MaximumAddressableIdsForLogicalProcessors;
+
+ if (MaxStandardCpuIdIndex >= CPUID_CACHE_PARAMS) {
+ AsmCpuidEx(CPUID_CACHE_PARAMS, 0, &CacheParamsEax.Uint32, NULL, NULL, NULL);
+ if (CacheParamsEax.Uint32 != 0) {
MaxCoresPerPackage = CacheParamsEax.Bits.MaximumAddressableIdsForLogicalProcessors + 1;
+ goto GetBits;
}
- else {
+ }
+
+ if (MaxExtendedCpuIdIndex >= CPUID_AMD_PROCESSOR_TOPOLOGY) {
+ AsmCpuid(CPUID_EXTENDED_CPU_SIG, NULL, NULL, &AmdExtendedCpuSigEcx.Uint32, NULL);
+ if (AmdExtendedCpuSigEcx.Bits.TopologyExtensions != 0) {
+ AsmCpuid(CPUID_AMD_PROCESSOR_TOPOLOGY, NULL, &AmdProcessorTopologyEbx.Uint32,
+ &AmdProcessorTopologyEcx.Uint32, NULL);
+
+ MaxCoresPerPackage = MaxLogicProcessorsPerPackage / (AmdProcessorTopologyEbx.Bits.ThreadsPerCore + 1);
+
//
- // Must be a single-core processor.
+ // Account for actual thread count (e.g., SMT disabled)
//
- MaxCoresPerPackage = 1;
+ AsmCpuid(CPUID_VIR_PHY_ADDRESS_SIZE, NULL, NULL, &AmdVirPhyAddressSizeEcx.Uint32, NULL);
+ MaxThreadPerPackageMask = 1 << AmdVirPhyAddressSizeEcx.Bits.ApicIdCoreIdSize;
+ ActualThreadPerPackageMask = 1;
+ while (ActualThreadPerPackageMask < MaxLogicProcessorsPerPackage) {
+ ActualThreadPerPackageMask <<= 1;
+ }
+
+ if (ActualThreadPerPackageMask < MaxThreadPerPackageMask) {
+ MaxCoresPerNode = MaxCoresPerPackage / (AmdProcessorTopologyEcx.Bits.NodesPerProcessor + 1);
+
+ CorePerNodeMask = 1;
+ while (CorePerNodeMask < MaxCoresPerNode) {
+ CorePerNodeMask <<= 1;
+ }
+ CorePerNodeMask -= 1;
+
+ ApicIdShift = 0;
+ do {
+ ApicIdShift += 1;
+ ActualThreadPerPackageMask <<= 1;
+ } while (ActualThreadPerPackageMask < MaxThreadPerPackageMask);
+
+ //
+ // Adjust APIC Id to report concatenation of Package|Core|Thread.
+ //
+ InitialApicId = ((InitialApicId & ~CorePerNodeMask) >> ApicIdShift) | (InitialApicId & CorePerNodeMask);
+ }
+
+ goto GetBits;
}
+ }
+
+ //
+ // Must be a single-core processor.
+ //
+ MaxCoresPerPackage = 1;
- ThreadBits = (UINTN)(HighBitSet32(MaxLogicProcessorsPerPackage / MaxCoresPerPackage - 1) + 1);
- CoreBits = (UINTN)(HighBitSet32(MaxCoresPerPackage - 1) + 1); }
+GetBits:
+ ThreadBits = (UINTN)(HighBitSet32(MaxLogicProcessorsPerPackage / MaxCoresPerPackage - 1) + 1);
+ CoreBits = (UINTN)(HighBitSet32(MaxCoresPerPackage - 1) + 1);
+GetLocation:
if (Thread != NULL) {
- *Thread = InitialApicId & ((1 << ThreadBits) - 1);
+ *Thread = InitialApicId & ((1 << ThreadBits) - 1);
}
if (Core != NULL) {
- *Core = (InitialApicId >> ThreadBits) & ((1 << CoreBits) - 1);
+ *Core = (InitialApicId >> ThreadBits) & ((1 << CoreBits) - 1);
}
if (Package != NULL) {
*Package = (InitialApicId >> (ThreadBits + CoreBits));
diff --git a/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c b/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c
index e690d2a..726e1e0 100644
--- a/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c
+++ b/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c
@@ -5,6 +5,8 @@
which have xAPIC and x2APIC modes.
Copyright (c) 2010 - 2016, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2017, AMD Inc. All rights reserved.<BR>
+
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@@ -16,6 +18,7 @@
**/
#include <Register/Cpuid.h>
+#include <Register/Amd/Cpuid.h>
#include <Register/Msr.h>
#include <Register/LocalApic.h>
@@ -1061,20 +1064,29 @@ GetProcessorLocationByApicId (
OUT UINT32 *Thread OPTIONAL
)
{
- BOOLEAN TopologyLeafSupported;
- UINTN ThreadBits;
- UINTN CoreBits;
- CPUID_VERSION_INFO_EBX VersionInfoEbx;
- CPUID_VERSION_INFO_EDX VersionInfoEdx;
- CPUID_CACHE_PARAMS_EAX CacheParamsEax;
- CPUID_EXTENDED_TOPOLOGY_EAX ExtendedTopologyEax;
- CPUID_EXTENDED_TOPOLOGY_EBX ExtendedTopologyEbx;
- CPUID_EXTENDED_TOPOLOGY_ECX ExtendedTopologyEcx;
- UINT32 MaxCpuIdIndex;
- UINT32 SubIndex;
- UINTN LevelType;
- UINT32 MaxLogicProcessorsPerPackage;
- UINT32 MaxCoresPerPackage;
+ CPUID_VERSION_INFO_EBX VersionInfoEbx;
+ CPUID_VERSION_INFO_EDX VersionInfoEdx;
+ CPUID_CACHE_PARAMS_EAX CacheParamsEax;
+ CPUID_EXTENDED_TOPOLOGY_EAX ExtendedTopologyEax;
+ CPUID_EXTENDED_TOPOLOGY_EBX ExtendedTopologyEbx;
+ CPUID_EXTENDED_TOPOLOGY_ECX ExtendedTopologyEcx;
+ CPUID_AMD_EXTENDED_CPU_SIG_ECX AmdExtendedCpuSigEcx;
+ CPUID_AMD_PROCESSOR_TOPOLOGY_EBX AmdProcessorTopologyEbx;
+ CPUID_AMD_PROCESSOR_TOPOLOGY_ECX AmdProcessorTopologyEcx;
+ CPUID_AMD_VIR_PHY_ADDRESS_SIZE_ECX AmdVirPhyAddressSizeEcx;
+ UINT32 MaxStandardCpuIdIndex;
+ UINT32 MaxExtendedCpuIdIndex;
+ UINT32 SubIndex;
+ UINTN LevelType;
+ UINT32 MaxLogicProcessorsPerPackage;
+ UINT32 MaxCoresPerPackage;
+ UINT32 MaxThreadPerPackageMask;
+ UINT32 ActualThreadPerPackageMask;
+ UINT32 MaxCoresPerNode;
+ UINT32 CorePerNodeMask;
+ UINT32 ApicIdShift;
+ UINTN ThreadBits;
+ UINTN CoreBits;
//
// Check if the processor is capable of supporting more than one logical processor.
@@ -1082,10 +1094,10 @@ GetProcessorLocationByApicId (
AsmCpuid(CPUID_VERSION_INFO, NULL, NULL, NULL, &VersionInfoEdx.Uint32);
if (VersionInfoEdx.Bits.HTT == 0) {
if (Thread != NULL) {
- *Thread = 0;
+ *Thread = 0;
}
if (Core != NULL) {
- *Core = 0;
+ *Core = 0;
}
if (Package != NULL) {
*Package = 0;
@@ -1097,20 +1109,16 @@ GetProcessorLocationByApicId (
CoreBits = 0;
//
- // Assume three-level mapping of APIC ID: Package:Core:SMT.
+ // Get the max index of CPUID
//
- TopologyLeafSupported = FALSE;
-
- //
- // Get the max index of basic CPUID
- //
- AsmCpuid(CPUID_SIGNATURE, &MaxCpuIdIndex, NULL, NULL, NULL);
+ AsmCpuid(CPUID_SIGNATURE, &MaxStandardCpuIdIndex, NULL, NULL, NULL);
+ AsmCpuid(CPUID_EXTENDED_FUNCTION, &MaxExtendedCpuIdIndex, NULL, NULL, NULL);
//
// If the extended topology enumeration leaf is available, it
// is the preferred mechanism for enumerating topology.
//
- if (MaxCpuIdIndex >= CPUID_EXTENDED_TOPOLOGY) {
+ if (MaxStandardCpuIdIndex >= CPUID_EXTENDED_TOPOLOGY) {
AsmCpuidEx(
CPUID_EXTENDED_TOPOLOGY,
0,
@@ -1125,8 +1133,6 @@ GetProcessorLocationByApicId (
// supported on that processor.
//
if (ExtendedTopologyEbx.Uint32 != 0) {
- TopologyLeafSupported = TRUE;
-
//
// Sub-leaf index 0 (ECX= 0 as input) provides enumeration parameters to extract
// the SMT sub-field of x2APIC ID.
@@ -1156,31 +1162,79 @@ GetProcessorLocationByApicId (
}
SubIndex++;
} while (LevelType != CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID);
+ goto GetLocation;
}
}
- if (!TopologyLeafSupported) {
- AsmCpuid(CPUID_VERSION_INFO, NULL, &VersionInfoEbx.Uint32, NULL, NULL);
- MaxLogicProcessorsPerPackage = VersionInfoEbx.Bits.MaximumAddressableIdsForLogicalProcessors;
- if (MaxCpuIdIndex >= CPUID_CACHE_PARAMS) {
- AsmCpuidEx(CPUID_CACHE_PARAMS, 0, &CacheParamsEax.Uint32, NULL, NULL, NULL);
+ AsmCpuid(CPUID_VERSION_INFO, NULL, &VersionInfoEbx.Uint32, NULL, NULL);
+ MaxLogicProcessorsPerPackage = VersionInfoEbx.Bits.MaximumAddressableIdsForLogicalProcessors;
+
+ if (MaxStandardCpuIdIndex >= CPUID_CACHE_PARAMS) {
+ AsmCpuidEx(CPUID_CACHE_PARAMS, 0, &CacheParamsEax.Uint32, NULL, NULL, NULL);
+ if (CacheParamsEax.Uint32 != 0) {
MaxCoresPerPackage = CacheParamsEax.Bits.MaximumAddressableIdsForLogicalProcessors + 1;
+ goto GetBits;
}
- else {
+ }
+
+ if (MaxExtendedCpuIdIndex >= CPUID_AMD_PROCESSOR_TOPOLOGY) {
+ AsmCpuid(CPUID_EXTENDED_CPU_SIG, NULL, NULL, &AmdExtendedCpuSigEcx.Uint32, NULL);
+ if (AmdExtendedCpuSigEcx.Bits.TopologyExtensions != 0) {
+ AsmCpuid(CPUID_AMD_PROCESSOR_TOPOLOGY, NULL, &AmdProcessorTopologyEbx.Uint32,
+ &AmdProcessorTopologyEcx.Uint32, NULL);
+
+ MaxCoresPerPackage = MaxLogicProcessorsPerPackage / (AmdProcessorTopologyEbx.Bits.ThreadsPerCore + 1);
+
//
- // Must be a single-core processor.
+ // Account for actual thread count (e.g., SMT disabled)
//
- MaxCoresPerPackage = 1;
+ AsmCpuid(CPUID_VIR_PHY_ADDRESS_SIZE, NULL, NULL, &AmdVirPhyAddressSizeEcx.Uint32, NULL);
+ MaxThreadPerPackageMask = 1 << AmdVirPhyAddressSizeEcx.Bits.ApicIdCoreIdSize;
+ ActualThreadPerPackageMask = 1;
+ while (ActualThreadPerPackageMask < MaxLogicProcessorsPerPackage) {
+ ActualThreadPerPackageMask <<= 1;
+ }
+
+ if (ActualThreadPerPackageMask < MaxThreadPerPackageMask) {
+ MaxCoresPerNode = MaxCoresPerPackage / (AmdProcessorTopologyEcx.Bits.NodesPerProcessor + 1);
+
+ CorePerNodeMask = 1;
+ while (CorePerNodeMask < MaxCoresPerNode) {
+ CorePerNodeMask <<= 1;
+ }
+ CorePerNodeMask -= 1;
+
+ ApicIdShift = 0;
+ do {
+ ApicIdShift += 1;
+ ActualThreadPerPackageMask <<= 1;
+ } while (ActualThreadPerPackageMask < MaxThreadPerPackageMask);
+
+ //
+ // Adjust APIC Id to report concatenation of Package|Core|Thread.
+ //
+ InitialApicId = ((InitialApicId & ~CorePerNodeMask) >> ApicIdShift) | (InitialApicId & CorePerNodeMask);
+ }
+
+ goto GetBits;
}
+ }
+
+ //
+ // Must be a single-core processor.
+ //
+ MaxCoresPerPackage = 1;
- ThreadBits = (UINTN)(HighBitSet32(MaxLogicProcessorsPerPackage / MaxCoresPerPackage - 1) + 1);
- CoreBits = (UINTN)(HighBitSet32(MaxCoresPerPackage - 1) + 1); }
+GetBits:
+ ThreadBits = (UINTN)(HighBitSet32(MaxLogicProcessorsPerPackage / MaxCoresPerPackage - 1) + 1);
+ CoreBits = (UINTN)(HighBitSet32(MaxCoresPerPackage - 1) + 1);
+GetLocation:
if (Thread != NULL) {
- *Thread = InitialApicId & ((1 << ThreadBits) - 1);
+ *Thread = InitialApicId & ((1 << ThreadBits) - 1);
}
if (Core != NULL) {
- *Core = (InitialApicId >> ThreadBits) & ((1 << CoreBits) - 1);
+ *Core = (InitialApicId >> ThreadBits) & ((1 << CoreBits) - 1);
}
if (Package != NULL) {
*Package = (InitialApicId >> (ThreadBits + CoreBits));
--
2.7.4
_______________________________________________
edk2-devel mailing list
edk2-devel@lists.01.org
https://lists.01.org/mailman/listinfo/edk2-devel
Leo,
Correct some words in below mail body.
Jeff
-----Original Message-----
From: edk2-devel [mailto:edk2-devel-bounces@lists.01.org] On Behalf Of Fan, Jeff
Sent: Thursday, June 08, 2017 1:34 PM
To: Leo Duran; edk2-devel@lists.01.org
Cc: Justen, Jordan L; Gao, Liming
Subject: Re: [edk2] [PATCH v3 2/2] UefiCpuPkg: Modify GetProcessorLocationByApicId() to support AMD.
Leo,
1. If Intel SDM supports the ExtendedCpuIdIndex >= CPUID_AMD_PROCESSOR_TOPOLOGY(0x8000001E) in the future, the following code may cause unexpected result for Intel processor.
if (MaxExtendedCpuIdIndex >= CPUID_AMD_PROCESSOR_TOPOLOGY)
May we use another way to check AMD or Intel processor?
2. Goto Statements should not be used (in general) except for error handling (https://github.com/tianocore-docs/Docs/raw/master/Specifications/CCS_2_1_Draft.pdf)
Thanks!
Jeff
-----Original Message-----
From: Leo Duran [mailto:leo.duran@amd.com]
Sent: Tuesday, June 06, 2017 11:59 PM
To: edk2-devel@lists.01.org
Cc: Leo Duran; Justen, Jordan L; Fan, Jeff; Gao, Liming; Brijesh Singh
Subject: [PATCH v3 2/2] UefiCpuPkg: Modify GetProcessorLocationByApicId() to support AMD.
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Jeff Fan <jeff.fan@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Cc: Brijesh Singh <brijesh.singh@amd.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Leo Duran <leo.duran@amd.com>
---
UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c | 130 +++++++++++++++------
.../BaseXApicX2ApicLib/BaseXApicX2ApicLib.c | 130 +++++++++++++++------
2 files changed, 184 insertions(+), 76 deletions(-) mode change 100644 => 100755 UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c
diff --git a/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c b/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c
old mode 100644
new mode 100755
index f81bbb2..02dfabc
--- a/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c
+++ b/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c
@@ -4,6 +4,8 @@
This local APIC library instance supports xAPIC mode only.
Copyright (c) 2010 - 2016, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2017, AMD Inc. All rights reserved.<BR>
+
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at @@ -15,6 +17,7 @@ **/
#include <Register/Cpuid.h>
+#include <Register/Amd/Cpuid.h>
#include <Register/Msr.h>
#include <Register/LocalApic.h>
@@ -966,20 +969,29 @@ GetProcessorLocationByApicId (
OUT UINT32 *Thread OPTIONAL
)
{
- BOOLEAN TopologyLeafSupported;
- UINTN ThreadBits;
- UINTN CoreBits;
- CPUID_VERSION_INFO_EBX VersionInfoEbx;
- CPUID_VERSION_INFO_EDX VersionInfoEdx;
- CPUID_CACHE_PARAMS_EAX CacheParamsEax;
- CPUID_EXTENDED_TOPOLOGY_EAX ExtendedTopologyEax;
- CPUID_EXTENDED_TOPOLOGY_EBX ExtendedTopologyEbx;
- CPUID_EXTENDED_TOPOLOGY_ECX ExtendedTopologyEcx;
- UINT32 MaxCpuIdIndex;
- UINT32 SubIndex;
- UINTN LevelType;
- UINT32 MaxLogicProcessorsPerPackage;
- UINT32 MaxCoresPerPackage;
+ CPUID_VERSION_INFO_EBX VersionInfoEbx;
+ CPUID_VERSION_INFO_EDX VersionInfoEdx;
+ CPUID_CACHE_PARAMS_EAX CacheParamsEax;
+ CPUID_EXTENDED_TOPOLOGY_EAX ExtendedTopologyEax;
+ CPUID_EXTENDED_TOPOLOGY_EBX ExtendedTopologyEbx;
+ CPUID_EXTENDED_TOPOLOGY_ECX ExtendedTopologyEcx;
+ CPUID_AMD_EXTENDED_CPU_SIG_ECX AmdExtendedCpuSigEcx;
+ CPUID_AMD_PROCESSOR_TOPOLOGY_EBX AmdProcessorTopologyEbx;
+ CPUID_AMD_PROCESSOR_TOPOLOGY_ECX AmdProcessorTopologyEcx;
+ CPUID_AMD_VIR_PHY_ADDRESS_SIZE_ECX AmdVirPhyAddressSizeEcx;
+ UINT32 MaxStandardCpuIdIndex;
+ UINT32 MaxExtendedCpuIdIndex;
+ UINT32 SubIndex;
+ UINTN LevelType;
+ UINT32 MaxLogicProcessorsPerPackage;
+ UINT32 MaxCoresPerPackage;
+ UINT32 MaxThreadPerPackageMask;
+ UINT32 ActualThreadPerPackageMask;
+ UINT32 MaxCoresPerNode;
+ UINT32 CorePerNodeMask;
+ UINT32 ApicIdShift;
+ UINTN ThreadBits;
+ UINTN CoreBits;
//
// Check if the processor is capable of supporting more than one logical processor.
@@ -987,10 +999,10 @@ GetProcessorLocationByApicId (
AsmCpuid(CPUID_VERSION_INFO, NULL, NULL, NULL, &VersionInfoEdx.Uint32);
if (VersionInfoEdx.Bits.HTT == 0) {
if (Thread != NULL) {
- *Thread = 0;
+ *Thread = 0;
}
if (Core != NULL) {
- *Core = 0;
+ *Core = 0;
}
if (Package != NULL) {
*Package = 0;
@@ -1002,20 +1014,16 @@ GetProcessorLocationByApicId (
CoreBits = 0;
//
- // Assume three-level mapping of APIC ID: Package:Core:SMT.
+ // Get the max index of CPUID
//
- TopologyLeafSupported = FALSE;
-
- //
- // Get the max index of basic CPUID
- //
- AsmCpuid(CPUID_SIGNATURE, &MaxCpuIdIndex, NULL, NULL, NULL);
+ AsmCpuid(CPUID_SIGNATURE, &MaxStandardCpuIdIndex, NULL, NULL, NULL);
+ AsmCpuid(CPUID_EXTENDED_FUNCTION, &MaxExtendedCpuIdIndex, NULL, NULL,
+ NULL);
//
// If the extended topology enumeration leaf is available, it
// is the preferred mechanism for enumerating topology.
//
- if (MaxCpuIdIndex >= CPUID_EXTENDED_TOPOLOGY) {
+ if (MaxStandardCpuIdIndex >= CPUID_EXTENDED_TOPOLOGY) {
AsmCpuidEx(
CPUID_EXTENDED_TOPOLOGY,
0,
@@ -1030,8 +1038,6 @@ GetProcessorLocationByApicId (
// supported on that processor.
//
if (ExtendedTopologyEbx.Uint32 != 0) {
- TopologyLeafSupported = TRUE;
-
//
// Sub-leaf index 0 (ECX= 0 as input) provides enumeration parameters to extract
// the SMT sub-field of x2APIC ID.
@@ -1061,31 +1067,79 @@ GetProcessorLocationByApicId (
}
SubIndex++;
} while (LevelType != CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID);
+ goto GetLocation;
}
}
- if (!TopologyLeafSupported) {
- AsmCpuid(CPUID_VERSION_INFO, NULL, &VersionInfoEbx.Uint32, NULL, NULL);
- MaxLogicProcessorsPerPackage = VersionInfoEbx.Bits.MaximumAddressableIdsForLogicalProcessors;
- if (MaxCpuIdIndex >= CPUID_CACHE_PARAMS) {
- AsmCpuidEx(CPUID_CACHE_PARAMS, 0, &CacheParamsEax.Uint32, NULL, NULL, NULL);
+ AsmCpuid(CPUID_VERSION_INFO, NULL, &VersionInfoEbx.Uint32, NULL,
+ NULL); MaxLogicProcessorsPerPackage =
+ VersionInfoEbx.Bits.MaximumAddressableIdsForLogicalProcessors;
+
+ if (MaxStandardCpuIdIndex >= CPUID_CACHE_PARAMS) {
+ AsmCpuidEx(CPUID_CACHE_PARAMS, 0, &CacheParamsEax.Uint32, NULL, NULL, NULL);
+ if (CacheParamsEax.Uint32 != 0) {
MaxCoresPerPackage = CacheParamsEax.Bits.MaximumAddressableIdsForLogicalProcessors + 1;
+ goto GetBits;
}
- else {
+ }
+
+ if (MaxExtendedCpuIdIndex >= CPUID_AMD_PROCESSOR_TOPOLOGY) {
+ AsmCpuid(CPUID_EXTENDED_CPU_SIG, NULL, NULL, &AmdExtendedCpuSigEcx.Uint32, NULL);
+ if (AmdExtendedCpuSigEcx.Bits.TopologyExtensions != 0) {
+ AsmCpuid(CPUID_AMD_PROCESSOR_TOPOLOGY, NULL, &AmdProcessorTopologyEbx.Uint32,
+ &AmdProcessorTopologyEcx.Uint32, NULL);
+
+ MaxCoresPerPackage = MaxLogicProcessorsPerPackage /
+ (AmdProcessorTopologyEbx.Bits.ThreadsPerCore + 1);
+
//
- // Must be a single-core processor.
+ // Account for actual thread count (e.g., SMT disabled)
//
- MaxCoresPerPackage = 1;
+ AsmCpuid(CPUID_VIR_PHY_ADDRESS_SIZE, NULL, NULL, &AmdVirPhyAddressSizeEcx.Uint32, NULL);
+ MaxThreadPerPackageMask = 1 << AmdVirPhyAddressSizeEcx.Bits.ApicIdCoreIdSize;
+ ActualThreadPerPackageMask = 1;
+ while (ActualThreadPerPackageMask < MaxLogicProcessorsPerPackage) {
+ ActualThreadPerPackageMask <<= 1;
+ }
+
+ if (ActualThreadPerPackageMask < MaxThreadPerPackageMask) {
+ MaxCoresPerNode = MaxCoresPerPackage /
+ (AmdProcessorTopologyEcx.Bits.NodesPerProcessor + 1);
+
+ CorePerNodeMask = 1;
+ while (CorePerNodeMask < MaxCoresPerNode) {
+ CorePerNodeMask <<= 1;
+ }
+ CorePerNodeMask -= 1;
+
+ ApicIdShift = 0;
+ do {
+ ApicIdShift += 1;
+ ActualThreadPerPackageMask <<= 1;
+ } while (ActualThreadPerPackageMask < MaxThreadPerPackageMask);
+
+ //
+ // Adjust APIC Id to report concatenation of Package|Core|Thread.
+ //
+ InitialApicId = ((InitialApicId & ~CorePerNodeMask) >> ApicIdShift) | (InitialApicId & CorePerNodeMask);
+ }
+
+ goto GetBits;
}
+ }
+
+ //
+ // Must be a single-core processor.
+ //
+ MaxCoresPerPackage = 1;
- ThreadBits = (UINTN)(HighBitSet32(MaxLogicProcessorsPerPackage / MaxCoresPerPackage - 1) + 1);
- CoreBits = (UINTN)(HighBitSet32(MaxCoresPerPackage - 1) + 1); }
+GetBits:
+ ThreadBits = (UINTN)(HighBitSet32(MaxLogicProcessorsPerPackage /
+MaxCoresPerPackage - 1) + 1);
+ CoreBits = (UINTN)(HighBitSet32(MaxCoresPerPackage - 1) + 1);
+GetLocation:
if (Thread != NULL) {
- *Thread = InitialApicId & ((1 << ThreadBits) - 1);
+ *Thread = InitialApicId & ((1 << ThreadBits) - 1);
}
if (Core != NULL) {
- *Core = (InitialApicId >> ThreadBits) & ((1 << CoreBits) - 1);
+ *Core = (InitialApicId >> ThreadBits) & ((1 << CoreBits) - 1);
}
if (Package != NULL) {
*Package = (InitialApicId >> (ThreadBits + CoreBits)); diff --git a/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c b/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c
index e690d2a..726e1e0 100644
--- a/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c
+++ b/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c
@@ -5,6 +5,8 @@
which have xAPIC and x2APIC modes.
Copyright (c) 2010 - 2016, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2017, AMD Inc. All rights reserved.<BR>
+
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at @@ -16,6 +18,7 @@ **/
#include <Register/Cpuid.h>
+#include <Register/Amd/Cpuid.h>
#include <Register/Msr.h>
#include <Register/LocalApic.h>
@@ -1061,20 +1064,29 @@ GetProcessorLocationByApicId (
OUT UINT32 *Thread OPTIONAL
)
{
- BOOLEAN TopologyLeafSupported;
- UINTN ThreadBits;
- UINTN CoreBits;
- CPUID_VERSION_INFO_EBX VersionInfoEbx;
- CPUID_VERSION_INFO_EDX VersionInfoEdx;
- CPUID_CACHE_PARAMS_EAX CacheParamsEax;
- CPUID_EXTENDED_TOPOLOGY_EAX ExtendedTopologyEax;
- CPUID_EXTENDED_TOPOLOGY_EBX ExtendedTopologyEbx;
- CPUID_EXTENDED_TOPOLOGY_ECX ExtendedTopologyEcx;
- UINT32 MaxCpuIdIndex;
- UINT32 SubIndex;
- UINTN LevelType;
- UINT32 MaxLogicProcessorsPerPackage;
- UINT32 MaxCoresPerPackage;
+ CPUID_VERSION_INFO_EBX VersionInfoEbx;
+ CPUID_VERSION_INFO_EDX VersionInfoEdx;
+ CPUID_CACHE_PARAMS_EAX CacheParamsEax;
+ CPUID_EXTENDED_TOPOLOGY_EAX ExtendedTopologyEax;
+ CPUID_EXTENDED_TOPOLOGY_EBX ExtendedTopologyEbx;
+ CPUID_EXTENDED_TOPOLOGY_ECX ExtendedTopologyEcx;
+ CPUID_AMD_EXTENDED_CPU_SIG_ECX AmdExtendedCpuSigEcx;
+ CPUID_AMD_PROCESSOR_TOPOLOGY_EBX AmdProcessorTopologyEbx;
+ CPUID_AMD_PROCESSOR_TOPOLOGY_ECX AmdProcessorTopologyEcx;
+ CPUID_AMD_VIR_PHY_ADDRESS_SIZE_ECX AmdVirPhyAddressSizeEcx;
+ UINT32 MaxStandardCpuIdIndex;
+ UINT32 MaxExtendedCpuIdIndex;
+ UINT32 SubIndex;
+ UINTN LevelType;
+ UINT32 MaxLogicProcessorsPerPackage;
+ UINT32 MaxCoresPerPackage;
+ UINT32 MaxThreadPerPackageMask;
+ UINT32 ActualThreadPerPackageMask;
+ UINT32 MaxCoresPerNode;
+ UINT32 CorePerNodeMask;
+ UINT32 ApicIdShift;
+ UINTN ThreadBits;
+ UINTN CoreBits;
//
// Check if the processor is capable of supporting more than one logical processor.
@@ -1082,10 +1094,10 @@ GetProcessorLocationByApicId (
AsmCpuid(CPUID_VERSION_INFO, NULL, NULL, NULL, &VersionInfoEdx.Uint32);
if (VersionInfoEdx.Bits.HTT == 0) {
if (Thread != NULL) {
- *Thread = 0;
+ *Thread = 0;
}
if (Core != NULL) {
- *Core = 0;
+ *Core = 0;
}
if (Package != NULL) {
*Package = 0;
@@ -1097,20 +1109,16 @@ GetProcessorLocationByApicId (
CoreBits = 0;
//
- // Assume three-level mapping of APIC ID: Package:Core:SMT.
+ // Get the max index of CPUID
//
- TopologyLeafSupported = FALSE;
-
- //
- // Get the max index of basic CPUID
- //
- AsmCpuid(CPUID_SIGNATURE, &MaxCpuIdIndex, NULL, NULL, NULL);
+ AsmCpuid(CPUID_SIGNATURE, &MaxStandardCpuIdIndex, NULL, NULL, NULL);
+ AsmCpuid(CPUID_EXTENDED_FUNCTION, &MaxExtendedCpuIdIndex, NULL, NULL,
+ NULL);
//
// If the extended topology enumeration leaf is available, it
// is the preferred mechanism for enumerating topology.
//
- if (MaxCpuIdIndex >= CPUID_EXTENDED_TOPOLOGY) {
+ if (MaxStandardCpuIdIndex >= CPUID_EXTENDED_TOPOLOGY) {
AsmCpuidEx(
CPUID_EXTENDED_TOPOLOGY,
0,
@@ -1125,8 +1133,6 @@ GetProcessorLocationByApicId (
// supported on that processor.
//
if (ExtendedTopologyEbx.Uint32 != 0) {
- TopologyLeafSupported = TRUE;
-
//
// Sub-leaf index 0 (ECX= 0 as input) provides enumeration parameters to extract
// the SMT sub-field of x2APIC ID.
@@ -1156,31 +1162,79 @@ GetProcessorLocationByApicId (
}
SubIndex++;
} while (LevelType != CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID);
+ goto GetLocation;
}
}
- if (!TopologyLeafSupported) {
- AsmCpuid(CPUID_VERSION_INFO, NULL, &VersionInfoEbx.Uint32, NULL, NULL);
- MaxLogicProcessorsPerPackage = VersionInfoEbx.Bits.MaximumAddressableIdsForLogicalProcessors;
- if (MaxCpuIdIndex >= CPUID_CACHE_PARAMS) {
- AsmCpuidEx(CPUID_CACHE_PARAMS, 0, &CacheParamsEax.Uint32, NULL, NULL, NULL);
+ AsmCpuid(CPUID_VERSION_INFO, NULL, &VersionInfoEbx.Uint32, NULL,
+ NULL); MaxLogicProcessorsPerPackage =
+ VersionInfoEbx.Bits.MaximumAddressableIdsForLogicalProcessors;
+
+ if (MaxStandardCpuIdIndex >= CPUID_CACHE_PARAMS) {
+ AsmCpuidEx(CPUID_CACHE_PARAMS, 0, &CacheParamsEax.Uint32, NULL, NULL, NULL);
+ if (CacheParamsEax.Uint32 != 0) {
MaxCoresPerPackage = CacheParamsEax.Bits.MaximumAddressableIdsForLogicalProcessors + 1;
+ goto GetBits;
}
- else {
+ }
+
+ if (MaxExtendedCpuIdIndex >= CPUID_AMD_PROCESSOR_TOPOLOGY) {
+ AsmCpuid(CPUID_EXTENDED_CPU_SIG, NULL, NULL, &AmdExtendedCpuSigEcx.Uint32, NULL);
+ if (AmdExtendedCpuSigEcx.Bits.TopologyExtensions != 0) {
+ AsmCpuid(CPUID_AMD_PROCESSOR_TOPOLOGY, NULL, &AmdProcessorTopologyEbx.Uint32,
+ &AmdProcessorTopologyEcx.Uint32, NULL);
+
+ MaxCoresPerPackage = MaxLogicProcessorsPerPackage /
+ (AmdProcessorTopologyEbx.Bits.ThreadsPerCore + 1);
+
//
- // Must be a single-core processor.
+ // Account for actual thread count (e.g., SMT disabled)
//
- MaxCoresPerPackage = 1;
+ AsmCpuid(CPUID_VIR_PHY_ADDRESS_SIZE, NULL, NULL, &AmdVirPhyAddressSizeEcx.Uint32, NULL);
+ MaxThreadPerPackageMask = 1 << AmdVirPhyAddressSizeEcx.Bits.ApicIdCoreIdSize;
+ ActualThreadPerPackageMask = 1;
+ while (ActualThreadPerPackageMask < MaxLogicProcessorsPerPackage) {
+ ActualThreadPerPackageMask <<= 1;
+ }
+
+ if (ActualThreadPerPackageMask < MaxThreadPerPackageMask) {
+ MaxCoresPerNode = MaxCoresPerPackage /
+ (AmdProcessorTopologyEcx.Bits.NodesPerProcessor + 1);
+
+ CorePerNodeMask = 1;
+ while (CorePerNodeMask < MaxCoresPerNode) {
+ CorePerNodeMask <<= 1;
+ }
+ CorePerNodeMask -= 1;
+
+ ApicIdShift = 0;
+ do {
+ ApicIdShift += 1;
+ ActualThreadPerPackageMask <<= 1;
+ } while (ActualThreadPerPackageMask < MaxThreadPerPackageMask);
+
+ //
+ // Adjust APIC Id to report concatenation of Package|Core|Thread.
+ //
+ InitialApicId = ((InitialApicId & ~CorePerNodeMask) >> ApicIdShift) | (InitialApicId & CorePerNodeMask);
+ }
+
+ goto GetBits;
}
+ }
+
+ //
+ // Must be a single-core processor.
+ //
+ MaxCoresPerPackage = 1;
- ThreadBits = (UINTN)(HighBitSet32(MaxLogicProcessorsPerPackage / MaxCoresPerPackage - 1) + 1);
- CoreBits = (UINTN)(HighBitSet32(MaxCoresPerPackage - 1) + 1); }
+GetBits:
+ ThreadBits = (UINTN)(HighBitSet32(MaxLogicProcessorsPerPackage /
+MaxCoresPerPackage - 1) + 1);
+ CoreBits = (UINTN)(HighBitSet32(MaxCoresPerPackage - 1) + 1);
+GetLocation:
if (Thread != NULL) {
- *Thread = InitialApicId & ((1 << ThreadBits) - 1);
+ *Thread = InitialApicId & ((1 << ThreadBits) - 1);
}
if (Core != NULL) {
- *Core = (InitialApicId >> ThreadBits) & ((1 << CoreBits) - 1);
+ *Core = (InitialApicId >> ThreadBits) & ((1 << CoreBits) - 1);
}
if (Package != NULL) {
*Package = (InitialApicId >> (ThreadBits + CoreBits));
--
2.7.4
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Hi Jeff,
Please see my replies below.
Thanks,
Leo.
> -----Original Message-----
> From: Fan, Jeff [mailto:jeff.fan@intel.com]
> Sent: Thursday, June 08, 2017 12:37 AM
> To: Fan, Jeff <jeff.fan@intel.com>; Duran, Leo <leo.duran@amd.com>;
> edk2-devel@lists.01.org
> Cc: Justen, Jordan L <jordan.l.justen@intel.com>; Gao, Liming
> <liming.gao@intel.com>
> Subject: RE: [PATCH v3 2/2] UefiCpuPkg: Modify
> GetProcessorLocationByApicId() to support AMD.
>
> Leo,
>
> Correct some words in below mail body.
>
> Jeff
>
> -----Original Message-----
> From: edk2-devel [mailto:edk2-devel-bounces@lists.01.org] On Behalf Of
> Fan, Jeff
> Sent: Thursday, June 08, 2017 1:34 PM
> To: Leo Duran; edk2-devel@lists.01.org
> Cc: Justen, Jordan L; Gao, Liming
> Subject: Re: [edk2] [PATCH v3 2/2] UefiCpuPkg: Modify
> GetProcessorLocationByApicId() to support AMD.
>
> Leo,
>
> 1. If Intel SDM supports the ExtendedCpuIdIndex >=
> CPUID_AMD_PROCESSOR_TOPOLOGY(0x8000001E) in the future, the
> following code may cause unexpected result for Intel processor.
> if (MaxExtendedCpuIdIndex >= CPUID_AMD_PROCESSOR_TOPOLOGY)
> May we use another way to check AMD or Intel processor?
[Duran, Leo] Any specific suggestions? Thanks.
>
> 2. Goto Statements should not be used (in general) except for error handling
> (https://github.com/tianocore-
> docs/Docs/raw/master/Specifications/CCS_2_1_Draft.pdf)
[Duran, Leo] OK, I will not use 'goto' in this case.
>
> Thanks!
> Jeff
>
> -----Original Message-----
> From: Leo Duran [mailto:leo.duran@amd.com]
> Sent: Tuesday, June 06, 2017 11:59 PM
> To: edk2-devel@lists.01.org
> Cc: Leo Duran; Justen, Jordan L; Fan, Jeff; Gao, Liming; Brijesh Singh
> Subject: [PATCH v3 2/2] UefiCpuPkg: Modify GetProcessorLocationByApicId()
> to support AMD.
>
> Cc: Jordan Justen <jordan.l.justen@intel.com>
> Cc: Jeff Fan <jeff.fan@intel.com>
> Cc: Liming Gao <liming.gao@intel.com>
> Cc: Brijesh Singh <brijesh.singh@amd.com>
> Contributed-under: TianoCore Contribution Agreement 1.0
> Signed-off-by: Leo Duran <leo.duran@amd.com>
> ---
> UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c | 130
> +++++++++++++++------
> .../BaseXApicX2ApicLib/BaseXApicX2ApicLib.c | 130 +++++++++++++++--
> ----
> 2 files changed, 184 insertions(+), 76 deletions(-) mode change 100644 =>
> 100755 UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c
>
> diff --git a/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c
> b/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c
> old mode 100644
> new mode 100755
> index f81bbb2..02dfabc
> --- a/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c
> +++ b/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c
> @@ -4,6 +4,8 @@
> This local APIC library instance supports xAPIC mode only.
>
> Copyright (c) 2010 - 2016, Intel Corporation. All rights reserved.<BR>
> + Copyright (c) 2017, AMD Inc. All rights reserved.<BR>
> +
> This program and the accompanying materials
> are licensed and made available under the terms and conditions of the BSD
> License
> which accompanies this distribution. The full text of the license may be
> found at @@ -15,6 +17,7 @@ **/
>
> #include <Register/Cpuid.h>
> +#include <Register/Amd/Cpuid.h>
> #include <Register/Msr.h>
> #include <Register/LocalApic.h>
>
> @@ -966,20 +969,29 @@ GetProcessorLocationByApicId (
> OUT UINT32 *Thread OPTIONAL
> )
> {
> - BOOLEAN TopologyLeafSupported;
> - UINTN ThreadBits;
> - UINTN CoreBits;
> - CPUID_VERSION_INFO_EBX VersionInfoEbx;
> - CPUID_VERSION_INFO_EDX VersionInfoEdx;
> - CPUID_CACHE_PARAMS_EAX CacheParamsEax;
> - CPUID_EXTENDED_TOPOLOGY_EAX ExtendedTopologyEax;
> - CPUID_EXTENDED_TOPOLOGY_EBX ExtendedTopologyEbx;
> - CPUID_EXTENDED_TOPOLOGY_ECX ExtendedTopologyEcx;
> - UINT32 MaxCpuIdIndex;
> - UINT32 SubIndex;
> - UINTN LevelType;
> - UINT32 MaxLogicProcessorsPerPackage;
> - UINT32 MaxCoresPerPackage;
> + CPUID_VERSION_INFO_EBX VersionInfoEbx;
> + CPUID_VERSION_INFO_EDX VersionInfoEdx;
> + CPUID_CACHE_PARAMS_EAX CacheParamsEax;
> + CPUID_EXTENDED_TOPOLOGY_EAX ExtendedTopologyEax;
> + CPUID_EXTENDED_TOPOLOGY_EBX ExtendedTopologyEbx;
> + CPUID_EXTENDED_TOPOLOGY_ECX ExtendedTopologyEcx;
> + CPUID_AMD_EXTENDED_CPU_SIG_ECX AmdExtendedCpuSigEcx;
> + CPUID_AMD_PROCESSOR_TOPOLOGY_EBX AmdProcessorTopologyEbx;
> + CPUID_AMD_PROCESSOR_TOPOLOGY_ECX AmdProcessorTopologyEcx;
> + CPUID_AMD_VIR_PHY_ADDRESS_SIZE_ECX AmdVirPhyAddressSizeEcx;
> + UINT32 MaxStandardCpuIdIndex;
> + UINT32 MaxExtendedCpuIdIndex;
> + UINT32 SubIndex;
> + UINTN LevelType;
> + UINT32 MaxLogicProcessorsPerPackage;
> + UINT32 MaxCoresPerPackage;
> + UINT32 MaxThreadPerPackageMask;
> + UINT32 ActualThreadPerPackageMask;
> + UINT32 MaxCoresPerNode;
> + UINT32 CorePerNodeMask;
> + UINT32 ApicIdShift;
> + UINTN ThreadBits;
> + UINTN CoreBits;
>
> //
> // Check if the processor is capable of supporting more than one logical
> processor.
> @@ -987,10 +999,10 @@ GetProcessorLocationByApicId (
> AsmCpuid(CPUID_VERSION_INFO, NULL, NULL, NULL,
> &VersionInfoEdx.Uint32);
> if (VersionInfoEdx.Bits.HTT == 0) {
> if (Thread != NULL) {
> - *Thread = 0;
> + *Thread = 0;
> }
> if (Core != NULL) {
> - *Core = 0;
> + *Core = 0;
> }
> if (Package != NULL) {
> *Package = 0;
> @@ -1002,20 +1014,16 @@ GetProcessorLocationByApicId (
> CoreBits = 0;
>
> //
> - // Assume three-level mapping of APIC ID: Package:Core:SMT.
> + // Get the max index of CPUID
> //
> - TopologyLeafSupported = FALSE;
> -
> - //
> - // Get the max index of basic CPUID
> - //
> - AsmCpuid(CPUID_SIGNATURE, &MaxCpuIdIndex, NULL, NULL, NULL);
> + AsmCpuid(CPUID_SIGNATURE, &MaxStandardCpuIdIndex, NULL, NULL,
> NULL);
> + AsmCpuid(CPUID_EXTENDED_FUNCTION, &MaxExtendedCpuIdIndex,
> NULL, NULL,
> + NULL);
>
> //
> // If the extended topology enumeration leaf is available, it
> // is the preferred mechanism for enumerating topology.
> //
> - if (MaxCpuIdIndex >= CPUID_EXTENDED_TOPOLOGY) {
> + if (MaxStandardCpuIdIndex >= CPUID_EXTENDED_TOPOLOGY) {
> AsmCpuidEx(
> CPUID_EXTENDED_TOPOLOGY,
> 0,
> @@ -1030,8 +1038,6 @@ GetProcessorLocationByApicId (
> // supported on that processor.
> //
> if (ExtendedTopologyEbx.Uint32 != 0) {
> - TopologyLeafSupported = TRUE;
> -
> //
> // Sub-leaf index 0 (ECX= 0 as input) provides enumeration parameters to
> extract
> // the SMT sub-field of x2APIC ID.
> @@ -1061,31 +1067,79 @@ GetProcessorLocationByApicId (
> }
> SubIndex++;
> } while (LevelType !=
> CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID);
> + goto GetLocation;
> }
> }
>
> - if (!TopologyLeafSupported) {
> - AsmCpuid(CPUID_VERSION_INFO, NULL, &VersionInfoEbx.Uint32, NULL,
> NULL);
> - MaxLogicProcessorsPerPackage =
> VersionInfoEbx.Bits.MaximumAddressableIdsForLogicalProcessors;
> - if (MaxCpuIdIndex >= CPUID_CACHE_PARAMS) {
> - AsmCpuidEx(CPUID_CACHE_PARAMS, 0, &CacheParamsEax.Uint32,
> NULL, NULL, NULL);
> + AsmCpuid(CPUID_VERSION_INFO, NULL, &VersionInfoEbx.Uint32, NULL,
> + NULL); MaxLogicProcessorsPerPackage =
> + VersionInfoEbx.Bits.MaximumAddressableIdsForLogicalProcessors;
> +
> + if (MaxStandardCpuIdIndex >= CPUID_CACHE_PARAMS) {
> + AsmCpuidEx(CPUID_CACHE_PARAMS, 0, &CacheParamsEax.Uint32,
> NULL, NULL, NULL);
> + if (CacheParamsEax.Uint32 != 0) {
> MaxCoresPerPackage =
> CacheParamsEax.Bits.MaximumAddressableIdsForLogicalProcessors + 1;
> + goto GetBits;
> }
> - else {
> + }
> +
> + if (MaxExtendedCpuIdIndex >= CPUID_AMD_PROCESSOR_TOPOLOGY) {
> + AsmCpuid(CPUID_EXTENDED_CPU_SIG, NULL, NULL,
> &AmdExtendedCpuSigEcx.Uint32, NULL);
> + if (AmdExtendedCpuSigEcx.Bits.TopologyExtensions != 0) {
> + AsmCpuid(CPUID_AMD_PROCESSOR_TOPOLOGY, NULL,
> &AmdProcessorTopologyEbx.Uint32,
> + &AmdProcessorTopologyEcx.Uint32, NULL);
> +
> + MaxCoresPerPackage = MaxLogicProcessorsPerPackage /
> + (AmdProcessorTopologyEbx.Bits.ThreadsPerCore + 1);
> +
> //
> - // Must be a single-core processor.
> + // Account for actual thread count (e.g., SMT disabled)
> //
> - MaxCoresPerPackage = 1;
> + AsmCpuid(CPUID_VIR_PHY_ADDRESS_SIZE, NULL, NULL,
> &AmdVirPhyAddressSizeEcx.Uint32, NULL);
> + MaxThreadPerPackageMask = 1 <<
> AmdVirPhyAddressSizeEcx.Bits.ApicIdCoreIdSize;
> + ActualThreadPerPackageMask = 1;
> + while (ActualThreadPerPackageMask < MaxLogicProcessorsPerPackage)
> {
> + ActualThreadPerPackageMask <<= 1;
> + }
> +
> + if (ActualThreadPerPackageMask < MaxThreadPerPackageMask) {
> + MaxCoresPerNode = MaxCoresPerPackage /
> + (AmdProcessorTopologyEcx.Bits.NodesPerProcessor + 1);
> +
> + CorePerNodeMask = 1;
> + while (CorePerNodeMask < MaxCoresPerNode) {
> + CorePerNodeMask <<= 1;
> + }
> + CorePerNodeMask -= 1;
> +
> + ApicIdShift = 0;
> + do {
> + ApicIdShift += 1;
> + ActualThreadPerPackageMask <<= 1;
> + } while (ActualThreadPerPackageMask < MaxThreadPerPackageMask);
> +
> + //
> + // Adjust APIC Id to report concatenation of Package|Core|Thread.
> + //
> + InitialApicId = ((InitialApicId & ~CorePerNodeMask) >> ApicIdShift) |
> (InitialApicId & CorePerNodeMask);
> + }
> +
> + goto GetBits;
> }
> + }
> +
> + //
> + // Must be a single-core processor.
> + //
> + MaxCoresPerPackage = 1;
>
> - ThreadBits = (UINTN)(HighBitSet32(MaxLogicProcessorsPerPackage /
> MaxCoresPerPackage - 1) + 1);
> - CoreBits = (UINTN)(HighBitSet32(MaxCoresPerPackage - 1) + 1); }
> +GetBits:
> + ThreadBits = (UINTN)(HighBitSet32(MaxLogicProcessorsPerPackage /
> +MaxCoresPerPackage - 1) + 1);
> + CoreBits = (UINTN)(HighBitSet32(MaxCoresPerPackage - 1) + 1);
>
> +GetLocation:
> if (Thread != NULL) {
> - *Thread = InitialApicId & ((1 << ThreadBits) - 1);
> + *Thread = InitialApicId & ((1 << ThreadBits) - 1);
> }
> if (Core != NULL) {
> - *Core = (InitialApicId >> ThreadBits) & ((1 << CoreBits) - 1);
> + *Core = (InitialApicId >> ThreadBits) & ((1 << CoreBits) - 1);
> }
> if (Package != NULL) {
> *Package = (InitialApicId >> (ThreadBits + CoreBits)); diff --git
> a/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c
> b/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c
> index e690d2a..726e1e0 100644
> --- a/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c
> +++ b/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c
> @@ -5,6 +5,8 @@
> which have xAPIC and x2APIC modes.
>
> Copyright (c) 2010 - 2016, Intel Corporation. All rights reserved.<BR>
> + Copyright (c) 2017, AMD Inc. All rights reserved.<BR>
> +
> This program and the accompanying materials
> are licensed and made available under the terms and conditions of the BSD
> License
> which accompanies this distribution. The full text of the license may be
> found at @@ -16,6 +18,7 @@ **/
>
> #include <Register/Cpuid.h>
> +#include <Register/Amd/Cpuid.h>
> #include <Register/Msr.h>
> #include <Register/LocalApic.h>
>
> @@ -1061,20 +1064,29 @@ GetProcessorLocationByApicId (
> OUT UINT32 *Thread OPTIONAL
> )
> {
> - BOOLEAN TopologyLeafSupported;
> - UINTN ThreadBits;
> - UINTN CoreBits;
> - CPUID_VERSION_INFO_EBX VersionInfoEbx;
> - CPUID_VERSION_INFO_EDX VersionInfoEdx;
> - CPUID_CACHE_PARAMS_EAX CacheParamsEax;
> - CPUID_EXTENDED_TOPOLOGY_EAX ExtendedTopologyEax;
> - CPUID_EXTENDED_TOPOLOGY_EBX ExtendedTopologyEbx;
> - CPUID_EXTENDED_TOPOLOGY_ECX ExtendedTopologyEcx;
> - UINT32 MaxCpuIdIndex;
> - UINT32 SubIndex;
> - UINTN LevelType;
> - UINT32 MaxLogicProcessorsPerPackage;
> - UINT32 MaxCoresPerPackage;
> + CPUID_VERSION_INFO_EBX VersionInfoEbx;
> + CPUID_VERSION_INFO_EDX VersionInfoEdx;
> + CPUID_CACHE_PARAMS_EAX CacheParamsEax;
> + CPUID_EXTENDED_TOPOLOGY_EAX ExtendedTopologyEax;
> + CPUID_EXTENDED_TOPOLOGY_EBX ExtendedTopologyEbx;
> + CPUID_EXTENDED_TOPOLOGY_ECX ExtendedTopologyEcx;
> + CPUID_AMD_EXTENDED_CPU_SIG_ECX AmdExtendedCpuSigEcx;
> + CPUID_AMD_PROCESSOR_TOPOLOGY_EBX AmdProcessorTopologyEbx;
> + CPUID_AMD_PROCESSOR_TOPOLOGY_ECX AmdProcessorTopologyEcx;
> + CPUID_AMD_VIR_PHY_ADDRESS_SIZE_ECX AmdVirPhyAddressSizeEcx;
> + UINT32 MaxStandardCpuIdIndex;
> + UINT32 MaxExtendedCpuIdIndex;
> + UINT32 SubIndex;
> + UINTN LevelType;
> + UINT32 MaxLogicProcessorsPerPackage;
> + UINT32 MaxCoresPerPackage;
> + UINT32 MaxThreadPerPackageMask;
> + UINT32 ActualThreadPerPackageMask;
> + UINT32 MaxCoresPerNode;
> + UINT32 CorePerNodeMask;
> + UINT32 ApicIdShift;
> + UINTN ThreadBits;
> + UINTN CoreBits;
>
> //
> // Check if the processor is capable of supporting more than one logical
> processor.
> @@ -1082,10 +1094,10 @@ GetProcessorLocationByApicId (
> AsmCpuid(CPUID_VERSION_INFO, NULL, NULL, NULL,
> &VersionInfoEdx.Uint32);
> if (VersionInfoEdx.Bits.HTT == 0) {
> if (Thread != NULL) {
> - *Thread = 0;
> + *Thread = 0;
> }
> if (Core != NULL) {
> - *Core = 0;
> + *Core = 0;
> }
> if (Package != NULL) {
> *Package = 0;
> @@ -1097,20 +1109,16 @@ GetProcessorLocationByApicId (
> CoreBits = 0;
>
> //
> - // Assume three-level mapping of APIC ID: Package:Core:SMT.
> + // Get the max index of CPUID
> //
> - TopologyLeafSupported = FALSE;
> -
> - //
> - // Get the max index of basic CPUID
> - //
> - AsmCpuid(CPUID_SIGNATURE, &MaxCpuIdIndex, NULL, NULL, NULL);
> + AsmCpuid(CPUID_SIGNATURE, &MaxStandardCpuIdIndex, NULL, NULL,
> NULL);
> + AsmCpuid(CPUID_EXTENDED_FUNCTION, &MaxExtendedCpuIdIndex,
> NULL, NULL,
> + NULL);
>
> //
> // If the extended topology enumeration leaf is available, it
> // is the preferred mechanism for enumerating topology.
> //
> - if (MaxCpuIdIndex >= CPUID_EXTENDED_TOPOLOGY) {
> + if (MaxStandardCpuIdIndex >= CPUID_EXTENDED_TOPOLOGY) {
> AsmCpuidEx(
> CPUID_EXTENDED_TOPOLOGY,
> 0,
> @@ -1125,8 +1133,6 @@ GetProcessorLocationByApicId (
> // supported on that processor.
> //
> if (ExtendedTopologyEbx.Uint32 != 0) {
> - TopologyLeafSupported = TRUE;
> -
> //
> // Sub-leaf index 0 (ECX= 0 as input) provides enumeration parameters to
> extract
> // the SMT sub-field of x2APIC ID.
> @@ -1156,31 +1162,79 @@ GetProcessorLocationByApicId (
> }
> SubIndex++;
> } while (LevelType !=
> CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID);
> + goto GetLocation;
> }
> }
>
> - if (!TopologyLeafSupported) {
> - AsmCpuid(CPUID_VERSION_INFO, NULL, &VersionInfoEbx.Uint32, NULL,
> NULL);
> - MaxLogicProcessorsPerPackage =
> VersionInfoEbx.Bits.MaximumAddressableIdsForLogicalProcessors;
> - if (MaxCpuIdIndex >= CPUID_CACHE_PARAMS) {
> - AsmCpuidEx(CPUID_CACHE_PARAMS, 0, &CacheParamsEax.Uint32,
> NULL, NULL, NULL);
> + AsmCpuid(CPUID_VERSION_INFO, NULL, &VersionInfoEbx.Uint32, NULL,
> + NULL); MaxLogicProcessorsPerPackage =
> + VersionInfoEbx.Bits.MaximumAddressableIdsForLogicalProcessors;
> +
> + if (MaxStandardCpuIdIndex >= CPUID_CACHE_PARAMS) {
> + AsmCpuidEx(CPUID_CACHE_PARAMS, 0, &CacheParamsEax.Uint32,
> NULL, NULL, NULL);
> + if (CacheParamsEax.Uint32 != 0) {
> MaxCoresPerPackage =
> CacheParamsEax.Bits.MaximumAddressableIdsForLogicalProcessors + 1;
> + goto GetBits;
> }
> - else {
> + }
> +
> + if (MaxExtendedCpuIdIndex >= CPUID_AMD_PROCESSOR_TOPOLOGY) {
> + AsmCpuid(CPUID_EXTENDED_CPU_SIG, NULL, NULL,
> &AmdExtendedCpuSigEcx.Uint32, NULL);
> + if (AmdExtendedCpuSigEcx.Bits.TopologyExtensions != 0) {
> + AsmCpuid(CPUID_AMD_PROCESSOR_TOPOLOGY, NULL,
> &AmdProcessorTopologyEbx.Uint32,
> + &AmdProcessorTopologyEcx.Uint32, NULL);
> +
> + MaxCoresPerPackage = MaxLogicProcessorsPerPackage /
> + (AmdProcessorTopologyEbx.Bits.ThreadsPerCore + 1);
> +
> //
> - // Must be a single-core processor.
> + // Account for actual thread count (e.g., SMT disabled)
> //
> - MaxCoresPerPackage = 1;
> + AsmCpuid(CPUID_VIR_PHY_ADDRESS_SIZE, NULL, NULL,
> &AmdVirPhyAddressSizeEcx.Uint32, NULL);
> + MaxThreadPerPackageMask = 1 <<
> AmdVirPhyAddressSizeEcx.Bits.ApicIdCoreIdSize;
> + ActualThreadPerPackageMask = 1;
> + while (ActualThreadPerPackageMask < MaxLogicProcessorsPerPackage)
> {
> + ActualThreadPerPackageMask <<= 1;
> + }
> +
> + if (ActualThreadPerPackageMask < MaxThreadPerPackageMask) {
> + MaxCoresPerNode = MaxCoresPerPackage /
> + (AmdProcessorTopologyEcx.Bits.NodesPerProcessor + 1);
> +
> + CorePerNodeMask = 1;
> + while (CorePerNodeMask < MaxCoresPerNode) {
> + CorePerNodeMask <<= 1;
> + }
> + CorePerNodeMask -= 1;
> +
> + ApicIdShift = 0;
> + do {
> + ApicIdShift += 1;
> + ActualThreadPerPackageMask <<= 1;
> + } while (ActualThreadPerPackageMask < MaxThreadPerPackageMask);
> +
> + //
> + // Adjust APIC Id to report concatenation of Package|Core|Thread.
> + //
> + InitialApicId = ((InitialApicId & ~CorePerNodeMask) >> ApicIdShift) |
> (InitialApicId & CorePerNodeMask);
> + }
> +
> + goto GetBits;
> }
> + }
> +
> + //
> + // Must be a single-core processor.
> + //
> + MaxCoresPerPackage = 1;
>
> - ThreadBits = (UINTN)(HighBitSet32(MaxLogicProcessorsPerPackage /
> MaxCoresPerPackage - 1) + 1);
> - CoreBits = (UINTN)(HighBitSet32(MaxCoresPerPackage - 1) + 1); }
> +GetBits:
> + ThreadBits = (UINTN)(HighBitSet32(MaxLogicProcessorsPerPackage /
> +MaxCoresPerPackage - 1) + 1);
> + CoreBits = (UINTN)(HighBitSet32(MaxCoresPerPackage - 1) + 1);
>
> +GetLocation:
> if (Thread != NULL) {
> - *Thread = InitialApicId & ((1 << ThreadBits) - 1);
> + *Thread = InitialApicId & ((1 << ThreadBits) - 1);
> }
> if (Core != NULL) {
> - *Core = (InitialApicId >> ThreadBits) & ((1 << CoreBits) - 1);
> + *Core = (InitialApicId >> ThreadBits) & ((1 << CoreBits) - 1);
> }
> if (Package != NULL) {
> *Package = (InitialApicId >> (ThreadBits + CoreBits));
> --
> 2.7.4
>
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