[v2] target/riscv: Support Zve32x and Zve64x extensions

[PATCH v2 0/5] target/riscv: Support Zve32x and Zve64x extensions

Jason Chien posted 5 patches 1 month ago

Diff against v1 v3
Download series mbox

Patches applied successfully (tree, apply log)
git fetch https://github.com/patchew-project/qemu tags/patchew/20240325083346.16656-1-jason.chien@sifive.com

Maintainers: Palmer Dabbelt <palmer@dabbelt.com>, Alistair Francis <alistair.francis@wdc.com>, Bin Meng <bin.meng@windriver.com>, Weiwei Li <liwei1518@gmail.com>, Daniel Henrique Barboza <dbarboza@ventanamicro.com>, Liu Zhiwei <zhiwei_liu@linux.alibaba.com>

There is a newer version of this series

target/riscv/cpu.c                      |  4 +++
target/riscv/cpu_cfg.h                  |  2 ++
target/riscv/cpu_helper.c               |  2 +-
target/riscv/csr.c                      |  2 +-
target/riscv/gdbstub.c                  |  2 +-
target/riscv/insn_trans/trans_rvv.c.inc |  4 +--
target/riscv/tcg/tcg-cpu.c              | 33 ++++++++++++++-----------
7 files changed, 30 insertions(+), 19 deletions(-)

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[PATCH v2 0/5] target/riscv: Support Zve32x and Zve64x extensions

Posted by Jason Chien 1 month ago

This patch series adds the support for Zve32x and Zvx64x and makes vector
registers visible in GDB if any of the V/Zve*/Zvk* extensions is enabled.

v2:
    Rebase onto riscv-to-apply.next (commit 385e575).

Jason Chien (5):
  target/riscv: Add support for Zve32x extension
  target/riscv: Expose Zve32x extension to users
  target/riscv: Add support for Zve64x extension
  target/riscv: Expose Zve64x extension to users
  target/riscv: Relax vector register check in RISCV gdbstub

 target/riscv/cpu.c                      |  4 +++
 target/riscv/cpu_cfg.h                  |  2 ++
 target/riscv/cpu_helper.c               |  2 +-
 target/riscv/csr.c                      |  2 +-
 target/riscv/gdbstub.c                  |  2 +-
 target/riscv/insn_trans/trans_rvv.c.inc |  4 +--
 target/riscv/tcg/tcg-cpu.c              | 33 ++++++++++++++-----------
 7 files changed, 30 insertions(+), 19 deletions(-)

-- 
2.43.2