[v3] target/riscv: Support Zve32x and Zve64x extensions

[PATCH v3 0/3] target/riscv: Support Zve32x and Zve64x extensions

Jason Chien posted 3 patches 1 month ago

Diff against v1 v2
Download series mbox

Patches applied successfully (tree, apply log)
git fetch https://github.com/patchew-project/qemu tags/patchew/20240328022343.6871-1-jason.chien@sifive.com

Maintainers: Palmer Dabbelt <palmer@dabbelt.com>, Alistair Francis <alistair.francis@wdc.com>, Bin Meng <bin.meng@windriver.com>, Weiwei Li <liwei1518@gmail.com>, Daniel Henrique Barboza <dbarboza@ventanamicro.com>, Liu Zhiwei <zhiwei_liu@linux.alibaba.com>

target/riscv/cpu.c                      |  4 +++
target/riscv/cpu_cfg.h                  |  2 ++
target/riscv/cpu_helper.c               |  2 +-
target/riscv/csr.c                      |  2 +-
target/riscv/gdbstub.c                  |  2 +-
target/riscv/insn_trans/trans_rvv.c.inc |  4 +--
target/riscv/tcg/tcg-cpu.c              | 33 ++++++++++++++-----------
7 files changed, 30 insertions(+), 19 deletions(-)

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[PATCH v3 0/3] target/riscv: Support Zve32x and Zve64x extensions

Posted by Jason Chien 1 month ago

This patch series adds the support for Zve32x and Zvx64x and makes vector
registers visible in GDB if any of the V/Zve*/Zvk* extensions is enabled.

v2:
    Rebase onto riscv-to-apply.next (commit 385e575).
v3:
    Spuash patch 2 into patch 1.
    Spuash patch 4 into patch 3.

Jason Chien (3):
  target/riscv: Add support for Zve32x extension
  target/riscv: Add support for Zve64x extension
  target/riscv: Relax vector register check in RISCV gdbstub

 target/riscv/cpu.c                      |  4 +++
 target/riscv/cpu_cfg.h                  |  2 ++
 target/riscv/cpu_helper.c               |  2 +-
 target/riscv/csr.c                      |  2 +-
 target/riscv/gdbstub.c                  |  2 +-
 target/riscv/insn_trans/trans_rvv.c.inc |  4 +--
 target/riscv/tcg/tcg-cpu.c              | 33 ++++++++++++++-----------
 7 files changed, 30 insertions(+), 19 deletions(-)

-- 
2.43.2

Re: [PATCH v3 0/3] target/riscv: Support Zve32x and Zve64x extensions

Posted by Jason Chien 2 weeks, 5 days ago

Ping.

Jason Chien <jason.chien@sifive.com> 於 2024年3月28日 週四 上午10:23寫道：

> This patch series adds the support for Zve32x and Zvx64x and makes vector
> registers visible in GDB if any of the V/Zve*/Zvk* extensions is enabled.
>
> v2:
>     Rebase onto riscv-to-apply.next (commit 385e575).
> v3:
>     Spuash patch 2 into patch 1.
>     Spuash patch 4 into patch 3.
>
> Jason Chien (3):
>   target/riscv: Add support for Zve32x extension
>   target/riscv: Add support for Zve64x extension
>   target/riscv: Relax vector register check in RISCV gdbstub
>
>  target/riscv/cpu.c                      |  4 +++
>  target/riscv/cpu_cfg.h                  |  2 ++
>  target/riscv/cpu_helper.c               |  2 +-
>  target/riscv/csr.c                      |  2 +-
>  target/riscv/gdbstub.c                  |  2 +-
>  target/riscv/insn_trans/trans_rvv.c.inc |  4 +--
>  target/riscv/tcg/tcg-cpu.c              | 33 ++++++++++++++-----------
>  7 files changed, 30 insertions(+), 19 deletions(-)
>
> --
> 2.43.2
>
>

Re: [PATCH v3 0/3] target/riscv: Support Zve32x and Zve64x extensions

Posted by Daniel Henrique Barboza 2 weeks, 5 days ago

Hi Jason,


We're in the middle of code freeze for the incoming 9.0 release. In this
period the maintainer will only queue bug fixes.

Your support is a new feature, so it'll only be pushed after the release is
done. Current ETA for the release is Apr 16th if there's no rc4. A safe
bet is to expect Alistair to queue the patches in the start of May.


Thanks,

Daniel



Perhaps we should start advertising the freeze dates more clearly in the
qemu-riscv ML.

On 4/9/24 03:29, Jason Chien wrote:
> Ping.
> 
> Jason Chien <jason.chien@sifive.com <mailto:jason.chien@sifive.com>> 於 2024年3月28日 週四 上午10:23寫道：
> 
>     This patch series adds the support for Zve32x and Zvx64x and makes vector
>     registers visible in GDB if any of the V/Zve*/Zvk* extensions is enabled.
> 
>     v2:
>          Rebase onto riscv-to-apply.next (commit 385e575).
>     v3:
>          Spuash patch 2 into patch 1.
>          Spuash patch 4 into patch 3.
> 
>     Jason Chien (3):
>        target/riscv: Add support for Zve32x extension
>        target/riscv: Add support for Zve64x extension
>        target/riscv: Relax vector register check in RISCV gdbstub
> 
>       target/riscv/cpu.c                      |  4 +++
>       target/riscv/cpu_cfg.h                  |  2 ++
>       target/riscv/cpu_helper.c               |  2 +-
>       target/riscv/csr.c                      |  2 +-
>       target/riscv/gdbstub.c                  |  2 +-
>       target/riscv/insn_trans/trans_rvv.c.inc |  4 +--
>       target/riscv/tcg/tcg-cpu.c              | 33 ++++++++++++++-----------
>       7 files changed, 30 insertions(+), 19 deletions(-)
> 
>     -- 
>     2.43.2
>