[v1] Fix PSIHB interrupts init PQ state

[PATCH 0/2] Fix PSIHB interrupts init PQ state

Frederic Barrat posted 2 patches 10 months, 3 weeks ago

Diff against v2
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git fetch https://github.com/patchew-project/qemu tags/patchew/20230630144243.214976-1-fbarrat@linux.ibm.com

Maintainers: "Cédric Le Goater" <clg@kaod.org>, "Frédéric Barrat" <fbarrat@linux.ibm.com>, Nicholas Piggin <npiggin@gmail.com>

There is a newer version of this series

hw/intc/xive.c        | 8 ++++++--
hw/ppc/pnv_psi.c      | 2 ++
include/hw/ppc/xive.h | 1 +
3 files changed, 9 insertions(+), 2 deletions(-)

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[PATCH 0/2] Fix PSIHB interrupts init PQ state

Posted by Frederic Barrat 10 months, 3 weeks ago

On P9 and 10, the real hardware defines the PQ state of the PSIHB
interrupts to be 0b00. Qemu defaults to 0b01.

It doesn't matter to skiboot, which doesn't rely on it and explicitly
masks the interrupts during intialization. But this patch fixes it,
just in case some other hypervisor checks it.


Frederic Barrat (2):
  pnv/xive: Add property on xive sources to define PQ state on reset
  pnv/psi: Initialize the PSIHB interrupts to match hardware

 hw/intc/xive.c        | 8 ++++++--
 hw/ppc/pnv_psi.c      | 2 ++
 include/hw/ppc/xive.h | 1 +
 3 files changed, 9 insertions(+), 2 deletions(-)

-- 
2.41.0