[v2] {tcg,aarch64}: Add TLB_CHECK_ALIGNED

[PATCH v2 0/9] {tcg,aarch64}: Add TLB_CHECK_ALIGNED

Richard Henderson posted 9 patches 10 months, 1 week ago

Diff against v1
Download series mbox

Failed in applying to current master (apply log)

include/exec/cpu-all.h     |  29 ++++++--
include/exec/cpu-defs.h    |   9 +++
include/exec/memattrs.h    |  12 ----
accel/tcg/cputlb.c         | 142 +++++++++++++++++++++++++------------
target/arm/ptw.c           |  28 ++++++++
target/arm/tcg/hflags.c    |  34 ++++++++-
target/arm/tcg/translate.c |   8 +--
target/sparc/mmu_helper.c  |   2 +-
tcg/tcg-op-ldst.c          |   2 +-
9 files changed, 190 insertions(+), 76 deletions(-)

Expand all Fold all

[PATCH v2 0/9] {tcg,aarch64}: Add TLB_CHECK_ALIGNED

Posted by Richard Henderson 10 months, 1 week ago

v1: https://lore.kernel.org/qemu-devel/20230223204342.1093632-1-richard.henderson@linaro.org/

Prerequisites and some of v1 merged since February.
Split TLB_DISCARD_WRITE renumber to a separate patch,
since there are now dependencies in tcg/.


r~


Richard Henderson (9):
  accel/tcg: Store some tlb flags in CPUTLBEntryFull
  accel/tcg: Move TLB_WATCHPOINT to TLB_SLOW_FLAGS_MASK
  accel/tcg: Renumber TLB_DISCARD_WRITE
  target/arm: Support 32-byte alignment in pow2_align
  exec/memattrs: Remove target_tlb_bit*
  accel/tcg: Add tlb_fill_flags to CPUTLBEntryFull
  accel/tcg: Add TLB_CHECK_ALIGNED
  target/arm: Do memory type alignment check when translation disabled
  target/arm: Do memory type alignment check when translation enabled

 include/exec/cpu-all.h     |  29 ++++++--
 include/exec/cpu-defs.h    |   9 +++
 include/exec/memattrs.h    |  12 ----
 accel/tcg/cputlb.c         | 142 +++++++++++++++++++++++++------------
 target/arm/ptw.c           |  28 ++++++++
 target/arm/tcg/hflags.c    |  34 ++++++++-
 target/arm/tcg/translate.c |   8 +--
 target/sparc/mmu_helper.c  |   2 +-
 tcg/tcg-op-ldst.c          |   2 +-
 9 files changed, 190 insertions(+), 76 deletions(-)

-- 
2.34.1