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Wed, 21 Jun 2023 05:19:05 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v2 1/9] accel/tcg: Store some tlb flags in CPUTLBEntryFull Date: Wed, 21 Jun 2023 14:18:54 +0200 Message-Id: <20230621121902.1392277-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230621121902.1392277-1-richard.henderson@linaro.org> References: <20230621121902.1392277-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::229; envelope-from=richard.henderson@linaro.org; helo=mail-lj1-x229.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1687349994325100001 Content-Type: text/plain; charset="utf-8" We have run out of bits we can use within the CPUTLBEntry comparators, as TLB_FLAGS_MASK cannot overlap alignment. Store slow_flags[] in CPUTLBEntryFull, and merge with the flags from the comparator. A new TLB_FORCE_SLOW bit is set within the comparator as an indication that the slow path must be used. Move TLB_BSWAP to TLB_SLOW_FLAGS_MASK. Since we are out of bits, we cannot create a new bit without moving an old one. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- include/exec/cpu-all.h | 21 +++++++-- include/exec/cpu-defs.h | 6 +++ accel/tcg/cputlb.c | 96 ++++++++++++++++++++++++----------------- 3 files changed, 80 insertions(+), 43 deletions(-) diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index 09bf4c0cc6..4422f4bb07 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -327,17 +327,30 @@ CPUArchState *cpu_copy(CPUArchState *env); #define TLB_MMIO (1 << (TARGET_PAGE_BITS_MIN - 3)) /* Set if TLB entry contains a watchpoint. */ #define TLB_WATCHPOINT (1 << (TARGET_PAGE_BITS_MIN - 4)) -/* Set if TLB entry requires byte swap. */ -#define TLB_BSWAP (1 << (TARGET_PAGE_BITS_MIN - 5)) +/* Set if the slow path must be used; more flags in CPUTLBEntryFull. */ +#define TLB_FORCE_SLOW (1 << (TARGET_PAGE_BITS_MIN - 5)) /* Set if TLB entry writes ignored. */ #define TLB_DISCARD_WRITE (1 << (TARGET_PAGE_BITS_MIN - 6)) =20 -/* Use this mask to check interception with an alignment mask +/* + * Use this mask to check interception with an alignment mask * in a TCG backend. */ #define TLB_FLAGS_MASK \ (TLB_INVALID_MASK | TLB_NOTDIRTY | TLB_MMIO \ - | TLB_WATCHPOINT | TLB_BSWAP | TLB_DISCARD_WRITE) + | TLB_WATCHPOINT | TLB_FORCE_SLOW | TLB_DISCARD_WRITE) + +/* + * Flags stored in CPUTLBEntryFull.slow_flags[x]. + * TLB_FORCE_SLOW must be set in CPUTLBEntry.addr_idx[x]. + */ +/* Set if TLB entry requires byte swap. */ +#define TLB_BSWAP (1 << 0) + +#define TLB_SLOW_FLAGS_MASK TLB_BSWAP + +/* The two sets of flags must not overlap. */ +QEMU_BUILD_BUG_ON(TLB_FLAGS_MASK & TLB_SLOW_FLAGS_MASK); =20 /** * tlb_hit_page: return true if page aligned @addr is a hit against the diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h index 4cb77c8dec..c174d5371a 100644 --- a/include/exec/cpu-defs.h +++ b/include/exec/cpu-defs.h @@ -124,6 +124,12 @@ typedef struct CPUTLBEntryFull { /* @lg_page_size contains the log2 of the page size. */ uint8_t lg_page_size; =20 + /* + * Additional tlb flags for use by the slow path. If non-zero, + * the corresponding CPUTLBEntry comparator must have TLB_FORCE_SLOW. + */ + uint8_t slow_flags[3]; + /* * Allow target-specific additions to this structure. * This may be used to cache items from the guest cpu diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 14ce97c33b..b40ce5ea0f 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -1110,6 +1110,24 @@ static void tlb_add_large_page(CPUArchState *env, in= t mmu_idx, env_tlb(env)->d[mmu_idx].large_page_mask =3D lp_mask; } =20 +static inline void tlb_set_compare(CPUTLBEntryFull *full, CPUTLBEntry *ent, + target_ulong address, int flags, + MMUAccessType access_type, bool enable) +{ + if (enable) { + address |=3D flags & TLB_FLAGS_MASK; + flags &=3D TLB_SLOW_FLAGS_MASK; + if (flags) { + address |=3D TLB_FORCE_SLOW; + } + } else { + address =3D -1; + flags =3D 0; + } + ent->addr_idx[access_type] =3D address; + full->slow_flags[access_type] =3D flags; +} + /* * Add a new TLB entry. At most one entry for a given virtual address * is permitted. Only a single TARGET_PAGE_SIZE region is mapped, the @@ -1125,9 +1143,7 @@ void tlb_set_page_full(CPUState *cpu, int mmu_idx, CPUTLB *tlb =3D env_tlb(env); CPUTLBDesc *desc =3D &tlb->d[mmu_idx]; MemoryRegionSection *section; - unsigned int index; - target_ulong address; - target_ulong write_address; + unsigned int index, read_flags, write_flags; uintptr_t addend; CPUTLBEntry *te, tn; hwaddr iotlb, xlat, sz, paddr_page; @@ -1156,13 +1172,13 @@ void tlb_set_page_full(CPUState *cpu, int mmu_idx, " prot=3D%x idx=3D%d\n", vaddr, full->phys_addr, prot, mmu_idx); =20 - address =3D vaddr_page; + read_flags =3D 0; if (full->lg_page_size < TARGET_PAGE_BITS) { /* Repeat the MMU check and TLB fill on every access. */ - address |=3D TLB_INVALID_MASK; + read_flags |=3D TLB_INVALID_MASK; } if (full->attrs.byte_swap) { - address |=3D TLB_BSWAP; + read_flags |=3D TLB_BSWAP; } =20 is_ram =3D memory_region_is_ram(section->mr); @@ -1176,7 +1192,7 @@ void tlb_set_page_full(CPUState *cpu, int mmu_idx, addend =3D 0; } =20 - write_address =3D address; + write_flags =3D read_flags; if (is_ram) { iotlb =3D memory_region_get_ram_addr(section->mr) + xlat; /* @@ -1185,9 +1201,9 @@ void tlb_set_page_full(CPUState *cpu, int mmu_idx, */ if (prot & PAGE_WRITE) { if (section->readonly) { - write_address |=3D TLB_DISCARD_WRITE; + write_flags |=3D TLB_DISCARD_WRITE; } else if (cpu_physical_memory_is_clean(iotlb)) { - write_address |=3D TLB_NOTDIRTY; + write_flags |=3D TLB_NOTDIRTY; } } } else { @@ -1198,9 +1214,9 @@ void tlb_set_page_full(CPUState *cpu, int mmu_idx, * Reads to romd devices go through the ram_ptr found above, * but of course reads to I/O must go through MMIO. */ - write_address |=3D TLB_MMIO; + write_flags |=3D TLB_MMIO; if (!is_romd) { - address =3D write_address; + read_flags =3D write_flags; } } =20 @@ -1253,36 +1269,30 @@ void tlb_set_page_full(CPUState *cpu, int mmu_idx, * vaddr we add back in io_readx()/io_writex()/get_page_addr_code(). */ desc->fulltlb[index] =3D *full; - desc->fulltlb[index].xlat_section =3D iotlb - vaddr_page; - desc->fulltlb[index].phys_addr =3D paddr_page; + full =3D &desc->fulltlb[index]; + full->xlat_section =3D iotlb - vaddr_page; + full->phys_addr =3D paddr_page; =20 /* Now calculate the new entry */ tn.addend =3D addend - vaddr_page; - if (prot & PAGE_READ) { - tn.addr_read =3D address; - if (wp_flags & BP_MEM_READ) { - tn.addr_read |=3D TLB_WATCHPOINT; - } - } else { - tn.addr_read =3D -1; - } =20 - if (prot & PAGE_EXEC) { - tn.addr_code =3D address; - } else { - tn.addr_code =3D -1; - } + tlb_set_compare(full, &tn, vaddr_page, read_flags, + MMU_INST_FETCH, prot & PAGE_EXEC); =20 - tn.addr_write =3D -1; - if (prot & PAGE_WRITE) { - tn.addr_write =3D write_address; - if (prot & PAGE_WRITE_INV) { - tn.addr_write |=3D TLB_INVALID_MASK; - } - if (wp_flags & BP_MEM_WRITE) { - tn.addr_write |=3D TLB_WATCHPOINT; - } + if (wp_flags & BP_MEM_READ) { + read_flags |=3D TLB_WATCHPOINT; } + tlb_set_compare(full, &tn, vaddr_page, read_flags, + MMU_DATA_LOAD, prot & PAGE_READ); + + if (prot & PAGE_WRITE_INV) { + write_flags |=3D TLB_INVALID_MASK; + } + if (wp_flags & BP_MEM_WRITE) { + write_flags |=3D TLB_WATCHPOINT; + } + tlb_set_compare(full, &tn, vaddr_page, write_flags, + MMU_DATA_STORE, prot & PAGE_WRITE); =20 copy_tlb_helper_locked(te, &tn); tlb_n_used_entries_inc(env, mmu_idx); @@ -1512,7 +1522,8 @@ static int probe_access_internal(CPUArchState *env, t= arget_ulong addr, CPUTLBEntry *entry =3D tlb_entry(env, mmu_idx, addr); target_ulong tlb_addr =3D tlb_read_idx(entry, access_type); target_ulong page_addr =3D addr & TARGET_PAGE_MASK; - int flags =3D TLB_FLAGS_MASK; + int flags =3D TLB_FLAGS_MASK & ~TLB_FORCE_SLOW; + CPUTLBEntryFull *full; =20 if (!tlb_hit_page(tlb_addr, page_addr)) { if (!victim_tlb_hit(env, mmu_idx, index, access_type, page_addr)) { @@ -1541,7 +1552,8 @@ static int probe_access_internal(CPUArchState *env, t= arget_ulong addr, } flags &=3D tlb_addr; =20 - *pfull =3D &env_tlb(env)->d[mmu_idx].fulltlb[index]; + *pfull =3D full =3D &env_tlb(env)->d[mmu_idx].fulltlb[index]; + flags |=3D full->slow_flags[access_type]; =20 /* Fold all "mmio-like" bits into TLB_MMIO. This is not RAM. */ if (unlikely(flags & ~(TLB_WATCHPOINT | TLB_NOTDIRTY))) { @@ -1764,6 +1776,8 @@ static bool mmu_lookup1(CPUArchState *env, MMULookupP= ageData *data, CPUTLBEntry *entry =3D tlb_entry(env, mmu_idx, addr); target_ulong tlb_addr =3D tlb_read_idx(entry, access_type); bool maybe_resized =3D false; + CPUTLBEntryFull *full; + int flags; =20 /* If the TLB entry is for a different page, reload and try again. */ if (!tlb_hit(tlb_addr, addr)) { @@ -1777,8 +1791,12 @@ static bool mmu_lookup1(CPUArchState *env, MMULookup= PageData *data, tlb_addr =3D tlb_read_idx(entry, access_type) & ~TLB_INVALID_MASK; } =20 - data->flags =3D tlb_addr & TLB_FLAGS_MASK; - data->full =3D &env_tlb(env)->d[mmu_idx].fulltlb[index]; + full =3D &env_tlb(env)->d[mmu_idx].fulltlb[index]; + flags =3D tlb_addr & (TLB_FLAGS_MASK & ~TLB_FORCE_SLOW); + flags |=3D full->slow_flags[access_type]; + + data->full =3D full; + data->flags =3D flags; /* Compute haddr speculatively; depending on flags it might be invalid= . */ data->haddr =3D (void *)((uintptr_t)addr + entry->addend); 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Wed, 21 Jun 2023 05:19:06 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v2 2/9] accel/tcg: Move TLB_WATCHPOINT to TLB_SLOW_FLAGS_MASK Date: Wed, 21 Jun 2023 14:18:55 +0200 Message-Id: <20230621121902.1392277-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230621121902.1392277-1-richard.henderson@linaro.org> References: <20230621121902.1392277-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::12f; envelope-from=richard.henderson@linaro.org; helo=mail-lf1-x12f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1687350069946100001 Content-Type: text/plain; charset="utf-8" This frees up one bit of the primary tlb flags without impacting the TLB_NOTDIRTY logic. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- include/exec/cpu-all.h | 8 ++++---- accel/tcg/cputlb.c | 18 ++++++++++++++---- 2 files changed, 18 insertions(+), 8 deletions(-) diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index 4422f4bb07..b5618613cc 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -325,8 +325,6 @@ CPUArchState *cpu_copy(CPUArchState *env); #define TLB_NOTDIRTY (1 << (TARGET_PAGE_BITS_MIN - 2)) /* Set if TLB entry is an IO callback. */ #define TLB_MMIO (1 << (TARGET_PAGE_BITS_MIN - 3)) -/* Set if TLB entry contains a watchpoint. */ -#define TLB_WATCHPOINT (1 << (TARGET_PAGE_BITS_MIN - 4)) /* Set if the slow path must be used; more flags in CPUTLBEntryFull. */ #define TLB_FORCE_SLOW (1 << (TARGET_PAGE_BITS_MIN - 5)) /* Set if TLB entry writes ignored. */ @@ -338,7 +336,7 @@ CPUArchState *cpu_copy(CPUArchState *env); */ #define TLB_FLAGS_MASK \ (TLB_INVALID_MASK | TLB_NOTDIRTY | TLB_MMIO \ - | TLB_WATCHPOINT | TLB_FORCE_SLOW | TLB_DISCARD_WRITE) + | TLB_FORCE_SLOW | TLB_DISCARD_WRITE) =20 /* * Flags stored in CPUTLBEntryFull.slow_flags[x]. @@ -346,8 +344,10 @@ CPUArchState *cpu_copy(CPUArchState *env); */ /* Set if TLB entry requires byte swap. */ #define TLB_BSWAP (1 << 0) +/* Set if TLB entry contains a watchpoint. */ +#define TLB_WATCHPOINT (1 << 1) =20 -#define TLB_SLOW_FLAGS_MASK TLB_BSWAP +#define TLB_SLOW_FLAGS_MASK (TLB_BSWAP | TLB_WATCHPOINT) =20 /* The two sets of flags must not overlap. */ QEMU_BUILD_BUG_ON(TLB_FLAGS_MASK & TLB_SLOW_FLAGS_MASK); diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index b40ce5ea0f..152c4e9994 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -1984,7 +1984,7 @@ static void *atomic_mmu_lookup(CPUArchState *env, tar= get_ulong addr, */ goto stop_the_world; } - /* Collect TLB_WATCHPOINT for read. */ + /* Collect tlb flags for read. */ tlb_addr |=3D tlbe->addr_read; =20 /* Notice an IO access or a needs-MMU-lookup access */ @@ -2001,9 +2001,19 @@ static void *atomic_mmu_lookup(CPUArchState *env, ta= rget_ulong addr, notdirty_write(env_cpu(env), addr, size, full, retaddr); } =20 - if (unlikely(tlb_addr & TLB_WATCHPOINT)) { - cpu_check_watchpoint(env_cpu(env), addr, size, full->attrs, - BP_MEM_READ | BP_MEM_WRITE, retaddr); + if (unlikely(tlb_addr & TLB_FORCE_SLOW)) { + int wp_flags =3D 0; + + if (full->slow_flags[MMU_DATA_STORE] & TLB_WATCHPOINT) { + wp_flags |=3D BP_MEM_WRITE; + } + if (full->slow_flags[MMU_DATA_LOAD] & TLB_WATCHPOINT) { + wp_flags |=3D BP_MEM_READ; + } + if (wp_flags) { + cpu_check_watchpoint(env_cpu(env), addr, size, + full->attrs, wp_flags, retaddr); + } } =20 return hostaddr; --=20 2.34.1 From nobody Tue May 14 17:54:18 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1687350007; cv=none; d=zohomail.com; s=zohoarc; b=NPM9SQGjr4mn/kh6WfQCaGtyTu4xJabRB3o+fhKQCxJ04IYE1Pogs+3C3DE3t5GlI45MdE9su0rrQqCtQe+SI/8BN9q0kzyqJzeLhfjFaxfi419iAGjSW9cWCJH9E+qHDOK2gXjMGNv7sr8hompTQnrnkuH9r272OwP3bI7VXAU= ARC-Message-Signature: i=1; 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Wed, 21 Jun 2023 05:19:07 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v2 3/9] accel/tcg: Renumber TLB_DISCARD_WRITE Date: Wed, 21 Jun 2023 14:18:56 +0200 Message-Id: <20230621121902.1392277-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230621121902.1392277-1-richard.henderson@linaro.org> References: <20230621121902.1392277-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::12e; envelope-from=richard.henderson@linaro.org; helo=mail-lf1-x12e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1687350008633100007 Content-Type: text/plain; charset="utf-8" Move to fill a hole in the set of bits. Reduce the total number of tlb bits by 1. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- include/exec/cpu-all.h | 4 ++-- tcg/tcg-op-ldst.c | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index b5618613cc..8018ce783e 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -325,10 +325,10 @@ CPUArchState *cpu_copy(CPUArchState *env); #define TLB_NOTDIRTY (1 << (TARGET_PAGE_BITS_MIN - 2)) /* Set if TLB entry is an IO callback. */ #define TLB_MMIO (1 << (TARGET_PAGE_BITS_MIN - 3)) +/* Set if TLB entry writes ignored. */ +#define TLB_DISCARD_WRITE (1 << (TARGET_PAGE_BITS_MIN - 4)) /* Set if the slow path must be used; more flags in CPUTLBEntryFull. */ #define TLB_FORCE_SLOW (1 << (TARGET_PAGE_BITS_MIN - 5)) -/* Set if TLB entry writes ignored. */ -#define TLB_DISCARD_WRITE (1 << (TARGET_PAGE_BITS_MIN - 6)) =20 /* * Use this mask to check interception with an alignment mask diff --git a/tcg/tcg-op-ldst.c b/tcg/tcg-op-ldst.c index a4f51bfb6e..0fcc1618e5 100644 --- a/tcg/tcg-op-ldst.c +++ b/tcg/tcg-op-ldst.c @@ -39,7 +39,7 @@ static void check_max_alignment(unsigned a_bits) * The requested alignment cannot overlap the TLB flags. * FIXME: Must keep the count up-to-date with "exec/cpu-all.h". */ - tcg_debug_assert(a_bits + 6 <=3D tcg_ctx->page_bits); + tcg_debug_assert(a_bits + 5 <=3D tcg_ctx->page_bits); #endif } =20 --=20 2.34.1 From nobody Tue May 14 17:54:18 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1687350004; cv=none; d=zohomail.com; s=zohoarc; b=H5Oi9KzSJrqvY8JojvnFiXr2EClO49WpmxVY/RMvNwunW6mJ2WuNhE5qxQssIvaJRnQ0Hb6qEoK2Q+OnotO9jpSBPnG+IfKjf1uq20hPovpuBmm+c+UoMK3mngrMaEcjipyNrQ2ZPUVZUwNYYBFiUcA1MKv6+f8ANj9cBC5x9xE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1687350004; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=GpguwOP2tBZG1Q3kxp3nwyx4GamestPy42HvjJG3rb4=; b=NdT72xNsFj0N6PUwOJrC8Ot+2h5vMF3WXaQM4mgP8uU4xg5pniiSGDOgQBdjzJr4ypHqk9IneUIg8gMNQewTg6b6tVmZ55qQtkzn5wexmA+l9BwtNbf7xmLfLCU/wjCjBeJsm5aPSKP7pGQtFVs5s1inLmLcfiCOMTdn+xCqm40= ARC-Authentication-Results: i=1; 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Wed, 21 Jun 2023 05:19:08 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v2 4/9] target/arm: Support 32-byte alignment in pow2_align Date: Wed, 21 Jun 2023 14:18:57 +0200 Message-Id: <20230621121902.1392277-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230621121902.1392277-1-richard.henderson@linaro.org> References: <20230621121902.1392277-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::52d; envelope-from=richard.henderson@linaro.org; helo=mail-ed1-x52d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1687350005457100001 Content-Type: text/plain; charset="utf-8" Now that we have removed TARGET_PAGE_BITS_MIN-6 from TLB_FLAGS_MASK, we can test for 32-byte alignment. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/tcg/translate.c | 8 +------- 1 file changed, 1 insertion(+), 7 deletions(-) diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c index 13c88ba1b9..286497ebf9 100644 --- a/target/arm/tcg/translate.c +++ b/target/arm/tcg/translate.c @@ -900,13 +900,7 @@ static inline void store_reg_from_load(DisasContext *s= , int reg, TCGv_i32 var) MemOp pow2_align(unsigned i) { static const MemOp mop_align[] =3D { - 0, MO_ALIGN_2, MO_ALIGN_4, MO_ALIGN_8, MO_ALIGN_16, - /* - * FIXME: TARGET_PAGE_BITS_MIN affects TLB_FLAGS_MASK such - * that 256-bit alignment (MO_ALIGN_32) cannot be supported: - * see get_alignment_bits(). Enforce only 128-bit alignment for no= w. - */ - MO_ALIGN_16 + 0, MO_ALIGN_2, MO_ALIGN_4, MO_ALIGN_8, MO_ALIGN_16, MO_ALIGN_32 }; g_assert(i < ARRAY_SIZE(mop_align)); return mop_align[i]; --=20 2.34.1 From nobody Tue May 14 17:54:18 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1687350184; cv=none; d=zohomail.com; s=zohoarc; b=SnKHoCd2mzKH551tc6w1H8ScCua2gsHVo4HZupZEMnECkrd7gAOt7TD3YdRod2gLQ8QRCck/SFW03Qi7DMWxLDcktPeK6DH6sztTaUKEl/nUhMhFEkQ9LucarxFsdq20tvC3FkEyABNxvgDCnlGqqVom/Gq/gzOmMJb+3c89Pnw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1687350184; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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Wed, 21 Jun 2023 05:19:09 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v2 5/9] exec/memattrs: Remove target_tlb_bit* Date: Wed, 21 Jun 2023 14:18:58 +0200 Message-Id: <20230621121902.1392277-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230621121902.1392277-1-richard.henderson@linaro.org> References: <20230621121902.1392277-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::236; envelope-from=richard.henderson@linaro.org; helo=mail-lj1-x236.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1687350186224100005 These fields are no longer used since 937f224559. Target specific extensions to the page tables should be done with TARGET_PAGE_ENTRY_EXTRA. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- include/exec/memattrs.h | 10 ---------- 1 file changed, 10 deletions(-) diff --git a/include/exec/memattrs.h b/include/exec/memattrs.h index 9fb98bc1ef..1bd7b6c5ca 100644 --- a/include/exec/memattrs.h +++ b/include/exec/memattrs.h @@ -47,16 +47,6 @@ typedef struct MemTxAttrs { unsigned int requester_id:16; /* Invert endianness for this page */ unsigned int byte_swap:1; - /* - * The following are target-specific page-table bits. These are not - * related to actual memory transactions at all. However, this struct= ure - * is part of the tlb_fill interface, cached in the cputlb structure, - * and has unused bits. These fields will be read by target-specific - * helpers using env->iotlb[mmu_idx][tlb_index()].attrs.target_tlb_bit= N. - */ - unsigned int target_tlb_bit0 : 1; - unsigned int target_tlb_bit1 : 1; - unsigned int target_tlb_bit2 : 1; } MemTxAttrs; =20 /* Bus masters which don't specify any attributes will get this, --=20 2.34.1 From nobody Tue May 14 17:54:18 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1687350070; cv=none; d=zohomail.com; s=zohoarc; b=Lh2ZjyvIFx6o0+f2vzL5j7ru9PJ1GJNiIDS+jjjgovh7No7wh8Xd27wcxo09Kuf3QARGSyYd7VSFEQ6h9xP7FMDDenJyLzJpFOAET1cJngOHdD4lTi41Y2FHkl5nQi6FuZ2459qSg4VhbZzdLinUwPp106UVlsgzpnxXVHX9hTQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; 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Wed, 21 Jun 2023 05:19:10 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v2 6/9] accel/tcg: Add tlb_fill_flags to CPUTLBEntryFull Date: Wed, 21 Jun 2023 14:18:59 +0200 Message-Id: <20230621121902.1392277-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230621121902.1392277-1-richard.henderson@linaro.org> References: <20230621121902.1392277-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::529; envelope-from=richard.henderson@linaro.org; helo=mail-ed1-x529.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1687350072014100007 Allow the target to set tlb flags to apply to all of the comparators. Remove MemTxAttrs.byte_swap, as the bit is not relevant to memory transactions, only the page mapping. Adjust target/sparc to set TLB_BSWAP directly. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- include/exec/cpu-defs.h | 3 +++ include/exec/memattrs.h | 2 -- accel/tcg/cputlb.c | 5 +---- target/sparc/mmu_helper.c | 2 +- 4 files changed, 5 insertions(+), 7 deletions(-) diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h index c174d5371a..9d39252271 100644 --- a/include/exec/cpu-defs.h +++ b/include/exec/cpu-defs.h @@ -124,6 +124,9 @@ typedef struct CPUTLBEntryFull { /* @lg_page_size contains the log2 of the page size. */ uint8_t lg_page_size; =20 + /* Additional tlb flags requested by tlb_fill. */ + uint8_t tlb_fill_flags; + /* * Additional tlb flags for use by the slow path. If non-zero, * the corresponding CPUTLBEntry comparator must have TLB_FORCE_SLOW. diff --git a/include/exec/memattrs.h b/include/exec/memattrs.h index 1bd7b6c5ca..5300649c8c 100644 --- a/include/exec/memattrs.h +++ b/include/exec/memattrs.h @@ -45,8 +45,6 @@ typedef struct MemTxAttrs { unsigned int memory:1; /* Requester ID (for MSI for example) */ unsigned int requester_id:16; - /* Invert endianness for this page */ - unsigned int byte_swap:1; } MemTxAttrs; =20 /* Bus masters which don't specify any attributes will get this, diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 152c4e9994..61f4d94a4d 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -1172,14 +1172,11 @@ void tlb_set_page_full(CPUState *cpu, int mmu_idx, " prot=3D%x idx=3D%d\n", vaddr, full->phys_addr, prot, mmu_idx); =20 - read_flags =3D 0; + read_flags =3D full->tlb_fill_flags; if (full->lg_page_size < TARGET_PAGE_BITS) { /* Repeat the MMU check and TLB fill on every access. */ read_flags |=3D TLB_INVALID_MASK; } - if (full->attrs.byte_swap) { - read_flags |=3D TLB_BSWAP; - } =20 is_ram =3D memory_region_is_ram(section->mr); is_romd =3D memory_region_is_romd(section->mr); diff --git a/target/sparc/mmu_helper.c b/target/sparc/mmu_helper.c index 453498c670..11f03b74d2 100644 --- a/target/sparc/mmu_helper.c +++ b/target/sparc/mmu_helper.c @@ -580,7 +580,7 @@ static int get_physical_address_data(CPUSPARCState *env= , CPUTLBEntryFull *full, int do_fault =3D 0; =20 if (TTE_IS_IE(env->dtlb[i].tte)) { - full->attrs.byte_swap =3D true; + full->tlb_fill_flags |=3D TLB_BSWAP; } =20 /* access ok? */ --=20 2.34.1 From nobody Tue May 14 17:54:18 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1687349996; cv=none; d=zohomail.com; s=zohoarc; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::533; envelope-from=richard.henderson@linaro.org; helo=mail-ed1-x533.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1687349997552100001 Content-Type: text/plain; charset="utf-8" This creates a per-page method for checking of alignment. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- include/exec/cpu-all.h | 4 +++- accel/tcg/cputlb.c | 27 ++++++++++++++++++++++++++- 2 files changed, 29 insertions(+), 2 deletions(-) diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index 8018ce783e..e61100fc80 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -346,8 +346,10 @@ CPUArchState *cpu_copy(CPUArchState *env); #define TLB_BSWAP (1 << 0) /* Set if TLB entry contains a watchpoint. */ #define TLB_WATCHPOINT (1 << 1) +/* Set if TLB entry requires aligned accesses. */ +#define TLB_CHECK_ALIGNED (1 << 2) =20 -#define TLB_SLOW_FLAGS_MASK (TLB_BSWAP | TLB_WATCHPOINT) +#define TLB_SLOW_FLAGS_MASK (TLB_BSWAP | TLB_WATCHPOINT | TLB_CHECK_ALIGN= ED) =20 /* The two sets of flags must not overlap. */ QEMU_BUILD_BUG_ON(TLB_FLAGS_MASK & TLB_SLOW_FLAGS_MASK); diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 61f4d94a4d..cb7b4b01e9 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -1553,7 +1553,7 @@ static int probe_access_internal(CPUArchState *env, t= arget_ulong addr, flags |=3D full->slow_flags[access_type]; =20 /* Fold all "mmio-like" bits into TLB_MMIO. This is not RAM. */ - if (unlikely(flags & ~(TLB_WATCHPOINT | TLB_NOTDIRTY))) { + if (flags & ~(TLB_WATCHPOINT | TLB_NOTDIRTY | TLB_CHECK_ALIGNED)) { *phost =3D NULL; return TLB_MMIO; } @@ -1909,6 +1909,31 @@ static bool mmu_lookup(CPUArchState *env, target_ulo= ng addr, MemOpIdx oi, tcg_debug_assert((flags & TLB_BSWAP) =3D=3D 0); } =20 + /* + * This alignment check differs from the one above, in that this is + * based on the atomicity of the operation. The intended use case is + * the ARM memory type field of each PTE, where access to pages with + * Device memory type require alignment. + */ + if (unlikely(flags & TLB_CHECK_ALIGNED)) { + MemOp size =3D l->memop & MO_SIZE; + + switch (l->memop & MO_ATOM_MASK) { + case MO_ATOM_NONE: + size =3D MO_8; + break; + case MO_ATOM_IFALIGN_PAIR: + case MO_ATOM_WITHIN16_PAIR: + size =3D size ? size - 1 : 0; + break; + default: + break; + } + if (addr & ((1 << size) - 1)) { + cpu_unaligned_access(env_cpu(env), addr, type, l->mmu_idx, ra); + } + } + return crosspage; } =20 --=20 2.34.1 From nobody Tue May 14 17:54:18 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1687350185; cv=none; d=zohomail.com; s=zohoarc; b=W1Ty8HF82eRdAMNCY13liSJTpiPuki3mukOsr/wxZTTHQdM55lGMDzAkFgFQo9oipwMwECaPSMqzTNS+z0qvH5ysghowzF2vkA5pLIExhTWVLWKWqxaLO2yDzdx8sHtm19KeKlWPJOxU66I5hACBZVmIElkjN7579K36EYwaTVg= ARC-Message-Signature: i=1; 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Wed, 21 Jun 2023 05:19:12 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Idan Horowitz Subject: [PATCH v2 8/9] target/arm: Do memory type alignment check when translation disabled Date: Wed, 21 Jun 2023 14:19:01 +0200 Message-Id: <20230621121902.1392277-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230621121902.1392277-1-richard.henderson@linaro.org> References: <20230621121902.1392277-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::533; envelope-from=richard.henderson@linaro.org; helo=mail-ed1-x533.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1687350185882100003 If translation is disabled, the default memory type is Device, which requires alignment checking. This is more optimally done early via the MemOp given to the TCG memory operation. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reported-by: Idan Horowitz Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1204 Signed-off-by: Richard Henderson --- target/arm/tcg/hflags.c | 34 ++++++++++++++++++++++++++++++++-- 1 file changed, 32 insertions(+), 2 deletions(-) diff --git a/target/arm/tcg/hflags.c b/target/arm/tcg/hflags.c index 616c5fa723..56d7db150a 100644 --- a/target/arm/tcg/hflags.c +++ b/target/arm/tcg/hflags.c @@ -25,6 +25,35 @@ static inline bool fgt_svc(CPUARMState *env, int el) FIELD_EX64(env->cp15.fgt_exec[FGTREG_HFGITR], HFGITR_EL2, SVC_EL1); } =20 +/* Return true if memory alignment should be enforced. */ +static bool aprofile_require_alignment(CPUARMState *env, int el, uint64_t = sctlr) +{ +#ifdef CONFIG_USER_ONLY + return false; +#else + /* Check the alignment enable bit. */ + if (sctlr & SCTLR_A) { + return true; + } + + /* + * If translation is disabled, then the default memory type is + * Device(-nGnRnE) instead of Normal, which requires that alignment + * be enforced. Since this affects all ram, it is most efficient + * to handle this during translation. + */ + if (sctlr & SCTLR_M) { + /* Translation enabled: memory type in PTE via MAIR_ELx. */ + return false; + } + if (el < 2 && (arm_hcr_el2_eff(env) & (HCR_DC | HCR_VM))) { + /* Stage 2 translation enabled: memory type in PTE. */ + return false; + } + return true; +#endif +} + static CPUARMTBFlags rebuild_hflags_common(CPUARMState *env, int fp_el, ARMMMUIdx mmu_idx, CPUARMTBFlags flags) @@ -120,8 +149,9 @@ static CPUARMTBFlags rebuild_hflags_a32(CPUARMState *en= v, int fp_el, { CPUARMTBFlags flags =3D {}; int el =3D arm_current_el(env); + uint64_t sctlr =3D arm_sctlr(env, el); =20 - if (arm_sctlr(env, el) & SCTLR_A) { + if (aprofile_require_alignment(env, el, sctlr)) { DP_TBFLAG_ANY(flags, ALIGN_MEM, 1); } =20 @@ -221,7 +251,7 @@ static CPUARMTBFlags rebuild_hflags_a64(CPUARMState *en= v, int el, int fp_el, =20 sctlr =3D regime_sctlr(env, stage1); =20 - if (sctlr & SCTLR_A) { + if (aprofile_require_alignment(env, el, sctlr)) { DP_TBFLAG_ANY(flags, ALIGN_MEM, 1); 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Wed, 21 Jun 2023 05:19:13 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v2 9/9] target/arm: Do memory type alignment check when translation enabled Date: Wed, 21 Jun 2023 14:19:02 +0200 Message-Id: <20230621121902.1392277-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230621121902.1392277-1-richard.henderson@linaro.org> References: <20230621121902.1392277-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::52f; envelope-from=richard.henderson@linaro.org; helo=mail-ed1-x52f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1687350037586100001 Content-Type: text/plain; charset="utf-8" If translation is enabled, and the PTE memory type is Device, enable checking alignment via TLB_CHECK_ALIGNMENT. While the check is done later than it should be per the ARM, it's better than not performing the check at all. Signed-off-by: Richard Henderson --- target/arm/ptw.c | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 37bcb17a9e..8dcd5d80ce 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -227,6 +227,16 @@ static bool regime_translation_disabled(CPUARMState *e= nv, ARMMMUIdx mmu_idx, return (regime_sctlr(env, mmu_idx) & SCTLR_M) =3D=3D 0; } =20 +static bool S1_attrs_are_device(uint8_t attrs) +{ + /* + * This slightly under-decodes the MAIR_ELx field: + * 0b0000dd01 is Device with FEAT_XS, otherwise UNPREDICTABLE; + * 0b0000dd1x is UNPREDICTABLE. + */ + return (attrs & 0xf0) =3D=3D 0; +} + static bool S2_attrs_are_device(uint64_t hcr, uint8_t attrs) { /* @@ -1274,6 +1284,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Tr= anslate *ptw, bool aarch64 =3D arm_el_is_aa64(env, el); uint64_t descriptor, new_descriptor; bool nstable; + bool device; =20 /* TODO: This code does not support shareability levels. */ if (aarch64) { @@ -1623,6 +1634,8 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Tr= anslate *ptw, if (regime_is_stage2(mmu_idx)) { result->cacheattrs.is_s2_format =3D true; result->cacheattrs.attrs =3D extract32(attrs, 2, 4); + device =3D S2_attrs_are_device(arm_hcr_el2_eff_secstate(env, is_se= cure), + result->cacheattrs.attrs); } else { /* Index into MAIR registers for cache attributes */ uint8_t attrindx =3D extract32(attrs, 2, 3); @@ -1635,6 +1648,21 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1T= ranslate *ptw, if (aarch64 && cpu_isar_feature(aa64_bti, cpu)) { result->f.guarded =3D extract64(attrs, 50, 1); /* GP */ } + device =3D S1_attrs_are_device(result->cacheattrs.attrs); + } + + /* + * Enable alignment checks on Device memory. + * + * Per R_XCHFJ, this check is mis-ordered, in that this alignment check + * should have priority 30, while the permission check should be next = at + * priority 31 and stage2 translation faults come after that. + * Due to the way the TCG softmmu TLB operates, we will have implicitly + * done the permission check and the stage2 lookup in finding the TLB + * entry, so the alignment check cannot be done sooner. + */ + if (device) { + result->f.tlb_fill_flags |=3D TLB_CHECK_ALIGNED; } =20 /* --=20 2.34.1