target/riscv/cpu.c | 9 +++++---- target/riscv/cpu_cfg.h | 2 +- target/riscv/csr.c | 6 +++--- target/riscv/pmp.c | 12 ++++++------ 4 files changed, 15 insertions(+), 14 deletions(-)
Smepmp is a ratified extension which qemu refers to as epmp.
Rename epmp to smepmp and add it to extension list so that
it is added to the isa string.
Signed-off-by: Himanshu Chauhan <hchauhan@ventanamicro.com>
---
target/riscv/cpu.c | 9 +++++----
target/riscv/cpu_cfg.h | 2 +-
target/riscv/csr.c | 6 +++---
target/riscv/pmp.c | 12 ++++++------
4 files changed, 15 insertions(+), 14 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 881bddf393..cf3d1c3207 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -127,6 +127,7 @@ static const struct isa_ext_data isa_edata_arr[] = {
ISA_EXT_DATA_ENTRY(svinval, PRIV_VERSION_1_12_0, ext_svinval),
ISA_EXT_DATA_ENTRY(svnapot, PRIV_VERSION_1_12_0, ext_svnapot),
ISA_EXT_DATA_ENTRY(svpbmt, PRIV_VERSION_1_12_0, ext_svpbmt),
+ ISA_EXT_DATA_ENTRY(smepmp, PRIV_VERSION_1_12_0, ext_smepmp),
ISA_EXT_DATA_ENTRY(xtheadba, PRIV_VERSION_1_11_0, ext_xtheadba),
ISA_EXT_DATA_ENTRY(xtheadbb, PRIV_VERSION_1_11_0, ext_xtheadbb),
ISA_EXT_DATA_ENTRY(xtheadbs, PRIV_VERSION_1_11_0, ext_xtheadbs),
@@ -547,7 +548,7 @@ static void rv32_ibex_cpu_init(Object *obj)
#ifndef CONFIG_USER_ONLY
set_satp_mode_max_supported(cpu, VM_1_10_MBARE);
#endif
- cpu->cfg.epmp = true;
+ cpu->cfg.ext_smepmp = true;
/* inherited from parent obj via riscv_cpu_init() */
cpu->cfg.ext_ifencei = true;
@@ -1336,12 +1337,12 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
return;
}
- if (cpu->cfg.epmp && !cpu->cfg.pmp) {
+ if (cpu->cfg.ext_smepmp && !cpu->cfg.pmp) {
/*
* Enhanced PMP should only be available
* on harts with PMP support
*/
- error_setg(errp, "Invalid configuration: EPMP requires PMP support");
+ error_setg(errp, "Invalid configuration: SMEPMP requires PMP support");
return;
}
@@ -1676,7 +1677,7 @@ static Property riscv_cpu_extensions[] = {
DEFINE_PROP_BOOL("x-zicond", RISCVCPU, cfg.ext_zicond, false),
/* ePMP 0.9.3 */
- DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false),
+ DEFINE_PROP_BOOL("smepmp", RISCVCPU, cfg.ext_smepmp, false),
DEFINE_PROP_BOOL("x-smaia", RISCVCPU, cfg.ext_smaia, false),
DEFINE_PROP_BOOL("x-ssaia", RISCVCPU, cfg.ext_ssaia, false),
diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
index c4a627d335..d79b022e35 100644
--- a/target/riscv/cpu_cfg.h
+++ b/target/riscv/cpu_cfg.h
@@ -87,6 +87,7 @@ struct RISCVCPUConfig {
bool ext_zvfh;
bool ext_zvfhmin;
bool ext_smaia;
+ bool ext_smepmp;
bool ext_ssaia;
bool ext_sscofpmf;
bool rvv_ta_all_1s;
@@ -121,7 +122,6 @@ struct RISCVCPUConfig {
uint16_t cboz_blocksize;
bool mmu;
bool pmp;
- bool epmp;
bool debug;
bool misa_w;
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 58499b5afc..d9bc591348 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -523,9 +523,9 @@ static RISCVException pmp(CPURISCVState *env, int csrno)
return RISCV_EXCP_ILLEGAL_INST;
}
-static RISCVException epmp(CPURISCVState *env, int csrno)
+static RISCVException smepmp(CPURISCVState *env, int csrno)
{
- if (riscv_cpu_cfg(env)->epmp) {
+ if (riscv_cpu_cfg(env)->ext_smepmp) {
return RISCV_EXCP_NONE;
}
@@ -4356,7 +4356,7 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
[CSR_VSIPH] = { "vsiph", aia_hmode32, NULL, NULL, rmw_vsiph },
/* Physical Memory Protection */
- [CSR_MSECCFG] = { "mseccfg", epmp, read_mseccfg, write_mseccfg,
+ [CSR_MSECCFG] = { "mseccfg", smepmp, read_mseccfg, write_mseccfg,
.min_priv_ver = PRIV_VERSION_1_11_0 },
[CSR_PMPCFG0] = { "pmpcfg0", pmp, read_pmpcfg, write_pmpcfg },
[CSR_PMPCFG1] = { "pmpcfg1", pmp, read_pmpcfg, write_pmpcfg },
diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index 418738afd8..18246e1737 100644
--- a/target/riscv/pmp.c
+++ b/target/riscv/pmp.c
@@ -87,7 +87,7 @@ static bool pmp_write_cfg(CPURISCVState *env, uint32_t pmp_index, uint8_t val)
if (pmp_index < MAX_RISCV_PMPS) {
bool locked = true;
- if (riscv_cpu_cfg(env)->epmp) {
+ if (riscv_cpu_cfg(env)->ext_smepmp) {
/* mseccfg.RLB is set */
if (MSECCFG_RLB_ISSET(env)) {
locked = false;
@@ -337,9 +337,9 @@ bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
/*
* Convert the PMP permissions to match the truth table in the
- * ePMP spec.
+ * SMEPMP spec.
*/
- const uint8_t epmp_operation =
+ const uint8_t smepmp_operation =
((env->pmp_state.pmp[i].cfg_reg & PMP_LOCK) >> 4) |
((env->pmp_state.pmp[i].cfg_reg & PMP_READ) << 2) |
(env->pmp_state.pmp[i].cfg_reg & PMP_WRITE) |
@@ -364,7 +364,7 @@ bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
* If mseccfg.MML Bit set, do the enhanced pmp priv check
*/
if (mode == PRV_M) {
- switch (epmp_operation) {
+ switch (smepmp_operation) {
case 0:
case 1:
case 4:
@@ -395,7 +395,7 @@ bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
g_assert_not_reached();
}
} else {
- switch (epmp_operation) {
+ switch (smepmp_operation) {
case 0:
case 8:
case 9:
@@ -576,7 +576,7 @@ void mseccfg_csr_write(CPURISCVState *env, target_ulong val)
}
}
- if (riscv_cpu_cfg(env)->epmp) {
+ if (riscv_cpu_cfg(env)->ext_smepmp) {
/* Sticky bits */
val |= (env->mseccfg & (MSECCFG_MMWP | MSECCFG_MML));
if ((val ^ env->mseccfg) & (MSECCFG_MMWP | MSECCFG_MML)) {
--
2.34.1On Tue, Jun 6, 2023 at 1:39 PM Himanshu Chauhan
<hchauhan@ventanamicro.com> wrote:
>
> Smepmp is a ratified extension which qemu refers to as epmp.
> Rename epmp to smepmp and add it to extension list so that
> it is added to the isa string.
>
> Signed-off-by: Himanshu Chauhan <hchauhan@ventanamicro.com>
> ---
> target/riscv/cpu.c | 9 +++++----
> target/riscv/cpu_cfg.h | 2 +-
> target/riscv/csr.c | 6 +++---
> target/riscv/pmp.c | 12 ++++++------
> 4 files changed, 15 insertions(+), 14 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 881bddf393..cf3d1c3207 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -127,6 +127,7 @@ static const struct isa_ext_data isa_edata_arr[] = {
> ISA_EXT_DATA_ENTRY(svinval, PRIV_VERSION_1_12_0, ext_svinval),
> ISA_EXT_DATA_ENTRY(svnapot, PRIV_VERSION_1_12_0, ext_svnapot),
> ISA_EXT_DATA_ENTRY(svpbmt, PRIV_VERSION_1_12_0, ext_svpbmt),
> + ISA_EXT_DATA_ENTRY(smepmp, PRIV_VERSION_1_12_0, ext_smepmp),
> ISA_EXT_DATA_ENTRY(xtheadba, PRIV_VERSION_1_11_0, ext_xtheadba),
> ISA_EXT_DATA_ENTRY(xtheadbb, PRIV_VERSION_1_11_0, ext_xtheadbb),
> ISA_EXT_DATA_ENTRY(xtheadbs, PRIV_VERSION_1_11_0, ext_xtheadbs),
> @@ -547,7 +548,7 @@ static void rv32_ibex_cpu_init(Object *obj)
> #ifndef CONFIG_USER_ONLY
> set_satp_mode_max_supported(cpu, VM_1_10_MBARE);
> #endif
> - cpu->cfg.epmp = true;
> + cpu->cfg.ext_smepmp = true;
>
Should also update Ibex CPU to priv level 1.12 otherwise Smepmp will
be disabled since it is now declared PRIV_VERSION_1_12_0 in
isa_edata_arr.
> /* inherited from parent obj via riscv_cpu_init() */
> cpu->cfg.ext_ifencei = true;
> @@ -1336,12 +1337,12 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
> return;
> }
>
> - if (cpu->cfg.epmp && !cpu->cfg.pmp) {
> + if (cpu->cfg.ext_smepmp && !cpu->cfg.pmp) {
> /*
> * Enhanced PMP should only be available
> * on harts with PMP support
> */
> - error_setg(errp, "Invalid configuration: EPMP requires PMP support");
> + error_setg(errp, "Invalid configuration: SMEPMP requires PMP support");
> return;
> }
Nitpick: the spec uses "Smepmp", not "SMEPMP".
>
> @@ -1676,7 +1677,7 @@ static Property riscv_cpu_extensions[] = {
> DEFINE_PROP_BOOL("x-zicond", RISCVCPU, cfg.ext_zicond, false),
>
> /* ePMP 0.9.3 */
> - DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false),
> + DEFINE_PROP_BOOL("smepmp", RISCVCPU, cfg.ext_smepmp, false),
> DEFINE_PROP_BOOL("x-smaia", RISCVCPU, cfg.ext_smaia, false),
> DEFINE_PROP_BOOL("x-ssaia", RISCVCPU, cfg.ext_ssaia, false),
>
You missed the comment update but maybe just move the definition next
to pmp and drop the comment since it's now ratified?
> diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
> index c4a627d335..d79b022e35 100644
> --- a/target/riscv/cpu_cfg.h
> +++ b/target/riscv/cpu_cfg.h
> @@ -87,6 +87,7 @@ struct RISCVCPUConfig {
> bool ext_zvfh;
> bool ext_zvfhmin;
> bool ext_smaia;
> + bool ext_smepmp;
> bool ext_ssaia;
> bool ext_sscofpmf;
> bool rvv_ta_all_1s;
> @@ -121,7 +122,6 @@ struct RISCVCPUConfig {
> uint16_t cboz_blocksize;
> bool mmu;
> bool pmp;
> - bool epmp;
> bool debug;
> bool misa_w;
>
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index 58499b5afc..d9bc591348 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -523,9 +523,9 @@ static RISCVException pmp(CPURISCVState *env, int csrno)
> return RISCV_EXCP_ILLEGAL_INST;
> }
>
> -static RISCVException epmp(CPURISCVState *env, int csrno)
> +static RISCVException smepmp(CPURISCVState *env, int csrno)
> {
> - if (riscv_cpu_cfg(env)->epmp) {
> + if (riscv_cpu_cfg(env)->ext_smepmp) {
> return RISCV_EXCP_NONE;
> }
>
> @@ -4356,7 +4356,7 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
> [CSR_VSIPH] = { "vsiph", aia_hmode32, NULL, NULL, rmw_vsiph },
>
> /* Physical Memory Protection */
> - [CSR_MSECCFG] = { "mseccfg", epmp, read_mseccfg, write_mseccfg,
> + [CSR_MSECCFG] = { "mseccfg", smepmp, read_mseccfg, write_mseccfg,
> .min_priv_ver = PRIV_VERSION_1_11_0 },
> [CSR_PMPCFG0] = { "pmpcfg0", pmp, read_pmpcfg, write_pmpcfg },
> [CSR_PMPCFG1] = { "pmpcfg1", pmp, read_pmpcfg, write_pmpcfg },
> diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
> index 418738afd8..18246e1737 100644
> --- a/target/riscv/pmp.c
> +++ b/target/riscv/pmp.c
> @@ -87,7 +87,7 @@ static bool pmp_write_cfg(CPURISCVState *env, uint32_t pmp_index, uint8_t val)
> if (pmp_index < MAX_RISCV_PMPS) {
> bool locked = true;
>
> - if (riscv_cpu_cfg(env)->epmp) {
> + if (riscv_cpu_cfg(env)->ext_smepmp) {
> /* mseccfg.RLB is set */
> if (MSECCFG_RLB_ISSET(env)) {
> locked = false;
> @@ -337,9 +337,9 @@ bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
>
> /*
> * Convert the PMP permissions to match the truth table in the
> - * ePMP spec.
> + * SMEPMP spec.
> */
Smepmp
> - const uint8_t epmp_operation =
> + const uint8_t smepmp_operation =
> ((env->pmp_state.pmp[i].cfg_reg & PMP_LOCK) >> 4) |
> ((env->pmp_state.pmp[i].cfg_reg & PMP_READ) << 2) |
> (env->pmp_state.pmp[i].cfg_reg & PMP_WRITE) |
> @@ -364,7 +364,7 @@ bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
> * If mseccfg.MML Bit set, do the enhanced pmp priv check
> */
> if (mode == PRV_M) {
> - switch (epmp_operation) {
> + switch (smepmp_operation) {
> case 0:
> case 1:
> case 4:
> @@ -395,7 +395,7 @@ bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
> g_assert_not_reached();
> }
> } else {
> - switch (epmp_operation) {
> + switch (smepmp_operation) {
> case 0:
> case 8:
> case 9:
> @@ -576,7 +576,7 @@ void mseccfg_csr_write(CPURISCVState *env, target_ulong val)
> }
> }
>
> - if (riscv_cpu_cfg(env)->epmp) {
> + if (riscv_cpu_cfg(env)->ext_smepmp) {
> /* Sticky bits */
> val |= (env->mseccfg & (MSECCFG_MMWP | MSECCFG_MML));
> if ((val ^ env->mseccfg) & (MSECCFG_MMWP | MSECCFG_MML)) {
> --
> 2.34.1
>
>
On 6/6/23 16:46, Loïc Lefort wrote:
> On Tue, Jun 6, 2023 at 1:39 PM Himanshu Chauhan
> <hchauhan@ventanamicro.com> wrote:
>>
>> Smepmp is a ratified extension which qemu refers to as epmp.
>> Rename epmp to smepmp and add it to extension list so that
>> it is added to the isa string.
>>
>> Signed-off-by: Himanshu Chauhan <hchauhan@ventanamicro.com>
>> ---
>> target/riscv/cpu.c | 9 +++++----
>> target/riscv/cpu_cfg.h | 2 +-
>> target/riscv/csr.c | 6 +++---
>> target/riscv/pmp.c | 12 ++++++------
>> 4 files changed, 15 insertions(+), 14 deletions(-)
>>
>> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
>> index 881bddf393..cf3d1c3207 100644
>> --- a/target/riscv/cpu.c
>> +++ b/target/riscv/cpu.c
>> @@ -127,6 +127,7 @@ static const struct isa_ext_data isa_edata_arr[] = {
>> ISA_EXT_DATA_ENTRY(svinval, PRIV_VERSION_1_12_0, ext_svinval),
>> ISA_EXT_DATA_ENTRY(svnapot, PRIV_VERSION_1_12_0, ext_svnapot),
>> ISA_EXT_DATA_ENTRY(svpbmt, PRIV_VERSION_1_12_0, ext_svpbmt),
>> + ISA_EXT_DATA_ENTRY(smepmp, PRIV_VERSION_1_12_0, ext_smepmp),
>> ISA_EXT_DATA_ENTRY(xtheadba, PRIV_VERSION_1_11_0, ext_xtheadba),
>> ISA_EXT_DATA_ENTRY(xtheadbb, PRIV_VERSION_1_11_0, ext_xtheadbb),
>> ISA_EXT_DATA_ENTRY(xtheadbs, PRIV_VERSION_1_11_0, ext_xtheadbs),
>> @@ -547,7 +548,7 @@ static void rv32_ibex_cpu_init(Object *obj)
>> #ifndef CONFIG_USER_ONLY
>> set_satp_mode_max_supported(cpu, VM_1_10_MBARE);
>> #endif
>> - cpu->cfg.epmp = true;
>> + cpu->cfg.ext_smepmp = true;
>>
> Should also update Ibex CPU to priv level 1.12 otherwise Smepmp will
> be disabled since it is now declared PRIV_VERSION_1_12_0 in
> isa_edata_arr.
(--- added Alistair in CC since he added the Ibex CPU back in 2020 ---)
Good point. Commit ed6eebaaafd states that the Ibex CPU has ePMP support
and this patch would break it.
I suggest changing the priv_version in a separated patch to facilitate future
rebases/bisects.
Thanks,
Daniel
>
>> /* inherited from parent obj via riscv_cpu_init() */
>> cpu->cfg.ext_ifencei = true;
>> @@ -1336,12 +1337,12 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
>> return;
>> }
>>
>> - if (cpu->cfg.epmp && !cpu->cfg.pmp) {
>> + if (cpu->cfg.ext_smepmp && !cpu->cfg.pmp) {
>> /*
>> * Enhanced PMP should only be available
>> * on harts with PMP support
>> */
>> - error_setg(errp, "Invalid configuration: EPMP requires PMP support");
>> + error_setg(errp, "Invalid configuration: SMEPMP requires PMP support");
>> return;
>> }
> Nitpick: the spec uses "Smepmp", not "SMEPMP".
>
>>
>> @@ -1676,7 +1677,7 @@ static Property riscv_cpu_extensions[] = {
>> DEFINE_PROP_BOOL("x-zicond", RISCVCPU, cfg.ext_zicond, false),
>>
>> /* ePMP 0.9.3 */
>> - DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false),
>> + DEFINE_PROP_BOOL("smepmp", RISCVCPU, cfg.ext_smepmp, false),
>> DEFINE_PROP_BOOL("x-smaia", RISCVCPU, cfg.ext_smaia, false),
>> DEFINE_PROP_BOOL("x-ssaia", RISCVCPU, cfg.ext_ssaia, false),
>>
> You missed the comment update but maybe just move the definition next
> to pmp and drop the comment since it's now ratified?
>
>> diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
>> index c4a627d335..d79b022e35 100644
>> --- a/target/riscv/cpu_cfg.h
>> +++ b/target/riscv/cpu_cfg.h
>> @@ -87,6 +87,7 @@ struct RISCVCPUConfig {
>> bool ext_zvfh;
>> bool ext_zvfhmin;
>> bool ext_smaia;
>> + bool ext_smepmp;
>> bool ext_ssaia;
>> bool ext_sscofpmf;
>> bool rvv_ta_all_1s;
>> @@ -121,7 +122,6 @@ struct RISCVCPUConfig {
>> uint16_t cboz_blocksize;
>> bool mmu;
>> bool pmp;
>> - bool epmp;
>> bool debug;
>> bool misa_w;
>>
>> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
>> index 58499b5afc..d9bc591348 100644
>> --- a/target/riscv/csr.c
>> +++ b/target/riscv/csr.c
>> @@ -523,9 +523,9 @@ static RISCVException pmp(CPURISCVState *env, int csrno)
>> return RISCV_EXCP_ILLEGAL_INST;
>> }
>>
>> -static RISCVException epmp(CPURISCVState *env, int csrno)
>> +static RISCVException smepmp(CPURISCVState *env, int csrno)
>> {
>> - if (riscv_cpu_cfg(env)->epmp) {
>> + if (riscv_cpu_cfg(env)->ext_smepmp) {
>> return RISCV_EXCP_NONE;
>> }
>>
>> @@ -4356,7 +4356,7 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
>> [CSR_VSIPH] = { "vsiph", aia_hmode32, NULL, NULL, rmw_vsiph },
>>
>> /* Physical Memory Protection */
>> - [CSR_MSECCFG] = { "mseccfg", epmp, read_mseccfg, write_mseccfg,
>> + [CSR_MSECCFG] = { "mseccfg", smepmp, read_mseccfg, write_mseccfg,
>> .min_priv_ver = PRIV_VERSION_1_11_0 },
>> [CSR_PMPCFG0] = { "pmpcfg0", pmp, read_pmpcfg, write_pmpcfg },
>> [CSR_PMPCFG1] = { "pmpcfg1", pmp, read_pmpcfg, write_pmpcfg },
>> diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
>> index 418738afd8..18246e1737 100644
>> --- a/target/riscv/pmp.c
>> +++ b/target/riscv/pmp.c
>> @@ -87,7 +87,7 @@ static bool pmp_write_cfg(CPURISCVState *env, uint32_t pmp_index, uint8_t val)
>> if (pmp_index < MAX_RISCV_PMPS) {
>> bool locked = true;
>>
>> - if (riscv_cpu_cfg(env)->epmp) {
>> + if (riscv_cpu_cfg(env)->ext_smepmp) {
>> /* mseccfg.RLB is set */
>> if (MSECCFG_RLB_ISSET(env)) {
>> locked = false;
>> @@ -337,9 +337,9 @@ bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
>>
>> /*
>> * Convert the PMP permissions to match the truth table in the
>> - * ePMP spec.
>> + * SMEPMP spec.
>> */
> Smepmp
>
>> - const uint8_t epmp_operation =
>> + const uint8_t smepmp_operation =
>> ((env->pmp_state.pmp[i].cfg_reg & PMP_LOCK) >> 4) |
>> ((env->pmp_state.pmp[i].cfg_reg & PMP_READ) << 2) |
>> (env->pmp_state.pmp[i].cfg_reg & PMP_WRITE) |
>> @@ -364,7 +364,7 @@ bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
>> * If mseccfg.MML Bit set, do the enhanced pmp priv check
>> */
>> if (mode == PRV_M) {
>> - switch (epmp_operation) {
>> + switch (smepmp_operation) {
>> case 0:
>> case 1:
>> case 4:
>> @@ -395,7 +395,7 @@ bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
>> g_assert_not_reached();
>> }
>> } else {
>> - switch (epmp_operation) {
>> + switch (smepmp_operation) {
>> case 0:
>> case 8:
>> case 9:
>> @@ -576,7 +576,7 @@ void mseccfg_csr_write(CPURISCVState *env, target_ulong val)
>> }
>> }
>>
>> - if (riscv_cpu_cfg(env)->epmp) {
>> + if (riscv_cpu_cfg(env)->ext_smepmp) {
>> /* Sticky bits */
>> val |= (env->mseccfg & (MSECCFG_MMWP | MSECCFG_MML));
>> if ((val ^ env->mseccfg) & (MSECCFG_MMWP | MSECCFG_MML)) {
>> --
>> 2.34.1
>>
>>
>
On Wed, Jun 7, 2023 at 6:56 AM Daniel Henrique Barboza
<dbarboza@ventanamicro.com> wrote:
>
>
>
> On 6/6/23 16:46, Loïc Lefort wrote:
> > On Tue, Jun 6, 2023 at 1:39 PM Himanshu Chauhan
> > <hchauhan@ventanamicro.com> wrote:
> >>
> >> Smepmp is a ratified extension which qemu refers to as epmp.
> >> Rename epmp to smepmp and add it to extension list so that
> >> it is added to the isa string.
> >>
> >> Signed-off-by: Himanshu Chauhan <hchauhan@ventanamicro.com>
> >> ---
> >> target/riscv/cpu.c | 9 +++++----
> >> target/riscv/cpu_cfg.h | 2 +-
> >> target/riscv/csr.c | 6 +++---
> >> target/riscv/pmp.c | 12 ++++++------
> >> 4 files changed, 15 insertions(+), 14 deletions(-)
> >>
> >> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> >> index 881bddf393..cf3d1c3207 100644
> >> --- a/target/riscv/cpu.c
> >> +++ b/target/riscv/cpu.c
> >> @@ -127,6 +127,7 @@ static const struct isa_ext_data isa_edata_arr[] = {
> >> ISA_EXT_DATA_ENTRY(svinval, PRIV_VERSION_1_12_0, ext_svinval),
> >> ISA_EXT_DATA_ENTRY(svnapot, PRIV_VERSION_1_12_0, ext_svnapot),
> >> ISA_EXT_DATA_ENTRY(svpbmt, PRIV_VERSION_1_12_0, ext_svpbmt),
> >> + ISA_EXT_DATA_ENTRY(smepmp, PRIV_VERSION_1_12_0, ext_smepmp),
> >> ISA_EXT_DATA_ENTRY(xtheadba, PRIV_VERSION_1_11_0, ext_xtheadba),
> >> ISA_EXT_DATA_ENTRY(xtheadbb, PRIV_VERSION_1_11_0, ext_xtheadbb),
> >> ISA_EXT_DATA_ENTRY(xtheadbs, PRIV_VERSION_1_11_0, ext_xtheadbs),
> >> @@ -547,7 +548,7 @@ static void rv32_ibex_cpu_init(Object *obj)
> >> #ifndef CONFIG_USER_ONLY
> >> set_satp_mode_max_supported(cpu, VM_1_10_MBARE);
> >> #endif
> >> - cpu->cfg.epmp = true;
> >> + cpu->cfg.ext_smepmp = true;
> >>
> > Should also update Ibex CPU to priv level 1.12 otherwise Smepmp will
> > be disabled since it is now declared PRIV_VERSION_1_12_0 in
> > isa_edata_arr.
>
> (--- added Alistair in CC since he added the Ibex CPU back in 2020 ---)
>
> Good point. Commit ed6eebaaafd states that the Ibex CPU has ePMP support
> and this patch would break it.
>
> I suggest changing the priv_version in a separated patch to facilitate future
> rebases/bisects.
Agreed!
Thanks for the patch as well, I have been meaning to get around to fix this
Alistair
>
>
> Thanks,
>
>
> Daniel
>
>
> >
> >> /* inherited from parent obj via riscv_cpu_init() */
> >> cpu->cfg.ext_ifencei = true;
> >> @@ -1336,12 +1337,12 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
> >> return;
> >> }
> >>
> >> - if (cpu->cfg.epmp && !cpu->cfg.pmp) {
> >> + if (cpu->cfg.ext_smepmp && !cpu->cfg.pmp) {
> >> /*
> >> * Enhanced PMP should only be available
> >> * on harts with PMP support
> >> */
> >> - error_setg(errp, "Invalid configuration: EPMP requires PMP support");
> >> + error_setg(errp, "Invalid configuration: SMEPMP requires PMP support");
> >> return;
> >> }
> > Nitpick: the spec uses "Smepmp", not "SMEPMP".
> >
> >>
> >> @@ -1676,7 +1677,7 @@ static Property riscv_cpu_extensions[] = {
> >> DEFINE_PROP_BOOL("x-zicond", RISCVCPU, cfg.ext_zicond, false),
> >>
> >> /* ePMP 0.9.3 */
> >> - DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false),
> >> + DEFINE_PROP_BOOL("smepmp", RISCVCPU, cfg.ext_smepmp, false),
> >> DEFINE_PROP_BOOL("x-smaia", RISCVCPU, cfg.ext_smaia, false),
> >> DEFINE_PROP_BOOL("x-ssaia", RISCVCPU, cfg.ext_ssaia, false),
> >>
> > You missed the comment update but maybe just move the definition next
> > to pmp and drop the comment since it's now ratified?
> >
> >> diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
> >> index c4a627d335..d79b022e35 100644
> >> --- a/target/riscv/cpu_cfg.h
> >> +++ b/target/riscv/cpu_cfg.h
> >> @@ -87,6 +87,7 @@ struct RISCVCPUConfig {
> >> bool ext_zvfh;
> >> bool ext_zvfhmin;
> >> bool ext_smaia;
> >> + bool ext_smepmp;
> >> bool ext_ssaia;
> >> bool ext_sscofpmf;
> >> bool rvv_ta_all_1s;
> >> @@ -121,7 +122,6 @@ struct RISCVCPUConfig {
> >> uint16_t cboz_blocksize;
> >> bool mmu;
> >> bool pmp;
> >> - bool epmp;
> >> bool debug;
> >> bool misa_w;
> >>
> >> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> >> index 58499b5afc..d9bc591348 100644
> >> --- a/target/riscv/csr.c
> >> +++ b/target/riscv/csr.c
> >> @@ -523,9 +523,9 @@ static RISCVException pmp(CPURISCVState *env, int csrno)
> >> return RISCV_EXCP_ILLEGAL_INST;
> >> }
> >>
> >> -static RISCVException epmp(CPURISCVState *env, int csrno)
> >> +static RISCVException smepmp(CPURISCVState *env, int csrno)
> >> {
> >> - if (riscv_cpu_cfg(env)->epmp) {
> >> + if (riscv_cpu_cfg(env)->ext_smepmp) {
> >> return RISCV_EXCP_NONE;
> >> }
> >>
> >> @@ -4356,7 +4356,7 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
> >> [CSR_VSIPH] = { "vsiph", aia_hmode32, NULL, NULL, rmw_vsiph },
> >>
> >> /* Physical Memory Protection */
> >> - [CSR_MSECCFG] = { "mseccfg", epmp, read_mseccfg, write_mseccfg,
> >> + [CSR_MSECCFG] = { "mseccfg", smepmp, read_mseccfg, write_mseccfg,
> >> .min_priv_ver = PRIV_VERSION_1_11_0 },
> >> [CSR_PMPCFG0] = { "pmpcfg0", pmp, read_pmpcfg, write_pmpcfg },
> >> [CSR_PMPCFG1] = { "pmpcfg1", pmp, read_pmpcfg, write_pmpcfg },
> >> diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
> >> index 418738afd8..18246e1737 100644
> >> --- a/target/riscv/pmp.c
> >> +++ b/target/riscv/pmp.c
> >> @@ -87,7 +87,7 @@ static bool pmp_write_cfg(CPURISCVState *env, uint32_t pmp_index, uint8_t val)
> >> if (pmp_index < MAX_RISCV_PMPS) {
> >> bool locked = true;
> >>
> >> - if (riscv_cpu_cfg(env)->epmp) {
> >> + if (riscv_cpu_cfg(env)->ext_smepmp) {
> >> /* mseccfg.RLB is set */
> >> if (MSECCFG_RLB_ISSET(env)) {
> >> locked = false;
> >> @@ -337,9 +337,9 @@ bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
> >>
> >> /*
> >> * Convert the PMP permissions to match the truth table in the
> >> - * ePMP spec.
> >> + * SMEPMP spec.
> >> */
> > Smepmp
> >
> >> - const uint8_t epmp_operation =
> >> + const uint8_t smepmp_operation =
> >> ((env->pmp_state.pmp[i].cfg_reg & PMP_LOCK) >> 4) |
> >> ((env->pmp_state.pmp[i].cfg_reg & PMP_READ) << 2) |
> >> (env->pmp_state.pmp[i].cfg_reg & PMP_WRITE) |
> >> @@ -364,7 +364,7 @@ bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
> >> * If mseccfg.MML Bit set, do the enhanced pmp priv check
> >> */
> >> if (mode == PRV_M) {
> >> - switch (epmp_operation) {
> >> + switch (smepmp_operation) {
> >> case 0:
> >> case 1:
> >> case 4:
> >> @@ -395,7 +395,7 @@ bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
> >> g_assert_not_reached();
> >> }
> >> } else {
> >> - switch (epmp_operation) {
> >> + switch (smepmp_operation) {
> >> case 0:
> >> case 8:
> >> case 9:
> >> @@ -576,7 +576,7 @@ void mseccfg_csr_write(CPURISCVState *env, target_ulong val)
> >> }
> >> }
> >>
> >> - if (riscv_cpu_cfg(env)->epmp) {
> >> + if (riscv_cpu_cfg(env)->ext_smepmp) {
> >> /* Sticky bits */
> >> val |= (env->mseccfg & (MSECCFG_MMWP | MSECCFG_MML));
> >> if ((val ^ env->mseccfg) & (MSECCFG_MMWP | MSECCFG_MML)) {
> >> --
> >> 2.34.1
> >>
> >>
> >
>
On 6/6/23 08:38, Himanshu Chauhan wrote:
> Smepmp is a ratified extension which qemu refers to as epmp.
> Rename epmp to smepmp and add it to extension list so that
> it is added to the isa string.
>
> Signed-off-by: Himanshu Chauhan <hchauhan@ventanamicro.com>
> ---
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> target/riscv/cpu.c | 9 +++++----
> target/riscv/cpu_cfg.h | 2 +-
> target/riscv/csr.c | 6 +++---
> target/riscv/pmp.c | 12 ++++++------
> 4 files changed, 15 insertions(+), 14 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 881bddf393..cf3d1c3207 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -127,6 +127,7 @@ static const struct isa_ext_data isa_edata_arr[] = {
> ISA_EXT_DATA_ENTRY(svinval, PRIV_VERSION_1_12_0, ext_svinval),
> ISA_EXT_DATA_ENTRY(svnapot, PRIV_VERSION_1_12_0, ext_svnapot),
> ISA_EXT_DATA_ENTRY(svpbmt, PRIV_VERSION_1_12_0, ext_svpbmt),
> + ISA_EXT_DATA_ENTRY(smepmp, PRIV_VERSION_1_12_0, ext_smepmp),
> ISA_EXT_DATA_ENTRY(xtheadba, PRIV_VERSION_1_11_0, ext_xtheadba),
> ISA_EXT_DATA_ENTRY(xtheadbb, PRIV_VERSION_1_11_0, ext_xtheadbb),
> ISA_EXT_DATA_ENTRY(xtheadbs, PRIV_VERSION_1_11_0, ext_xtheadbs),
> @@ -547,7 +548,7 @@ static void rv32_ibex_cpu_init(Object *obj)
> #ifndef CONFIG_USER_ONLY
> set_satp_mode_max_supported(cpu, VM_1_10_MBARE);
> #endif
> - cpu->cfg.epmp = true;
> + cpu->cfg.ext_smepmp = true;
>
> /* inherited from parent obj via riscv_cpu_init() */
> cpu->cfg.ext_ifencei = true;
> @@ -1336,12 +1337,12 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
> return;
> }
>
> - if (cpu->cfg.epmp && !cpu->cfg.pmp) {
> + if (cpu->cfg.ext_smepmp && !cpu->cfg.pmp) {
> /*
> * Enhanced PMP should only be available
> * on harts with PMP support
> */
> - error_setg(errp, "Invalid configuration: EPMP requires PMP support");
> + error_setg(errp, "Invalid configuration: SMEPMP requires PMP support");
> return;
> }
>
> @@ -1676,7 +1677,7 @@ static Property riscv_cpu_extensions[] = {
> DEFINE_PROP_BOOL("x-zicond", RISCVCPU, cfg.ext_zicond, false),
>
> /* ePMP 0.9.3 */
> - DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false),
> + DEFINE_PROP_BOOL("smepmp", RISCVCPU, cfg.ext_smepmp, false),
> DEFINE_PROP_BOOL("x-smaia", RISCVCPU, cfg.ext_smaia, false),
> DEFINE_PROP_BOOL("x-ssaia", RISCVCPU, cfg.ext_ssaia, false),
>
> diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
> index c4a627d335..d79b022e35 100644
> --- a/target/riscv/cpu_cfg.h
> +++ b/target/riscv/cpu_cfg.h
> @@ -87,6 +87,7 @@ struct RISCVCPUConfig {
> bool ext_zvfh;
> bool ext_zvfhmin;
> bool ext_smaia;
> + bool ext_smepmp;
> bool ext_ssaia;
> bool ext_sscofpmf;
> bool rvv_ta_all_1s;
> @@ -121,7 +122,6 @@ struct RISCVCPUConfig {
> uint16_t cboz_blocksize;
> bool mmu;
> bool pmp;
> - bool epmp;
> bool debug;
> bool misa_w;
>
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index 58499b5afc..d9bc591348 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -523,9 +523,9 @@ static RISCVException pmp(CPURISCVState *env, int csrno)
> return RISCV_EXCP_ILLEGAL_INST;
> }
>
> -static RISCVException epmp(CPURISCVState *env, int csrno)
> +static RISCVException smepmp(CPURISCVState *env, int csrno)
> {
> - if (riscv_cpu_cfg(env)->epmp) {
> + if (riscv_cpu_cfg(env)->ext_smepmp) {
> return RISCV_EXCP_NONE;
> }
>
> @@ -4356,7 +4356,7 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
> [CSR_VSIPH] = { "vsiph", aia_hmode32, NULL, NULL, rmw_vsiph },
>
> /* Physical Memory Protection */
> - [CSR_MSECCFG] = { "mseccfg", epmp, read_mseccfg, write_mseccfg,
> + [CSR_MSECCFG] = { "mseccfg", smepmp, read_mseccfg, write_mseccfg,
> .min_priv_ver = PRIV_VERSION_1_11_0 },
> [CSR_PMPCFG0] = { "pmpcfg0", pmp, read_pmpcfg, write_pmpcfg },
> [CSR_PMPCFG1] = { "pmpcfg1", pmp, read_pmpcfg, write_pmpcfg },
> diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
> index 418738afd8..18246e1737 100644
> --- a/target/riscv/pmp.c
> +++ b/target/riscv/pmp.c
> @@ -87,7 +87,7 @@ static bool pmp_write_cfg(CPURISCVState *env, uint32_t pmp_index, uint8_t val)
> if (pmp_index < MAX_RISCV_PMPS) {
> bool locked = true;
>
> - if (riscv_cpu_cfg(env)->epmp) {
> + if (riscv_cpu_cfg(env)->ext_smepmp) {
> /* mseccfg.RLB is set */
> if (MSECCFG_RLB_ISSET(env)) {
> locked = false;
> @@ -337,9 +337,9 @@ bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
>
> /*
> * Convert the PMP permissions to match the truth table in the
> - * ePMP spec.
> + * SMEPMP spec.
> */
> - const uint8_t epmp_operation =
> + const uint8_t smepmp_operation =
> ((env->pmp_state.pmp[i].cfg_reg & PMP_LOCK) >> 4) |
> ((env->pmp_state.pmp[i].cfg_reg & PMP_READ) << 2) |
> (env->pmp_state.pmp[i].cfg_reg & PMP_WRITE) |
> @@ -364,7 +364,7 @@ bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
> * If mseccfg.MML Bit set, do the enhanced pmp priv check
> */
> if (mode == PRV_M) {
> - switch (epmp_operation) {
> + switch (smepmp_operation) {
> case 0:
> case 1:
> case 4:
> @@ -395,7 +395,7 @@ bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
> g_assert_not_reached();
> }
> } else {
> - switch (epmp_operation) {
> + switch (smepmp_operation) {
> case 0:
> case 8:
> case 9:
> @@ -576,7 +576,7 @@ void mseccfg_csr_write(CPURISCVState *env, target_ulong val)
> }
> }
>
> - if (riscv_cpu_cfg(env)->epmp) {
> + if (riscv_cpu_cfg(env)->ext_smepmp) {
> /* Sticky bits */
> val |= (env->mseccfg & (MSECCFG_MMWP | MSECCFG_MML));
> if ((val ^ env->mseccfg) & (MSECCFG_MMWP | MSECCFG_MML)) {
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