From nobody Sat May 18 04:46:30 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1686051553; cv=none; d=zohomail.com; s=zohoarc; b=Lp+Khnq12v3KBqGHrfFmVLz2TZzQl3K3suPYxiJMhpvgQ0Emx1MJ6MBRQ4ZYRV7i/wx8BImSVDjdR0mB/y9fY6UcYpjTD6bu776i3EpbAuoWl4G56znnUtfVPT7lados1YbS7MCkWidMLNQHOvyUjXSzhhCZcbBnIykhGf52/N4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1686051553; h=Content-Transfer-Encoding:Cc:Date:From:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Sender:Subject:To; bh=5XyhAMoDpcD2PvKAHbfJxoR+Hl1/S3rQpLL4TguLsrw=; b=JUXBRt39LII3g3Bvn/qHNW+DRA1f1rPrWpFiikFF5dHlE7KhzLhxNiLTiJ9xdKdQ1lKxhPryU1DRqTg8gdrp4/lGefoJ0NAsy17ba1Mp984/P9w5OvXhZoVytcAr0HsJZJ15KN8GvKnoBmczvgAmalTUt/dDlJVOHj0LmzwNy54= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1686051553457297.2550900907373; Tue, 6 Jun 2023 04:39:13 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q6V1C-0002hr-V1; Tue, 06 Jun 2023 07:38:30 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q6V1A-0002fz-Nt for qemu-devel@nongnu.org; Tue, 06 Jun 2023 07:38:28 -0400 Received: from mail-pf1-x430.google.com ([2607:f8b0:4864:20::430]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q6V15-0008A3-HE for qemu-devel@nongnu.org; Tue, 06 Jun 2023 07:38:25 -0400 Received: by mail-pf1-x430.google.com with SMTP id d2e1a72fcca58-657c4bcad0bso619813b3a.1 for ; Tue, 06 Jun 2023 04:38:20 -0700 (PDT) Received: from saptrishi.. ([2405:201:d019:c279:cac6:c564:908b:19a9]) by smtp.gmail.com with ESMTPSA id t24-20020aa79398000000b0063799398eaesm4470360pfe.51.2023.06.06.04.38.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 06 Jun 2023 04:38:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1686051499; x=1688643499; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=5XyhAMoDpcD2PvKAHbfJxoR+Hl1/S3rQpLL4TguLsrw=; b=WygHCKizb+31xW8hgoS/pdlUB7unymdWJ5tmHj1zUz6yFPUa4K0I9dmdsCF44OjSfG utT07KqVhMrqK/SeLVtGJUSXin8wvAhxeHMJWq0bCsf0sJKJpBlH7WEsT9q3EetWe/Hs jte9f90P5AUQAXGKAn0uflhNPIHso5Xzvz9A9JwrgSpN286b5/g9Fc7QBO2lfHj7KdOB zY1gakG2ou3TejYCnUBZfbrzPQ+i6TTot9RrJTxZTqG6NpUB5sngUnBSMDHQuLtpG0zn EedKNb7OTy3pPsKw+qyTpUnHI3hADiCnjKLwhDmWDn8uhMZqIJxBhupvWmwHWPkraUmP EcMg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1686051499; x=1688643499; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=5XyhAMoDpcD2PvKAHbfJxoR+Hl1/S3rQpLL4TguLsrw=; b=JWRUPnfqWlKBr0nHkfdDUAR4WQH9d9yjMWNucpPbTRkO6S5czd9RVetfuaiwJ9yBIF dYrZkX/5sOIwGFyYySCBwDV7x3nyI1kenev7CV5+OqGYVZWgaDcKsfyy2vpSn4m2i27p JnBVCuLJuZALOMv4+9IY9daJWim2xpSxMcJ+3M1o89OHY1KsjDbla9gpv6rHey8c3+5q xpUpHZu655O9IY5RwS058y5Z4RvpzXuDukkR+xtThFnfjdqDJEO+U4sSuyShX4tllaCG MasxUnxTeMHxd55XROCa3buJyrrnKBTctbx3V3OIp64QJVXNShOtrlTvp4o3OqE/xV6Y 8OYQ== X-Gm-Message-State: AC+VfDyaZOJm2YWwoHm4OHLTPV+yOITwKevRrp1orTa5E/cW7fGk98YH dgmCYLn8fUr3uLzYLP0kJBKa/Q== X-Google-Smtp-Source: ACHHUZ5LKWe0AnYdVrUxAuNYnV2/wzxutp9uSC2SQmcL+MB0nM4Tq7F3yYLbS8hJopjEGokfsqLOzQ== X-Received: by 2002:a05:6a20:4292:b0:111:a0e5:d29d with SMTP id o18-20020a056a20429200b00111a0e5d29dmr2706391pzj.4.1686051499538; Tue, 06 Jun 2023 04:38:19 -0700 (PDT) From: Himanshu Chauhan To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org Cc: Himanshu Chauhan Subject: [PATCH] Add epmp to extensions list and rename it to smepmp Date: Tue, 6 Jun 2023 17:08:12 +0530 Message-Id: <20230606113812.519723-1-hchauhan@ventanamicro.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::430; envelope-from=hchauhan@ventanamicro.com; helo=mail-pf1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1686051555023100001 Content-Type: text/plain; charset="utf-8" Smepmp is a ratified extension which qemu refers to as epmp. Rename epmp to smepmp and add it to extension list so that it is added to the isa string. Signed-off-by: Himanshu Chauhan Reviewed-by: Daniel Henrique Barboza --- target/riscv/cpu.c | 9 +++++---- target/riscv/cpu_cfg.h | 2 +- target/riscv/csr.c | 6 +++--- target/riscv/pmp.c | 12 ++++++------ 4 files changed, 15 insertions(+), 14 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 881bddf393..cf3d1c3207 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -127,6 +127,7 @@ static const struct isa_ext_data isa_edata_arr[] =3D { ISA_EXT_DATA_ENTRY(svinval, PRIV_VERSION_1_12_0, ext_svinval), ISA_EXT_DATA_ENTRY(svnapot, PRIV_VERSION_1_12_0, ext_svnapot), ISA_EXT_DATA_ENTRY(svpbmt, PRIV_VERSION_1_12_0, ext_svpbmt), + ISA_EXT_DATA_ENTRY(smepmp, PRIV_VERSION_1_12_0, ext_smepmp), ISA_EXT_DATA_ENTRY(xtheadba, PRIV_VERSION_1_11_0, ext_xtheadba), ISA_EXT_DATA_ENTRY(xtheadbb, PRIV_VERSION_1_11_0, ext_xtheadbb), ISA_EXT_DATA_ENTRY(xtheadbs, PRIV_VERSION_1_11_0, ext_xtheadbs), @@ -547,7 +548,7 @@ static void rv32_ibex_cpu_init(Object *obj) #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(cpu, VM_1_10_MBARE); #endif - cpu->cfg.epmp =3D true; + cpu->cfg.ext_smepmp =3D true; =20 /* inherited from parent obj via riscv_cpu_init() */ cpu->cfg.ext_ifencei =3D true; @@ -1336,12 +1337,12 @@ static void riscv_cpu_realize(DeviceState *dev, Err= or **errp) return; } =20 - if (cpu->cfg.epmp && !cpu->cfg.pmp) { + if (cpu->cfg.ext_smepmp && !cpu->cfg.pmp) { /* * Enhanced PMP should only be available * on harts with PMP support */ - error_setg(errp, "Invalid configuration: EPMP requires PMP support= "); + error_setg(errp, "Invalid configuration: SMEPMP requires PMP suppo= rt"); return; } =20 @@ -1676,7 +1677,7 @@ static Property riscv_cpu_extensions[] =3D { DEFINE_PROP_BOOL("x-zicond", RISCVCPU, cfg.ext_zicond, false), =20 /* ePMP 0.9.3 */ - DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false), + DEFINE_PROP_BOOL("smepmp", RISCVCPU, cfg.ext_smepmp, false), DEFINE_PROP_BOOL("x-smaia", RISCVCPU, cfg.ext_smaia, false), DEFINE_PROP_BOOL("x-ssaia", RISCVCPU, cfg.ext_ssaia, false), =20 diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h index c4a627d335..d79b022e35 100644 --- a/target/riscv/cpu_cfg.h +++ b/target/riscv/cpu_cfg.h @@ -87,6 +87,7 @@ struct RISCVCPUConfig { bool ext_zvfh; bool ext_zvfhmin; bool ext_smaia; + bool ext_smepmp; bool ext_ssaia; bool ext_sscofpmf; bool rvv_ta_all_1s; @@ -121,7 +122,6 @@ struct RISCVCPUConfig { uint16_t cboz_blocksize; bool mmu; bool pmp; - bool epmp; bool debug; bool misa_w; =20 diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 58499b5afc..d9bc591348 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -523,9 +523,9 @@ static RISCVException pmp(CPURISCVState *env, int csrno) return RISCV_EXCP_ILLEGAL_INST; } =20 -static RISCVException epmp(CPURISCVState *env, int csrno) +static RISCVException smepmp(CPURISCVState *env, int csrno) { - if (riscv_cpu_cfg(env)->epmp) { + if (riscv_cpu_cfg(env)->ext_smepmp) { return RISCV_EXCP_NONE; } =20 @@ -4356,7 +4356,7 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { [CSR_VSIPH] =3D { "vsiph", aia_hmode32, NULL, NULL, rmw_vs= iph }, =20 /* Physical Memory Protection */ - [CSR_MSECCFG] =3D { "mseccfg", epmp, read_mseccfg, write_mseccfg, + [CSR_MSECCFG] =3D { "mseccfg", smepmp, read_mseccfg, write_mseccfg, .min_priv_ver =3D PRIV_VERSION_1_11_0 }, [CSR_PMPCFG0] =3D { "pmpcfg0", pmp, read_pmpcfg, write_pmpcfg }, [CSR_PMPCFG1] =3D { "pmpcfg1", pmp, read_pmpcfg, write_pmpcfg }, diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c index 418738afd8..18246e1737 100644 --- a/target/riscv/pmp.c +++ b/target/riscv/pmp.c @@ -87,7 +87,7 @@ static bool pmp_write_cfg(CPURISCVState *env, uint32_t pm= p_index, uint8_t val) if (pmp_index < MAX_RISCV_PMPS) { bool locked =3D true; =20 - if (riscv_cpu_cfg(env)->epmp) { + if (riscv_cpu_cfg(env)->ext_smepmp) { /* mseccfg.RLB is set */ if (MSECCFG_RLB_ISSET(env)) { locked =3D false; @@ -337,9 +337,9 @@ bool pmp_hart_has_privs(CPURISCVState *env, target_ulon= g addr, =20 /* * Convert the PMP permissions to match the truth table in the - * ePMP spec. + * SMEPMP spec. */ - const uint8_t epmp_operation =3D + const uint8_t smepmp_operation =3D ((env->pmp_state.pmp[i].cfg_reg & PMP_LOCK) >> 4) | ((env->pmp_state.pmp[i].cfg_reg & PMP_READ) << 2) | (env->pmp_state.pmp[i].cfg_reg & PMP_WRITE) | @@ -364,7 +364,7 @@ bool pmp_hart_has_privs(CPURISCVState *env, target_ulon= g addr, * If mseccfg.MML Bit set, do the enhanced pmp priv check */ if (mode =3D=3D PRV_M) { - switch (epmp_operation) { + switch (smepmp_operation) { case 0: case 1: case 4: @@ -395,7 +395,7 @@ bool pmp_hart_has_privs(CPURISCVState *env, target_ulon= g addr, g_assert_not_reached(); } } else { - switch (epmp_operation) { + switch (smepmp_operation) { case 0: case 8: case 9: @@ -576,7 +576,7 @@ void mseccfg_csr_write(CPURISCVState *env, target_ulong= val) } } =20 - if (riscv_cpu_cfg(env)->epmp) { + if (riscv_cpu_cfg(env)->ext_smepmp) { /* Sticky bits */ val |=3D (env->mseccfg & (MSECCFG_MMWP | MSECCFG_MML)); if ((val ^ env->mseccfg) & (MSECCFG_MMWP | MSECCFG_MML)) { --=20 2.34.1