The following changes since commit b11728dc3ae67ddedf34b7a4f318170e7092803c:

  Merge tag 'pull-riscv-to-apply-20230224' of github.com:palmer-dabbelt/qemu into staging (2023-02-26 20:14:46 +0000)

are available in the Git repository at:

  https://git.linaro.org/people/pmaydell/qemu-arm.git pull-target-arm-20230227

for you to fetch changes up to e844f0c5d0bd2c4d8d3c1622eb2a88586c9c4677:

  hw: Replace qemu_or_irq typedef by OrIRQState (2023-02-27 13:27:05 +0000)

----------------------------------------------------------------
target-arm queue:
 * Various code cleanups
 * More refactoring working towards allowing a build
   without CONFIG_TCG

----------------------------------------------------------------
Claudio Fontana (2):
      target/arm: move helpers to tcg/
      target/arm: Move psci.c into the tcg directory

Fabiano Rosas (9):
      target/arm: Wrap breakpoint/watchpoint updates with tcg_enabled
      target/arm: Wrap TCG-only code in debug_helper.c
      target/arm: move translate modules to tcg/
      target/arm: Wrap arm_rebuild_hflags calls with tcg_enabled
      target/arm: Move hflags code into the tcg directory
      target/arm: Move regime_using_lpae_format into internal.h
      target/arm: Don't access TCG code when debugging with KVM
      cpu-defs.h: Expose CPUTLBEntryFull to non-TCG code
      tests/avocado: add machine:none tag to version.py

Philippe Mathieu-Daudé (13):
      hw/gpio/max7310: Simplify max7310_realize()
      hw/char/pl011: Un-inline pl011_create()
      hw/char/pl011: Open-code pl011_luminary_create()
      hw/char/xilinx_uartlite: Expose XILINX_UARTLITE QOM type
      hw/char/xilinx_uartlite: Open-code xilinx_uartlite_create()
      hw/char/cmsdk-apb-uart: Open-code cmsdk_apb_uart_create()
      hw/timer/cmsdk-apb-timer: Remove unused 'qdev-properties.h' header
      hw/intc/armv7m_nvic: Use QOM cast CPU() macro
      hw/arm/musicpal: Remove unused dummy MemoryRegion
      iothread: Remove unused IOThreadClass / IOTHREAD_CLASS
      hw/irq: Declare QOM macros using OBJECT_DECLARE_SIMPLE_TYPE()
      hw/or-irq: Declare QOM macros using OBJECT_DECLARE_SIMPLE_TYPE()
      hw: Replace qemu_or_irq typedef by OrIRQState

Thomas Huth (1):
      include/hw/arm/allwinner-a10.h: Remove superfluous includes from the header

 MAINTAINERS                              |   1 +
 include/exec/cpu-defs.h                  |   6 +
 include/hw/arm/allwinner-a10.h           |   2 -
 include/hw/arm/armsse.h                  |   6 +-
 include/hw/arm/bcm2835_peripherals.h     |   2 +-
 include/hw/arm/exynos4210.h              |   4 +-
 include/hw/arm/stm32f205_soc.h           |   2 +-
 include/hw/arm/stm32f405_soc.h           |   2 +-
 include/hw/arm/xlnx-versal.h             |   6 +-
 include/hw/arm/xlnx-zynqmp.h             |   2 +-
 include/hw/char/cmsdk-apb-uart.h         |  34 ---
 include/hw/char/pl011.h                  |  36 +--
 include/hw/char/xilinx_uartlite.h        |  22 +-
 include/hw/or-irq.h                      |   5 +-
 include/hw/timer/cmsdk-apb-timer.h       |   1 -
 target/arm/internals.h                   |  23 +-
 target/arm/{ => tcg}/translate-a64.h     |   0
 target/arm/{ => tcg}/translate.h         |   0
 target/arm/{ => tcg}/vec_internal.h      |   0
 target/arm/{ => tcg}/a32-uncond.decode   |   0
 target/arm/{ => tcg}/a32.decode          |   0
 target/arm/{ => tcg}/m-nocp.decode       |   0
 target/arm/{ => tcg}/mve.decode          |   0
 target/arm/{ => tcg}/neon-dp.decode      |   0
 target/arm/{ => tcg}/neon-ls.decode      |   0
 target/arm/{ => tcg}/neon-shared.decode  |   0
 target/arm/{ => tcg}/sme-fa64.decode     |   0
 target/arm/{ => tcg}/sme.decode          |   0
 target/arm/{ => tcg}/sve.decode          |   0
 target/arm/{ => tcg}/t16.decode          |   0
 target/arm/{ => tcg}/t32.decode          |   0
 target/arm/{ => tcg}/vfp-uncond.decode   |   0
 target/arm/{ => tcg}/vfp.decode          |   0
 hw/arm/allwinner-a10.c                   |   1 +
 hw/arm/boot.c                            |   6 +-
 hw/arm/exynos4210.c                      |   4 +-
 hw/arm/mps2-tz.c                         |   2 +-
 hw/arm/mps2.c                            |  41 ++-
 hw/arm/musicpal.c                        |   4 -
 hw/arm/stellaris.c                       |  11 +-
 hw/char/pl011.c                          |  17 ++
 hw/char/xilinx_uartlite.c                |   4 +-
 hw/core/irq.c                            |   9 +-
 hw/core/or-irq.c                         |  18 +-
 hw/gpio/max7310.c                        |   5 +-
 hw/intc/armv7m_nvic.c                    |  26 +-
 hw/microblaze/petalogix_s3adsp1800_mmu.c |   7 +-
 hw/pci-host/raven.c                      |   2 +-
 iothread.c                               |   4 -
 target/arm/arm-powerctl.c                |   7 +-
 target/arm/cpu.c                         |   9 +-
 target/arm/debug_helper.c                | 490 ++++++++++++++++---------------
 target/arm/helper.c                      | 411 +-------------------------
 target/arm/machine.c                     |  12 +-
 target/arm/ptw.c                         |   4 +
 target/arm/tcg-stubs.c                   |  27 ++
 target/arm/{ => tcg}/crypto_helper.c     |   0
 target/arm/{ => tcg}/helper-a64.c        |   0
 target/arm/tcg/hflags.c                  | 403 +++++++++++++++++++++++++
 target/arm/{ => tcg}/iwmmxt_helper.c     |   0
 target/arm/{ => tcg}/m_helper.c          |   0
 target/arm/{ => tcg}/mte_helper.c        |   0
 target/arm/{ => tcg}/mve_helper.c        |   0
 target/arm/{ => tcg}/neon_helper.c       |   0
 target/arm/{ => tcg}/op_helper.c         |   0
 target/arm/{ => tcg}/pauth_helper.c      |   0
 target/arm/{ => tcg}/psci.c              |   0
 target/arm/{ => tcg}/sme_helper.c        |   0
 target/arm/{ => tcg}/sve_helper.c        |   0
 target/arm/{ => tcg}/tlb_helper.c        |  18 --
 target/arm/{ => tcg}/translate-a64.c     |   0
 target/arm/{ => tcg}/translate-m-nocp.c  |   0
 target/arm/{ => tcg}/translate-mve.c     |   0
 target/arm/{ => tcg}/translate-neon.c    |   0
 target/arm/{ => tcg}/translate-sme.c     |   0
 target/arm/{ => tcg}/translate-sve.c     |   0
 target/arm/{ => tcg}/translate-vfp.c     |   0
 target/arm/{ => tcg}/translate.c         |   0
 target/arm/{ => tcg}/vec_helper.c        |   0
 target/arm/meson.build                   |  46 +--
 target/arm/tcg/meson.build               |  50 ++++
 tests/avocado/version.py                 |   1 +
 82 files changed, 918 insertions(+), 875 deletions(-)
 rename target/arm/{ => tcg}/translate-a64.h (100%)
 rename target/arm/{ => tcg}/translate.h (100%)
 rename target/arm/{ => tcg}/vec_internal.h (100%)
 rename target/arm/{ => tcg}/a32-uncond.decode (100%)
 rename target/arm/{ => tcg}/a32.decode (100%)
 rename target/arm/{ => tcg}/m-nocp.decode (100%)
 rename target/arm/{ => tcg}/mve.decode (100%)
 rename target/arm/{ => tcg}/neon-dp.decode (100%)
 rename target/arm/{ => tcg}/neon-ls.decode (100%)
 rename target/arm/{ => tcg}/neon-shared.decode (100%)
 rename target/arm/{ => tcg}/sme-fa64.decode (100%)
 rename target/arm/{ => tcg}/sme.decode (100%)
 rename target/arm/{ => tcg}/sve.decode (100%)
 rename target/arm/{ => tcg}/t16.decode (100%)
 rename target/arm/{ => tcg}/t32.decode (100%)
 rename target/arm/{ => tcg}/vfp-uncond.decode (100%)
 rename target/arm/{ => tcg}/vfp.decode (100%)
 create mode 100644 target/arm/tcg-stubs.c
 rename target/arm/{ => tcg}/crypto_helper.c (100%)
 rename target/arm/{ => tcg}/helper-a64.c (100%)
 create mode 100644 target/arm/tcg/hflags.c
 rename target/arm/{ => tcg}/iwmmxt_helper.c (100%)
 rename target/arm/{ => tcg}/m_helper.c (100%)
 rename target/arm/{ => tcg}/mte_helper.c (100%)
 rename target/arm/{ => tcg}/mve_helper.c (100%)
 rename target/arm/{ => tcg}/neon_helper.c (100%)
 rename target/arm/{ => tcg}/op_helper.c (100%)
 rename target/arm/{ => tcg}/pauth_helper.c (100%)
 rename target/arm/{ => tcg}/psci.c (100%)
 rename target/arm/{ => tcg}/sme_helper.c (100%)
 rename target/arm/{ => tcg}/sve_helper.c (100%)
 rename target/arm/{ => tcg}/tlb_helper.c (94%)
 rename target/arm/{ => tcg}/translate-a64.c (100%)
 rename target/arm/{ => tcg}/translate-m-nocp.c (100%)
 rename target/arm/{ => tcg}/translate-mve.c (100%)
 rename target/arm/{ => tcg}/translate-neon.c (100%)
 rename target/arm/{ => tcg}/translate-sme.c (100%)
 rename target/arm/{ => tcg}/translate-sve.c (100%)
 rename target/arm/{ => tcg}/translate-vfp.c (100%)
 rename target/arm/{ => tcg}/translate.c (100%)
 rename target/arm/{ => tcg}/vec_helper.c (100%)
 create mode 100644 target/arm/tcg/meson.build

On Mon, 27 Feb 2023 at 14:01, Peter Maydell <peter.maydell@linaro.org> wrote:
>
> The following changes since commit b11728dc3ae67ddedf34b7a4f318170e7092803c:
>
>   Merge tag 'pull-riscv-to-apply-20230224' of github.com:palmer-dabbelt/qemu into staging (2023-02-26 20:14:46 +0000)
>
> are available in the Git repository at:
>
>   https://git.linaro.org/people/pmaydell/qemu-arm.git pull-target-arm-20230227
>
> for you to fetch changes up to e844f0c5d0bd2c4d8d3c1622eb2a88586c9c4677:
>
>   hw: Replace qemu_or_irq typedef by OrIRQState (2023-02-27 13:27:05 +0000)
>
> ----------------------------------------------------------------
> target-arm queue:
>  * Various code cleanups
>  * More refactoring working towards allowing a build
>    without CONFIG_TCG
>


Applied, thanks.

Please update the changelog at https://wiki.qemu.org/ChangeLog/8.0
for any user-visible changes.

-- PMM