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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id s9-20020a5d4249000000b002c5598c14acsm7158514wrr.6.2023.02.27.06.01.05 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Feb 2023 06:01:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=DxEn9POx9LLw52m4ZF8v0HOcC8aENtYC1Crsbx0vnOw=; b=t1l9ZcGomuXQMrxZBrzcdoLvh+wloIYApVU3Ywr0/vLda2jUd9Bk2L8uAKFQgYDQbS SpFg58IMC+5VfzxxxtOBls+7K4uSeD3dSs/WUBi42dZ+ZWAFEmaWMQfVNTuZinGfCYtl 6ndX1vyy5ftixjEhpVMfOtGVFO5fs4LaTJstpaS51cVK8H0n1ZkI/Q1gKpt74+G5lp1X t+mIf8j6TvGkETVT4hLhmnFepCBYMLOKcLF67YttnggP9XaixnxSj127+tKZ/v9mMG+C /pTMHiblYdCUJrLUimXx/h9Cpm9jiNNc2vEew9/MaYb2+N/G+YFRRwAnE7cSL+VEmwVV T8mg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=DxEn9POx9LLw52m4ZF8v0HOcC8aENtYC1Crsbx0vnOw=; b=mjQgddyZVq0HIWTDiQR2nRPzOowafHTJ9ETL9DpNvNNW1M/cdr/7nRc6r2K14buca5 zY5K4pTfa2wArOCZ6dhWic0oVNtg+sqbTXFY7iY0HBq3WCm88xjdptGYln69z5HDvaPn F0IGTT9S/BtPf1rFaffpZj3e+bf5QDk2vagd6UFN6YenWSzuwMw3b2ccrkL3Nekbwoj+ Jp+Y73wVnggpZ1fJr1LcNxeND6owQ4zQy6bfmtVc4upS3j8WOJ0pkCG3uVVp7C3APESa nflS5+jxZXTniYqX55BiNeLGt5HtbWOnael7FH0AcOjqejTkJsOXFjBKrZCtw8Qyaryu neFw== X-Gm-Message-State: AO0yUKWpJeKPoNuK2GrC5IgpJZzD1XSEYiEWHA5GEuBHeKMZ8PNnsvAw 8puTNoJ7C/J0Gbqu7GPFp48TViVZCvR6+Kyt X-Google-Smtp-Source: AK7set/yBiuMN2dt9wierGG3nEBXTr6nOCiKh23x7u004VSHHJUXRgh6y5uQaqYh6sL4NMVPH1afRg== X-Received: by 2002:adf:dc0c:0:b0:2cb:f4:e59a with SMTP id t12-20020adfdc0c000000b002cb00f4e59amr3548924wri.71.1677506466356; Mon, 27 Feb 2023 06:01:06 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 01/25] include/hw/arm/allwinner-a10.h: Remove superfluous includes from the header Date: Mon, 27 Feb 2023 14:00:38 +0000 Message-Id: <20230227140102.3712344-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230227140102.3712344-1-peter.maydell@linaro.org> References: <20230227140102.3712344-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1677506557910100001 From: Thomas Huth pci_device.h is not needed at all in allwinner-a10.h, and serial.h is only needed by the corresponding .c file. Signed-off-by: Thomas Huth Reviewed-by: Alex Benn=C3=A9e Message-id: 20230215152233.210024-1-thuth@redhat.com Signed-off-by: Peter Maydell --- include/hw/arm/allwinner-a10.h | 2 -- hw/arm/allwinner-a10.c | 1 + 2 files changed, 1 insertion(+), 2 deletions(-) diff --git a/include/hw/arm/allwinner-a10.h b/include/hw/arm/allwinner-a10.h index 79e0c80568e..095afb225d6 100644 --- a/include/hw/arm/allwinner-a10.h +++ b/include/hw/arm/allwinner-a10.h @@ -1,9 +1,7 @@ #ifndef HW_ARM_ALLWINNER_A10_H #define HW_ARM_ALLWINNER_A10_H =20 -#include "hw/char/serial.h" #include "hw/arm/boot.h" -#include "hw/pci/pci_device.h" #include "hw/timer/allwinner-a10-pit.h" #include "hw/intc/allwinner-a10-pic.h" #include "hw/net/allwinner_emac.h" diff --git a/hw/arm/allwinner-a10.c b/hw/arm/allwinner-a10.c index dc1966ff7a2..b7ca795c712 100644 --- a/hw/arm/allwinner-a10.c +++ b/hw/arm/allwinner-a10.c @@ -18,6 +18,7 @@ #include "qemu/osdep.h" #include "qapi/error.h" #include "qemu/module.h" +#include "hw/char/serial.h" #include "hw/sysbus.h" #include "hw/arm/allwinner-a10.h" #include "hw/misc/unimp.h" --=20 2.34.1 From nobody Tue May 14 10:40:27 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1677506549; cv=none; d=zohomail.com; s=zohoarc; b=Qom1VMNeGQPYzBeygoURNTInQKreDxQrO9u4zee+1ktZntk4WRmbuBWT67sOtns6Yw2cO//fFVTIi0VdJ71i5HmmEZ+WD3Hkc29XuYa0uGV8vwBLgO7zV9TMYEi1h34IbFR1TvWXuVbn8Sb7eXjDw/8yRi6ZuHyMpW3WigJ2WF8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1677506549; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=vrjkaKCliIFkLE0ljnHmQFIiPqAoUGCU+4M0ENFMcrk=; b=IjXaJd/mTztDB8KDdd5prbaKPkNX3ULBTpYDn/qrQERuRRMjX+t+vjq+irTLYBdJoKTGlxbPcL4yJFmfBQ1A2D95n3UteeD++BCEYoCHwa0dcL5j/EH9w+1r65xrrkEACANWse1AGV2qrVxLB09tp3GyQZmMGcZcdROJt8LARas= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1677506549752554.1783971644878; Mon, 27 Feb 2023 06:02:29 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pWe4q-00018r-7u; Mon, 27 Feb 2023 09:02:04 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pWe3z-0000VE-Ok for qemu-devel@nongnu.org; Mon, 27 Feb 2023 09:01:11 -0500 Received: from mail-wr1-x42c.google.com ([2a00:1450:4864:20::42c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pWe3x-0007WR-Uq for qemu-devel@nongnu.org; Mon, 27 Feb 2023 09:01:11 -0500 Received: by mail-wr1-x42c.google.com with SMTP id r7so6329417wrz.6 for ; Mon, 27 Feb 2023 06:01:09 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id s9-20020a5d4249000000b002c5598c14acsm7158514wrr.6.2023.02.27.06.01.06 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Feb 2023 06:01:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=vrjkaKCliIFkLE0ljnHmQFIiPqAoUGCU+4M0ENFMcrk=; b=gRNlgXABrQlLN4CfgW1Z61p3m+VGHgsGU8hF7Yvj5/QE82BS81YVdsqXEx1/NGwYTu JMaTJTUJQFB6WcYMhcRkAVVQnTJy6ECw6i5lc6vh20fLXKj5ToWe/UjWqN5dWxT2482u S27zOUvnE03xwtAIog27jdG6Q2McFMT7QlpzLJDxKCT8apmC5OAb7V5XqChF5e3hTZ/n /yIIc+pp1EKlY+KXdFMP3yy1K8KlH8c5FWWBuOzZff+7Xp80wmDc7oSTOKHH/AX32n+Z 5SiYVmTi6Qo01Oq5Jw56qJRz0oZpUesu0CmQlpc6IdMiCMR5Sxb96OqGBaxsvjz2M+lu itvA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=vrjkaKCliIFkLE0ljnHmQFIiPqAoUGCU+4M0ENFMcrk=; b=I2rozQbDILvhtSqWMOqtV2pEyFaekqEt1V0sdZqSQAQ+rgAAxCn95p8xtLfKBWg6Rr p/iZUBpdnHet16BAvJmnymJS0YMxkreUYX0816dhnzyUdTkQ6ajld/waUkD6SWvtXFzu +idl+zAg1I6c0P++uREufbdXYYdM6LQ/APA6p3CT20XnAFUOMcoW8ektTTUPHqyZlv+x /r++nAtF4qytPHolMzJu43gBOlwDyiExvXM3r1bIwMs4XW7Sx9ywEtSS7MwHxZ5y6ozs eAPR4TfSPKoEptIrkCb8IbZl0Xb/QwA4pY+N/y7q06xb82xlH++f5qnVJVPnUxybN8SV AMDw== X-Gm-Message-State: AO0yUKV21in3HW57DYGkQvqZfDvVAXoKZ7RkckShRaZzsZ6/Cm08d8z7 zDeGljQfRGPZ0OAQWj2h7bvCUGXmOSdkYdad X-Google-Smtp-Source: AK7set92RCYaHHmN6+NU38W2Mf/WseupTp2C/P0IQzcgLFWxtU9LBhvnWvSQgaZIg7Nop+DOSWWpjQ== X-Received: by 2002:a5d:4447:0:b0:2c9:b3a9:b080 with SMTP id x7-20020a5d4447000000b002c9b3a9b080mr6098768wrr.16.1677506468299; Mon, 27 Feb 2023 06:01:08 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 02/25] target/arm: Wrap breakpoint/watchpoint updates with tcg_enabled Date: Mon, 27 Feb 2023 14:00:39 +0000 Message-Id: <20230227140102.3712344-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230227140102.3712344-1-peter.maydell@linaro.org> References: <20230227140102.3712344-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1677506598468100001 Content-Type: text/plain; charset="utf-8" From: Fabiano Rosas This is in preparation for restricting compilation of some parts of debug_helper.c to TCG only. Signed-off-by: Fabiano Rosas Reviewed-by: Richard Henderson Signed-off-by: Peter Maydell --- target/arm/cpu.c | 6 ++++-- target/arm/debug_helper.c | 16 ++++++++++++---- target/arm/machine.c | 7 +++++-- 3 files changed, 21 insertions(+), 8 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 876ab8f3bf8..da416f7b1cb 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -539,8 +539,10 @@ static void arm_cpu_reset_hold(Object *obj) } #endif =20 - hw_breakpoint_update_all(cpu); - hw_watchpoint_update_all(cpu); + if (tcg_enabled()) { + hw_breakpoint_update_all(cpu); + hw_watchpoint_update_all(cpu); + } arm_rebuild_hflags(env); } =20 diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c index 3c671c88c1a..3325eb9d7df 100644 --- a/target/arm/debug_helper.c +++ b/target/arm/debug_helper.c @@ -939,7 +939,9 @@ static void dbgwvr_write(CPUARMState *env, const ARMCPR= egInfo *ri, value &=3D ~3ULL; =20 raw_write(env, ri, value); - hw_watchpoint_update(cpu, i); + if (tcg_enabled()) { + hw_watchpoint_update(cpu, i); + } } =20 static void dbgwcr_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -949,7 +951,9 @@ static void dbgwcr_write(CPUARMState *env, const ARMCPR= egInfo *ri, int i =3D ri->crm; =20 raw_write(env, ri, value); - hw_watchpoint_update(cpu, i); + if (tcg_enabled()) { + hw_watchpoint_update(cpu, i); + } } =20 void hw_breakpoint_update(ARMCPU *cpu, int n) @@ -1062,7 +1066,9 @@ static void dbgbvr_write(CPUARMState *env, const ARMC= PRegInfo *ri, int i =3D ri->crm; =20 raw_write(env, ri, value); - hw_breakpoint_update(cpu, i); + if (tcg_enabled()) { + hw_breakpoint_update(cpu, i); + } } =20 static void dbgbcr_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -1079,7 +1085,9 @@ static void dbgbcr_write(CPUARMState *env, const ARMC= PRegInfo *ri, value =3D deposit64(value, 8, 1, extract64(value, 7, 1)); =20 raw_write(env, ri, value); - hw_breakpoint_update(cpu, i); + if (tcg_enabled()) { + hw_breakpoint_update(cpu, i); + } } =20 void define_debug_regs(ARMCPU *cpu) diff --git a/target/arm/machine.c b/target/arm/machine.c index b4c3850570c..fd6323f6d8a 100644 --- a/target/arm/machine.c +++ b/target/arm/machine.c @@ -2,6 +2,7 @@ #include "cpu.h" #include "qemu/error-report.h" #include "sysemu/kvm.h" +#include "sysemu/tcg.h" #include "kvm_arm.h" #include "internals.h" #include "migration/cpu.h" @@ -848,8 +849,10 @@ static int cpu_post_load(void *opaque, int version_id) return -1; } =20 - hw_breakpoint_update_all(cpu); - hw_watchpoint_update_all(cpu); + if (tcg_enabled()) { + hw_breakpoint_update_all(cpu); + hw_watchpoint_update_all(cpu); + } =20 /* * TCG gen_update_fp_context() relies on the invariant that --=20 2.34.1 From nobody Tue May 14 10:40:27 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1677506939; cv=none; d=zohomail.com; s=zohoarc; b=Tw9G+0fasbxdVuprA6xleW7nj0ZPavFF2+O8oXQZaN6mUAOaCY7NSwbp2KO5v6R3fBJocHV0RDRLkwyMa7/Qnqh6cxAQK/nTJ6y99dpO8q67ZuNiH673sGQ1D3Xuk3KQaZGEQzOliw+4ug5zhdD0BZX6ZU0jCcmvYz4ShsujpaM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1677506939; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id s9-20020a5d4249000000b002c5598c14acsm7158514wrr.6.2023.02.27.06.01.08 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Feb 2023 06:01:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=bE93Hku4a49BxWD57nAmzE6RVeycvKgkJSiaEIVzgyM=; b=cttRIdDnTLIWVpKXNinp7BxgUlMnCzEHvR/J8bg6B8aEBLX9XaSGxXknR73qrVbnNi X3VyH5Td1WroJ+Ig+CUjtHmjSAr28i9HG/jHqkHzrYaR2xaMMww9pCoIyfjRmDi8UNKb I2QxOWNdHg+MkULlsRjaiudmmVlcFPgWdKuDF5BA8sQBWdGS0CHBxHSCdsejRT0i0GTC kHgwQnJLYTmV3OIBE4dcovaWdenuNEWtI83IAOpI3WVW4WL+vmwH+wKjayjXTmdw2QLn q/Mo2Ka/pcxBs2c3EFL0rfrBF7aoNuA1U4XroenVG49b2PloDZ2QyBW3xYLOyrX+4XTL 7d+g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=bE93Hku4a49BxWD57nAmzE6RVeycvKgkJSiaEIVzgyM=; b=4gJl+ptqustAfl6awYV6GLEStYa3CZXc8zwtUg5/aXpRQpxEH1+WGlTq4/PKDVQ9fK nbPMQDakiCzjuKiZWucoWcBsteSGNprhxiPmY0d4KREnrNDd9rRyJZP/BDLg/pxu3A1C KyRAhlll4dE6hl+czeo8PnivCuKKmngeNpzopn1GAderOVcf9SyfGyyZFwBKsKW6yWrS uGdQKZxN73NsrRDBfHIJeDKlhX7+LLy92pxcUQnFOLzKKKiq/K0uCh2FV6BqNl2Pon9u AIVzp8TZ2B/5pOGg4EHJD72g8OFCrSj/mbQDJympmtUrRsNk5iL7SedyxrAgiRou1Era BUEg== X-Gm-Message-State: AO0yUKVnOFLq4UKxI6Pv8FrDdZQAuyDDWyQEoP3ZOZm03DSXMYdp1Vj1 l3yHdGBbadeC6k7jQRWaJXqqQXbjXLhoYME9 X-Google-Smtp-Source: AK7set8Mb8jnRPd4wZ0GjiGwdrR4iAlJt1J9nO6tMhjVYZHyoqIAFCt5rDLgoq4+r4DpcA34CL2WzQ== X-Received: by 2002:adf:ef8e:0:b0:2c7:83b:9d20 with SMTP id d14-20020adfef8e000000b002c7083b9d20mr15669589wro.34.1677506469590; Mon, 27 Feb 2023 06:01:09 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 03/25] target/arm: Wrap TCG-only code in debug_helper.c Date: Mon, 27 Feb 2023 14:00:40 +0000 Message-Id: <20230227140102.3712344-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230227140102.3712344-1-peter.maydell@linaro.org> References: <20230227140102.3712344-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1677506941111100012 Content-Type: text/plain; charset="utf-8" From: Fabiano Rosas The next few patches will move helpers under CONFIG_TCG. We'd prefer to keep the debug helpers and debug registers close together, so rearrange the file a bit to be able to wrap the helpers with a TCG ifdef. Signed-off-by: Fabiano Rosas Reviewed-by: Richard Henderson Signed-off-by: Peter Maydell --- target/arm/debug_helper.c | 476 +++++++++++++++++++------------------- 1 file changed, 239 insertions(+), 237 deletions(-) diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c index 3325eb9d7df..dfc8b2a1a5d 100644 --- a/target/arm/debug_helper.c +++ b/target/arm/debug_helper.c @@ -12,8 +12,9 @@ #include "cpregs.h" #include "exec/exec-all.h" #include "exec/helper-proto.h" +#include "sysemu/tcg.h" =20 - +#ifdef CONFIG_TCG /* Return the Exception Level targeted by debug exceptions. */ static int arm_debug_target_el(CPUARMState *env) { @@ -536,6 +537,243 @@ void HELPER(exception_swstep)(CPUARMState *env, uint3= 2_t syndrome) raise_exception_debug(env, EXCP_UDEF, syndrome); } =20 +void hw_watchpoint_update(ARMCPU *cpu, int n) +{ + CPUARMState *env =3D &cpu->env; + vaddr len =3D 0; + vaddr wvr =3D env->cp15.dbgwvr[n]; + uint64_t wcr =3D env->cp15.dbgwcr[n]; + int mask; + int flags =3D BP_CPU | BP_STOP_BEFORE_ACCESS; + + if (env->cpu_watchpoint[n]) { + cpu_watchpoint_remove_by_ref(CPU(cpu), env->cpu_watchpoint[n]); + env->cpu_watchpoint[n] =3D NULL; + } + + if (!FIELD_EX64(wcr, DBGWCR, E)) { + /* E bit clear : watchpoint disabled */ + return; + } + + switch (FIELD_EX64(wcr, DBGWCR, LSC)) { + case 0: + /* LSC 00 is reserved and must behave as if the wp is disabled */ + return; + case 1: + flags |=3D BP_MEM_READ; + break; + case 2: + flags |=3D BP_MEM_WRITE; + break; + case 3: + flags |=3D BP_MEM_ACCESS; + break; + } + + /* + * Attempts to use both MASK and BAS fields simultaneously are + * CONSTRAINED UNPREDICTABLE; we opt to ignore BAS in this case, + * thus generating a watchpoint for every byte in the masked region. + */ + mask =3D FIELD_EX64(wcr, DBGWCR, MASK); + if (mask =3D=3D 1 || mask =3D=3D 2) { + /* + * Reserved values of MASK; we must act as if the mask value was + * some non-reserved value, or as if the watchpoint were disabled. + * We choose the latter. + */ + return; + } else if (mask) { + /* Watchpoint covers an aligned area up to 2GB in size */ + len =3D 1ULL << mask; + /* + * If masked bits in WVR are not zero it's CONSTRAINED UNPREDICTAB= LE + * whether the watchpoint fires when the unmasked bits match; we o= pt + * to generate the exceptions. + */ + wvr &=3D ~(len - 1); + } else { + /* Watchpoint covers bytes defined by the byte address select bits= */ + int bas =3D FIELD_EX64(wcr, DBGWCR, BAS); + int basstart; + + if (extract64(wvr, 2, 1)) { + /* + * Deprecated case of an only 4-aligned address. BAS[7:4] are + * ignored, and BAS[3:0] define which bytes to watch. + */ + bas &=3D 0xf; + } + + if (bas =3D=3D 0) { + /* This must act as if the watchpoint is disabled */ + return; + } + + /* + * The BAS bits are supposed to be programmed to indicate a contig= uous + * range of bytes. Otherwise it is CONSTRAINED UNPREDICTABLE wheth= er + * we fire for each byte in the word/doubleword addressed by the W= VR. + * We choose to ignore any non-zero bits after the first range of = 1s. + */ + basstart =3D ctz32(bas); + len =3D cto32(bas >> basstart); + wvr +=3D basstart; + } + + cpu_watchpoint_insert(CPU(cpu), wvr, len, flags, + &env->cpu_watchpoint[n]); +} + +void hw_watchpoint_update_all(ARMCPU *cpu) +{ + int i; + CPUARMState *env =3D &cpu->env; + + /* + * Completely clear out existing QEMU watchpoints and our array, to + * avoid possible stale entries following migration load. + */ + cpu_watchpoint_remove_all(CPU(cpu), BP_CPU); + memset(env->cpu_watchpoint, 0, sizeof(env->cpu_watchpoint)); + + for (i =3D 0; i < ARRAY_SIZE(cpu->env.cpu_watchpoint); i++) { + hw_watchpoint_update(cpu, i); + } +} + +void hw_breakpoint_update(ARMCPU *cpu, int n) +{ + CPUARMState *env =3D &cpu->env; + uint64_t bvr =3D env->cp15.dbgbvr[n]; + uint64_t bcr =3D env->cp15.dbgbcr[n]; + vaddr addr; + int bt; + int flags =3D BP_CPU; + + if (env->cpu_breakpoint[n]) { + cpu_breakpoint_remove_by_ref(CPU(cpu), env->cpu_breakpoint[n]); + env->cpu_breakpoint[n] =3D NULL; + } + + if (!extract64(bcr, 0, 1)) { + /* E bit clear : watchpoint disabled */ + return; + } + + bt =3D extract64(bcr, 20, 4); + + switch (bt) { + case 4: /* unlinked address mismatch (reserved if AArch64) */ + case 5: /* linked address mismatch (reserved if AArch64) */ + qemu_log_mask(LOG_UNIMP, + "arm: address mismatch breakpoint types not implemen= ted\n"); + return; + case 0: /* unlinked address match */ + case 1: /* linked address match */ + { + /* + * Bits [1:0] are RES0. + * + * It is IMPLEMENTATION DEFINED whether bits [63:49] + * ([63:53] for FEAT_LVA) are hardwired to a copy of the sign bit + * of the VA field ([48] or [52] for FEAT_LVA), or whether the + * value is read as written. It is CONSTRAINED UNPREDICTABLE + * whether the RESS bits are ignored when comparing an address. + * Therefore we are allowed to compare the entire register, which + * lets us avoid considering whether FEAT_LVA is actually enabled. + * + * The BAS field is used to allow setting breakpoints on 16-bit + * wide instructions; it is CONSTRAINED UNPREDICTABLE whether + * a bp will fire if the addresses covered by the bp and the addre= sses + * covered by the insn overlap but the insn doesn't start at the + * start of the bp address range. We choose to require the insn and + * the bp to have the same address. The constraints on writing to + * BAS enforced in dbgbcr_write mean we have only four cases: + * 0b0000 =3D> no breakpoint + * 0b0011 =3D> breakpoint on addr + * 0b1100 =3D> breakpoint on addr + 2 + * 0b1111 =3D> breakpoint on addr + * See also figure D2-3 in the v8 ARM ARM (DDI0487A.c). + */ + int bas =3D extract64(bcr, 5, 4); + addr =3D bvr & ~3ULL; + if (bas =3D=3D 0) { + return; + } + if (bas =3D=3D 0xc) { + addr +=3D 2; + } + break; + } + case 2: /* unlinked context ID match */ + case 8: /* unlinked VMID match (reserved if no EL2) */ + case 10: /* unlinked context ID and VMID match (reserved if no EL2) */ + qemu_log_mask(LOG_UNIMP, + "arm: unlinked context breakpoint types not implemen= ted\n"); + return; + case 9: /* linked VMID match (reserved if no EL2) */ + case 11: /* linked context ID and VMID match (reserved if no EL2) */ + case 3: /* linked context ID match */ + default: + /* + * We must generate no events for Linked context matches (unless + * they are linked to by some other bp/wp, which is handled in + * updates for the linking bp/wp). We choose to also generate no e= vents + * for reserved values. + */ + return; + } + + cpu_breakpoint_insert(CPU(cpu), addr, flags, &env->cpu_breakpoint[n]); +} + +void hw_breakpoint_update_all(ARMCPU *cpu) +{ + int i; + CPUARMState *env =3D &cpu->env; + + /* + * Completely clear out existing QEMU breakpoints and our array, to + * avoid possible stale entries following migration load. + */ + cpu_breakpoint_remove_all(CPU(cpu), BP_CPU); + memset(env->cpu_breakpoint, 0, sizeof(env->cpu_breakpoint)); + + for (i =3D 0; i < ARRAY_SIZE(cpu->env.cpu_breakpoint); i++) { + hw_breakpoint_update(cpu, i); + } +} + +#if !defined(CONFIG_USER_ONLY) + +vaddr arm_adjust_watchpoint_address(CPUState *cs, vaddr addr, int len) +{ + ARMCPU *cpu =3D ARM_CPU(cs); + CPUARMState *env =3D &cpu->env; + + /* + * In BE32 system mode, target memory is stored byteswapped (on a + * little-endian host system), and by the time we reach here (via an + * opcode helper) the addresses of subword accesses have been adjusted + * to account for that, which means that watchpoints will not match. + * Undo the adjustment here. + */ + if (arm_sctlr_b(env)) { + if (len =3D=3D 1) { + addr ^=3D 3; + } else if (len =3D=3D 2) { + addr ^=3D 2; + } + } + + return addr; +} + +#endif /* !CONFIG_USER_ONLY */ +#endif /* CONFIG_TCG */ + /* * Check for traps to "powerdown debug" registers, which are controlled * by MDCR.TDOSA @@ -813,112 +1051,6 @@ static const ARMCPRegInfo debug_lpae_cp_reginfo[] = =3D { .access =3D PL0_R, .type =3D ARM_CP_CONST | ARM_CP_64BIT, .resetvalu= e =3D 0 }, }; =20 -void hw_watchpoint_update(ARMCPU *cpu, int n) -{ - CPUARMState *env =3D &cpu->env; - vaddr len =3D 0; - vaddr wvr =3D env->cp15.dbgwvr[n]; - uint64_t wcr =3D env->cp15.dbgwcr[n]; - int mask; - int flags =3D BP_CPU | BP_STOP_BEFORE_ACCESS; - - if (env->cpu_watchpoint[n]) { - cpu_watchpoint_remove_by_ref(CPU(cpu), env->cpu_watchpoint[n]); - env->cpu_watchpoint[n] =3D NULL; - } - - if (!FIELD_EX64(wcr, DBGWCR, E)) { - /* E bit clear : watchpoint disabled */ - return; - } - - switch (FIELD_EX64(wcr, DBGWCR, LSC)) { - case 0: - /* LSC 00 is reserved and must behave as if the wp is disabled */ - return; - case 1: - flags |=3D BP_MEM_READ; - break; - case 2: - flags |=3D BP_MEM_WRITE; - break; - case 3: - flags |=3D BP_MEM_ACCESS; - break; - } - - /* - * Attempts to use both MASK and BAS fields simultaneously are - * CONSTRAINED UNPREDICTABLE; we opt to ignore BAS in this case, - * thus generating a watchpoint for every byte in the masked region. - */ - mask =3D FIELD_EX64(wcr, DBGWCR, MASK); - if (mask =3D=3D 1 || mask =3D=3D 2) { - /* - * Reserved values of MASK; we must act as if the mask value was - * some non-reserved value, or as if the watchpoint were disabled. - * We choose the latter. - */ - return; - } else if (mask) { - /* Watchpoint covers an aligned area up to 2GB in size */ - len =3D 1ULL << mask; - /* - * If masked bits in WVR are not zero it's CONSTRAINED UNPREDICTAB= LE - * whether the watchpoint fires when the unmasked bits match; we o= pt - * to generate the exceptions. - */ - wvr &=3D ~(len - 1); - } else { - /* Watchpoint covers bytes defined by the byte address select bits= */ - int bas =3D FIELD_EX64(wcr, DBGWCR, BAS); - int basstart; - - if (extract64(wvr, 2, 1)) { - /* - * Deprecated case of an only 4-aligned address. BAS[7:4] are - * ignored, and BAS[3:0] define which bytes to watch. - */ - bas &=3D 0xf; - } - - if (bas =3D=3D 0) { - /* This must act as if the watchpoint is disabled */ - return; - } - - /* - * The BAS bits are supposed to be programmed to indicate a contig= uous - * range of bytes. Otherwise it is CONSTRAINED UNPREDICTABLE wheth= er - * we fire for each byte in the word/doubleword addressed by the W= VR. - * We choose to ignore any non-zero bits after the first range of = 1s. - */ - basstart =3D ctz32(bas); - len =3D cto32(bas >> basstart); - wvr +=3D basstart; - } - - cpu_watchpoint_insert(CPU(cpu), wvr, len, flags, - &env->cpu_watchpoint[n]); -} - -void hw_watchpoint_update_all(ARMCPU *cpu) -{ - int i; - CPUARMState *env =3D &cpu->env; - - /* - * Completely clear out existing QEMU watchpoints and our array, to - * avoid possible stale entries following migration load. - */ - cpu_watchpoint_remove_all(CPU(cpu), BP_CPU); - memset(env->cpu_watchpoint, 0, sizeof(env->cpu_watchpoint)); - - for (i =3D 0; i < ARRAY_SIZE(cpu->env.cpu_watchpoint); i++) { - hw_watchpoint_update(cpu, i); - } -} - static void dbgwvr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { @@ -956,109 +1088,6 @@ static void dbgwcr_write(CPUARMState *env, const ARM= CPRegInfo *ri, } } =20 -void hw_breakpoint_update(ARMCPU *cpu, int n) -{ - CPUARMState *env =3D &cpu->env; - uint64_t bvr =3D env->cp15.dbgbvr[n]; - uint64_t bcr =3D env->cp15.dbgbcr[n]; - vaddr addr; - int bt; - int flags =3D BP_CPU; - - if (env->cpu_breakpoint[n]) { - cpu_breakpoint_remove_by_ref(CPU(cpu), env->cpu_breakpoint[n]); - env->cpu_breakpoint[n] =3D NULL; - } - - if (!extract64(bcr, 0, 1)) { - /* E bit clear : watchpoint disabled */ - return; - } - - bt =3D extract64(bcr, 20, 4); - - switch (bt) { - case 4: /* unlinked address mismatch (reserved if AArch64) */ - case 5: /* linked address mismatch (reserved if AArch64) */ - qemu_log_mask(LOG_UNIMP, - "arm: address mismatch breakpoint types not implemen= ted\n"); - return; - case 0: /* unlinked address match */ - case 1: /* linked address match */ - { - /* - * Bits [1:0] are RES0. - * - * It is IMPLEMENTATION DEFINED whether bits [63:49] - * ([63:53] for FEAT_LVA) are hardwired to a copy of the sign bit - * of the VA field ([48] or [52] for FEAT_LVA), or whether the - * value is read as written. It is CONSTRAINED UNPREDICTABLE - * whether the RESS bits are ignored when comparing an address. - * Therefore we are allowed to compare the entire register, which - * lets us avoid considering whether FEAT_LVA is actually enabled. - * - * The BAS field is used to allow setting breakpoints on 16-bit - * wide instructions; it is CONSTRAINED UNPREDICTABLE whether - * a bp will fire if the addresses covered by the bp and the addre= sses - * covered by the insn overlap but the insn doesn't start at the - * start of the bp address range. We choose to require the insn and - * the bp to have the same address. The constraints on writing to - * BAS enforced in dbgbcr_write mean we have only four cases: - * 0b0000 =3D> no breakpoint - * 0b0011 =3D> breakpoint on addr - * 0b1100 =3D> breakpoint on addr + 2 - * 0b1111 =3D> breakpoint on addr - * See also figure D2-3 in the v8 ARM ARM (DDI0487A.c). - */ - int bas =3D extract64(bcr, 5, 4); - addr =3D bvr & ~3ULL; - if (bas =3D=3D 0) { - return; - } - if (bas =3D=3D 0xc) { - addr +=3D 2; - } - break; - } - case 2: /* unlinked context ID match */ - case 8: /* unlinked VMID match (reserved if no EL2) */ - case 10: /* unlinked context ID and VMID match (reserved if no EL2) */ - qemu_log_mask(LOG_UNIMP, - "arm: unlinked context breakpoint types not implemen= ted\n"); - return; - case 9: /* linked VMID match (reserved if no EL2) */ - case 11: /* linked context ID and VMID match (reserved if no EL2) */ - case 3: /* linked context ID match */ - default: - /* - * We must generate no events for Linked context matches (unless - * they are linked to by some other bp/wp, which is handled in - * updates for the linking bp/wp). We choose to also generate no e= vents - * for reserved values. - */ - return; - } - - cpu_breakpoint_insert(CPU(cpu), addr, flags, &env->cpu_breakpoint[n]); -} - -void hw_breakpoint_update_all(ARMCPU *cpu) -{ - int i; - CPUARMState *env =3D &cpu->env; - - /* - * Completely clear out existing QEMU breakpoints and our array, to - * avoid possible stale entries following migration load. - */ - cpu_breakpoint_remove_all(CPU(cpu), BP_CPU); - memset(env->cpu_breakpoint, 0, sizeof(env->cpu_breakpoint)); - - for (i =3D 0; i < ARRAY_SIZE(cpu->env.cpu_breakpoint); i++) { - hw_breakpoint_update(cpu, i); - } -} - static void dbgbvr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { @@ -1210,30 +1239,3 @@ void define_debug_regs(ARMCPU *cpu) g_free(dbgwcr_el1_name); } } - -#if !defined(CONFIG_USER_ONLY) - -vaddr arm_adjust_watchpoint_address(CPUState *cs, vaddr addr, int len) -{ - ARMCPU *cpu =3D ARM_CPU(cs); - CPUARMState *env =3D &cpu->env; - - /* - * In BE32 system mode, target memory is stored byteswapped (on a - * little-endian host system), and by the time we reach here (via an - * opcode helper) the addresses of subword accesses have been adjusted - * to account for that, which means that watchpoints will not match. - * Undo the adjustment here. - */ - if (arm_sctlr_b(env)) { - if (len =3D=3D 1) { - addr ^=3D 3; - } else if (len =3D=3D 2) { - addr ^=3D 2; - } - } - - return addr; -} - -#endif --=20 2.34.1 From nobody Tue May 14 10:40:27 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1677506607; cv=none; d=zohomail.com; s=zohoarc; b=epIKO2d7VFw7+C08e3zQhUpn8Cw8C3niFA405Wij6fBCaZh+4BmZG6I7f0v8l70ReoCaX2e+XCw7Kt/o0WSWJQaH89WQLJoh4fHqd68R7lX97dqTz5vRGZEmzn2cezf9SO7vmpHMfkyHMWKn6YSDmtHFYhvjLZUkPYOyArmm+WE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1677506607; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=yWuIpfN973PjPZqsEuqLsmILfrrzNt0DJYDKzdG9yUE=; b=nY8arzOK+jklYbWvyM5egAvAV/0CmGMMpN0kunhq9AdQhDRbiSlSmnstM4vu7bDA8TyNtvBhsoksJT5vwzP+cMAGcxt7LGQJG0GqBH+uis3QtrMV+LKXCYwr9iWoqTxEKRMvJe7MRBCwaSCvJSaRiIcJZZXJ0h2p1LO7r/u3EGQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1677506607041531.5337020538898; Mon, 27 Feb 2023 06:03:27 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pWe5E-00034H-10; Mon, 27 Feb 2023 09:02:28 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pWe45-0000dJ-Kr for qemu-devel@nongnu.org; Mon, 27 Feb 2023 09:01:29 -0500 Received: from mail-wm1-x32c.google.com ([2a00:1450:4864:20::32c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pWe40-0007Ww-M0 for qemu-devel@nongnu.org; Mon, 27 Feb 2023 09:01:14 -0500 Received: by mail-wm1-x32c.google.com with SMTP id r19-20020a05600c459300b003eb3e2a5e7bso2250201wmo.0 for ; Mon, 27 Feb 2023 06:01:12 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id s9-20020a5d4249000000b002c5598c14acsm7158514wrr.6.2023.02.27.06.01.09 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Feb 2023 06:01:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=yWuIpfN973PjPZqsEuqLsmILfrrzNt0DJYDKzdG9yUE=; b=hfaGH2e0HckZ0GVT5xJ+NNrEo8UjdQ2L1hoqUgCJywc2a2q3UP/AlFEzNG0NBJXDOY wETuo08Lq0jmLPwJwEK0fC9teP/6KWsxGE0xCaQaxrWgMrYGy65nN4qsW7ODaojUfqT6 lAs/sxfwq5ltKqQ+zQnnMzJHkdf89oMgSaVqI8/YIjx2HeQ2va5fAASkipPnbmtCRPMs qJ4a9WMCo9PqeKO5TTMk/geRcyfSLXLHQ/lzWm69UDlqbi+gQRP973KpP/tmA4bPzv9u PKL6/dn+nPsgkCAPkuLJWmTiTsZi2BePpTG0i6/8kMVsUqGTpPd9km9lzZ/wtP5Tm6XX GbuQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=yWuIpfN973PjPZqsEuqLsmILfrrzNt0DJYDKzdG9yUE=; b=HVonET8lB9T1jqThcb5OsqRwbp+jzpWvqpd1hh2/QTmF6B2d7BKyziU79sATirnUyV 3e9hab/hR7FwC5eOCY3Bm+cGvCEy3kcLIoaPSkVmOtHvtNkh+fSmXvuK2KU/DwZhL4hB iouQvT4rpvAWEypjM73CdCdiOqyNvN6aLZNc4odDYR/ifivMbsbsHX4oFuByWKObs5wP /knvj7CBKSMEYJ7xDsgoNFlUD9meQq8ZwOtJhduPVCzjhs/fWszggBIMAhDGTylyCOMn /9NW9ozNAE+4B27V+vrvynRcffSVVjUQ+u6vg9hMKnQmPn4expNfgovLvvIpjUI1wEs+ c0rg== X-Gm-Message-State: AO0yUKW5iVEgTWXadkRf0lERKlvpNLxJ9Q3tprOp2FepUWqoXzOWDfVj d4Xwhs+qq5YkrAkUnHBDTPiTy0K4R5vrD4vG X-Google-Smtp-Source: AK7set+Ixyd0d2YPg0N3S5nLh0C0VhQV9pdVo3UOUlR3jAgmAyiX+tYsvdrAK7o8Kz0J/7wkK56Ngw== X-Received: by 2002:a05:600c:4da2:b0:3e2:19b0:887d with SMTP id v34-20020a05600c4da200b003e219b0887dmr19902962wmp.25.1677506470906; Mon, 27 Feb 2023 06:01:10 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 04/25] target/arm: move translate modules to tcg/ Date: Mon, 27 Feb 2023 14:00:41 +0000 Message-Id: <20230227140102.3712344-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230227140102.3712344-1-peter.maydell@linaro.org> References: <20230227140102.3712344-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1677506651482100001 From: Fabiano Rosas Introduce the target/arm/tcg directory. Its purpose is to hold the TCG code that is selected by CONFIG_TCG. Signed-off-by: Claudio Fontana Signed-off-by: Fabiano Rosas Reviewed-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Peter Maydell --- MAINTAINERS | 1 + target/arm/{ =3D> tcg}/translate-a64.h | 0 target/arm/{ =3D> tcg}/translate.h | 0 target/arm/{ =3D> tcg}/a32-uncond.decode | 0 target/arm/{ =3D> tcg}/a32.decode | 0 target/arm/{ =3D> tcg}/m-nocp.decode | 0 target/arm/{ =3D> tcg}/mve.decode | 0 target/arm/{ =3D> tcg}/neon-dp.decode | 0 target/arm/{ =3D> tcg}/neon-ls.decode | 0 target/arm/{ =3D> tcg}/neon-shared.decode | 0 target/arm/{ =3D> tcg}/sme-fa64.decode | 0 target/arm/{ =3D> tcg}/sme.decode | 0 target/arm/{ =3D> tcg}/sve.decode | 0 target/arm/{ =3D> tcg}/t16.decode | 0 target/arm/{ =3D> tcg}/t32.decode | 0 target/arm/{ =3D> tcg}/vfp-uncond.decode | 0 target/arm/{ =3D> tcg}/vfp.decode | 0 target/arm/{ =3D> tcg}/translate-a64.c | 0 target/arm/{ =3D> tcg}/translate-m-nocp.c | 0 target/arm/{ =3D> tcg}/translate-mve.c | 0 target/arm/{ =3D> tcg}/translate-neon.c | 0 target/arm/{ =3D> tcg}/translate-sme.c | 0 target/arm/{ =3D> tcg}/translate-sve.c | 0 target/arm/{ =3D> tcg}/translate-vfp.c | 0 target/arm/{ =3D> tcg}/translate.c | 0 target/arm/meson.build | 30 +++--------------- target/arm/{ =3D> tcg}/meson.build | 41 +------------------------ 27 files changed, 6 insertions(+), 66 deletions(-) rename target/arm/{ =3D> tcg}/translate-a64.h (100%) rename target/arm/{ =3D> tcg}/translate.h (100%) rename target/arm/{ =3D> tcg}/a32-uncond.decode (100%) rename target/arm/{ =3D> tcg}/a32.decode (100%) rename target/arm/{ =3D> tcg}/m-nocp.decode (100%) rename target/arm/{ =3D> tcg}/mve.decode (100%) rename target/arm/{ =3D> tcg}/neon-dp.decode (100%) rename target/arm/{ =3D> tcg}/neon-ls.decode (100%) rename target/arm/{ =3D> tcg}/neon-shared.decode (100%) rename target/arm/{ =3D> tcg}/sme-fa64.decode (100%) rename target/arm/{ =3D> tcg}/sme.decode (100%) rename target/arm/{ =3D> tcg}/sve.decode (100%) rename target/arm/{ =3D> tcg}/t16.decode (100%) rename target/arm/{ =3D> tcg}/t32.decode (100%) rename target/arm/{ =3D> tcg}/vfp-uncond.decode (100%) rename target/arm/{ =3D> tcg}/vfp.decode (100%) rename target/arm/{ =3D> tcg}/translate-a64.c (100%) rename target/arm/{ =3D> tcg}/translate-m-nocp.c (100%) rename target/arm/{ =3D> tcg}/translate-mve.c (100%) rename target/arm/{ =3D> tcg}/translate-neon.c (100%) rename target/arm/{ =3D> tcg}/translate-sme.c (100%) rename target/arm/{ =3D> tcg}/translate-sve.c (100%) rename target/arm/{ =3D> tcg}/translate-vfp.c (100%) rename target/arm/{ =3D> tcg}/translate.c (100%) copy target/arm/{ =3D> tcg}/meson.build (64%) diff --git a/MAINTAINERS b/MAINTAINERS index 5c1ee411397..c6e6549f069 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -161,6 +161,7 @@ M: Peter Maydell L: qemu-arm@nongnu.org S: Maintained F: target/arm/ +F: target/arm/tcg/ F: tests/tcg/arm/ F: tests/tcg/aarch64/ F: tests/qtest/arm-cpu-features.c diff --git a/target/arm/translate-a64.h b/target/arm/tcg/translate-a64.h similarity index 100% rename from target/arm/translate-a64.h rename to target/arm/tcg/translate-a64.h diff --git a/target/arm/translate.h b/target/arm/tcg/translate.h similarity index 100% rename from target/arm/translate.h rename to target/arm/tcg/translate.h diff --git a/target/arm/a32-uncond.decode b/target/arm/tcg/a32-uncond.decode similarity index 100% rename from target/arm/a32-uncond.decode rename to target/arm/tcg/a32-uncond.decode diff --git a/target/arm/a32.decode b/target/arm/tcg/a32.decode similarity index 100% rename from target/arm/a32.decode rename to target/arm/tcg/a32.decode diff --git a/target/arm/m-nocp.decode b/target/arm/tcg/m-nocp.decode similarity index 100% rename from target/arm/m-nocp.decode rename to target/arm/tcg/m-nocp.decode diff --git a/target/arm/mve.decode b/target/arm/tcg/mve.decode similarity index 100% rename from target/arm/mve.decode rename to target/arm/tcg/mve.decode diff --git a/target/arm/neon-dp.decode b/target/arm/tcg/neon-dp.decode similarity index 100% rename from target/arm/neon-dp.decode rename to target/arm/tcg/neon-dp.decode diff --git a/target/arm/neon-ls.decode b/target/arm/tcg/neon-ls.decode similarity index 100% rename from target/arm/neon-ls.decode rename to target/arm/tcg/neon-ls.decode diff --git a/target/arm/neon-shared.decode b/target/arm/tcg/neon-shared.dec= ode similarity index 100% rename from target/arm/neon-shared.decode rename to target/arm/tcg/neon-shared.decode diff --git a/target/arm/sme-fa64.decode b/target/arm/tcg/sme-fa64.decode similarity index 100% rename from target/arm/sme-fa64.decode rename to target/arm/tcg/sme-fa64.decode diff --git a/target/arm/sme.decode b/target/arm/tcg/sme.decode similarity index 100% rename from target/arm/sme.decode rename to target/arm/tcg/sme.decode diff --git a/target/arm/sve.decode b/target/arm/tcg/sve.decode similarity index 100% rename from target/arm/sve.decode rename to target/arm/tcg/sve.decode diff --git a/target/arm/t16.decode b/target/arm/tcg/t16.decode similarity index 100% rename from target/arm/t16.decode rename to target/arm/tcg/t16.decode diff --git a/target/arm/t32.decode b/target/arm/tcg/t32.decode similarity index 100% rename from target/arm/t32.decode rename to target/arm/tcg/t32.decode diff --git a/target/arm/vfp-uncond.decode b/target/arm/tcg/vfp-uncond.decode similarity index 100% rename from target/arm/vfp-uncond.decode rename to target/arm/tcg/vfp-uncond.decode diff --git a/target/arm/vfp.decode b/target/arm/tcg/vfp.decode similarity index 100% rename from target/arm/vfp.decode rename to target/arm/tcg/vfp.decode diff --git a/target/arm/translate-a64.c b/target/arm/tcg/translate-a64.c similarity index 100% rename from target/arm/translate-a64.c rename to target/arm/tcg/translate-a64.c diff --git a/target/arm/translate-m-nocp.c b/target/arm/tcg/translate-m-noc= p.c similarity index 100% rename from target/arm/translate-m-nocp.c rename to target/arm/tcg/translate-m-nocp.c diff --git a/target/arm/translate-mve.c b/target/arm/tcg/translate-mve.c similarity index 100% rename from target/arm/translate-mve.c rename to target/arm/tcg/translate-mve.c diff --git a/target/arm/translate-neon.c b/target/arm/tcg/translate-neon.c similarity index 100% rename from target/arm/translate-neon.c rename to target/arm/tcg/translate-neon.c diff --git a/target/arm/translate-sme.c b/target/arm/tcg/translate-sme.c similarity index 100% rename from target/arm/translate-sme.c rename to target/arm/tcg/translate-sme.c diff --git a/target/arm/translate-sve.c b/target/arm/tcg/translate-sve.c similarity index 100% rename from target/arm/translate-sve.c rename to target/arm/tcg/translate-sve.c diff --git a/target/arm/translate-vfp.c b/target/arm/tcg/translate-vfp.c similarity index 100% rename from target/arm/translate-vfp.c rename to target/arm/tcg/translate-vfp.c diff --git a/target/arm/translate.c b/target/arm/tcg/translate.c similarity index 100% rename from target/arm/translate.c rename to target/arm/tcg/translate.c diff --git a/target/arm/meson.build b/target/arm/meson.build index 87e911b27fb..b2904b676b0 100644 --- a/target/arm/meson.build +++ b/target/arm/meson.build @@ -1,22 +1,4 @@ -gen =3D [ - decodetree.process('sve.decode', extra_args: '--decode=3Ddisas_sve'), - decodetree.process('sme.decode', extra_args: '--decode=3Ddisas_sme'), - decodetree.process('sme-fa64.decode', extra_args: '--static-decode=3Ddis= as_sme_fa64'), - decodetree.process('neon-shared.decode', extra_args: '--decode=3Ddisas_n= eon_shared'), - decodetree.process('neon-dp.decode', extra_args: '--decode=3Ddisas_neon_= dp'), - decodetree.process('neon-ls.decode', extra_args: '--decode=3Ddisas_neon_= ls'), - decodetree.process('vfp.decode', extra_args: '--decode=3Ddisas_vfp'), - decodetree.process('vfp-uncond.decode', extra_args: '--decode=3Ddisas_vf= p_uncond'), - decodetree.process('m-nocp.decode', extra_args: '--decode=3Ddisas_m_nocp= '), - decodetree.process('mve.decode', extra_args: '--decode=3Ddisas_mve'), - decodetree.process('a32.decode', extra_args: '--static-decode=3Ddisas_a3= 2'), - decodetree.process('a32-uncond.decode', extra_args: '--static-decode=3Dd= isas_a32_uncond'), - decodetree.process('t32.decode', extra_args: '--static-decode=3Ddisas_t3= 2'), - decodetree.process('t16.decode', extra_args: ['-w', '16', '--static-deco= de=3Ddisas_t16']), -] - arm_ss =3D ss.source_set() -arm_ss.add(gen) arm_ss.add(files( 'cpu.c', 'crypto_helper.c', @@ -29,11 +11,6 @@ arm_ss.add(files( 'neon_helper.c', 'op_helper.c', 'tlb_helper.c', - 'translate.c', - 'translate-m-nocp.c', - 'translate-mve.c', - 'translate-neon.c', - 'translate-vfp.c', 'vec_helper.c', 'vfp_helper.c', 'cpu_tcg.c', @@ -50,9 +27,6 @@ arm_ss.add(when: 'TARGET_AARCH64', if_true: files( 'pauth_helper.c', 'sve_helper.c', 'sme_helper.c', - 'translate-a64.c', - 'translate-sve.c', - 'translate-sme.c', )) =20 arm_softmmu_ss =3D ss.source_set() @@ -67,5 +41,9 @@ arm_softmmu_ss.add(files( =20 subdir('hvf') =20 +if 'CONFIG_TCG' in config_all + subdir('tcg') +endif + target_arch +=3D {'arm': arm_ss} target_softmmu_arch +=3D {'arm': arm_softmmu_ss} diff --git a/target/arm/meson.build b/target/arm/tcg/meson.build similarity index 64% copy from target/arm/meson.build copy to target/arm/tcg/meson.build index 87e911b27fb..044561bd4de 100644 --- a/target/arm/meson.build +++ b/target/arm/tcg/meson.build @@ -15,57 +15,18 @@ gen =3D [ decodetree.process('t16.decode', extra_args: ['-w', '16', '--static-deco= de=3Ddisas_t16']), ] =20 -arm_ss =3D ss.source_set() arm_ss.add(gen) + arm_ss.add(files( - 'cpu.c', - 'crypto_helper.c', - 'debug_helper.c', - 'gdbstub.c', - 'helper.c', - 'iwmmxt_helper.c', - 'm_helper.c', - 'mve_helper.c', - 'neon_helper.c', - 'op_helper.c', - 'tlb_helper.c', 'translate.c', 'translate-m-nocp.c', 'translate-mve.c', 'translate-neon.c', 'translate-vfp.c', - 'vec_helper.c', - 'vfp_helper.c', - 'cpu_tcg.c', )) -arm_ss.add(zlib) - -arm_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c', 'kvm64.c'), if_fals= e: files('kvm-stub.c')) =20 arm_ss.add(when: 'TARGET_AARCH64', if_true: files( - 'cpu64.c', - 'gdbstub64.c', - 'helper-a64.c', - 'mte_helper.c', - 'pauth_helper.c', - 'sve_helper.c', - 'sme_helper.c', 'translate-a64.c', 'translate-sve.c', 'translate-sme.c', )) - -arm_softmmu_ss =3D ss.source_set() -arm_softmmu_ss.add(files( - 'arch_dump.c', - 'arm-powerctl.c', - 'machine.c', - 'monitor.c', - 'psci.c', - 'ptw.c', -)) - -subdir('hvf') - -target_arch +=3D {'arm': arm_ss} -target_softmmu_arch +=3D {'arm': arm_softmmu_ss} --=20 2.34.1 From nobody Tue May 14 10:40:27 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1677506997643100001 From: Claudio Fontana Signed-off-by: Claudio Fontana Signed-off-by: Fabiano Rosas Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Peter Maydell --- target/arm/{ =3D> tcg}/vec_internal.h | 0 target/arm/tcg-stubs.c | 23 +++++++++++++++++++++++ target/arm/{ =3D> tcg}/crypto_helper.c | 0 target/arm/{ =3D> tcg}/helper-a64.c | 0 target/arm/{ =3D> tcg}/iwmmxt_helper.c | 0 target/arm/{ =3D> tcg}/m_helper.c | 0 target/arm/{ =3D> tcg}/mte_helper.c | 0 target/arm/{ =3D> tcg}/mve_helper.c | 0 target/arm/{ =3D> tcg}/neon_helper.c | 0 target/arm/{ =3D> tcg}/op_helper.c | 0 target/arm/{ =3D> tcg}/pauth_helper.c | 0 target/arm/{ =3D> tcg}/sme_helper.c | 0 target/arm/{ =3D> tcg}/sve_helper.c | 0 target/arm/{ =3D> tcg}/tlb_helper.c | 0 target/arm/{ =3D> tcg}/vec_helper.c | 0 target/arm/meson.build | 15 ++------------- target/arm/tcg/meson.build | 13 +++++++++++++ 17 files changed, 38 insertions(+), 13 deletions(-) rename target/arm/{ =3D> tcg}/vec_internal.h (100%) create mode 100644 target/arm/tcg-stubs.c rename target/arm/{ =3D> tcg}/crypto_helper.c (100%) rename target/arm/{ =3D> tcg}/helper-a64.c (100%) rename target/arm/{ =3D> tcg}/iwmmxt_helper.c (100%) rename target/arm/{ =3D> tcg}/m_helper.c (100%) rename target/arm/{ =3D> tcg}/mte_helper.c (100%) rename target/arm/{ =3D> tcg}/mve_helper.c (100%) rename target/arm/{ =3D> tcg}/neon_helper.c (100%) rename target/arm/{ =3D> tcg}/op_helper.c (100%) rename target/arm/{ =3D> tcg}/pauth_helper.c (100%) rename target/arm/{ =3D> tcg}/sme_helper.c (100%) rename target/arm/{ =3D> tcg}/sve_helper.c (100%) rename target/arm/{ =3D> tcg}/tlb_helper.c (100%) rename target/arm/{ =3D> tcg}/vec_helper.c (100%) diff --git a/target/arm/vec_internal.h b/target/arm/tcg/vec_internal.h similarity index 100% rename from target/arm/vec_internal.h rename to target/arm/tcg/vec_internal.h diff --git a/target/arm/tcg-stubs.c b/target/arm/tcg-stubs.c new file mode 100644 index 00000000000..1a7ddb36647 --- /dev/null +++ b/target/arm/tcg-stubs.c @@ -0,0 +1,23 @@ +/* + * QEMU ARM stubs for some TCG helper functions + * + * Copyright 2021 SUSE LLC + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + */ + +#include "qemu/osdep.h" +#include "cpu.h" +#include "internals.h" + +void write_v7m_exception(CPUARMState *env, uint32_t new_exc) +{ + g_assert_not_reached(); +} + +void raise_exception_ra(CPUARMState *env, uint32_t excp, uint32_t syndrome, + uint32_t target_el, uintptr_t ra) +{ + g_assert_not_reached(); +} diff --git a/target/arm/crypto_helper.c b/target/arm/tcg/crypto_helper.c similarity index 100% rename from target/arm/crypto_helper.c rename to target/arm/tcg/crypto_helper.c diff --git a/target/arm/helper-a64.c b/target/arm/tcg/helper-a64.c similarity index 100% rename from target/arm/helper-a64.c rename to target/arm/tcg/helper-a64.c diff --git a/target/arm/iwmmxt_helper.c b/target/arm/tcg/iwmmxt_helper.c similarity index 100% rename from target/arm/iwmmxt_helper.c rename to target/arm/tcg/iwmmxt_helper.c diff --git a/target/arm/m_helper.c b/target/arm/tcg/m_helper.c similarity index 100% rename from target/arm/m_helper.c rename to target/arm/tcg/m_helper.c diff --git a/target/arm/mte_helper.c b/target/arm/tcg/mte_helper.c similarity index 100% rename from target/arm/mte_helper.c rename to target/arm/tcg/mte_helper.c diff --git a/target/arm/mve_helper.c b/target/arm/tcg/mve_helper.c similarity index 100% rename from target/arm/mve_helper.c rename to target/arm/tcg/mve_helper.c diff --git a/target/arm/neon_helper.c b/target/arm/tcg/neon_helper.c similarity index 100% rename from target/arm/neon_helper.c rename to target/arm/tcg/neon_helper.c diff --git a/target/arm/op_helper.c b/target/arm/tcg/op_helper.c similarity index 100% rename from target/arm/op_helper.c rename to target/arm/tcg/op_helper.c diff --git a/target/arm/pauth_helper.c b/target/arm/tcg/pauth_helper.c similarity index 100% rename from target/arm/pauth_helper.c rename to target/arm/tcg/pauth_helper.c diff --git a/target/arm/sme_helper.c b/target/arm/tcg/sme_helper.c similarity index 100% rename from target/arm/sme_helper.c rename to target/arm/tcg/sme_helper.c diff --git a/target/arm/sve_helper.c b/target/arm/tcg/sve_helper.c similarity index 100% rename from target/arm/sve_helper.c rename to target/arm/tcg/sve_helper.c diff --git a/target/arm/tlb_helper.c b/target/arm/tcg/tlb_helper.c similarity index 100% rename from target/arm/tlb_helper.c rename to target/arm/tcg/tlb_helper.c diff --git a/target/arm/vec_helper.c b/target/arm/tcg/vec_helper.c similarity index 100% rename from target/arm/vec_helper.c rename to target/arm/tcg/vec_helper.c diff --git a/target/arm/meson.build b/target/arm/meson.build index b2904b676b0..3e2f4030056 100644 --- a/target/arm/meson.build +++ b/target/arm/meson.build @@ -1,17 +1,9 @@ arm_ss =3D ss.source_set() arm_ss.add(files( 'cpu.c', - 'crypto_helper.c', 'debug_helper.c', 'gdbstub.c', 'helper.c', - 'iwmmxt_helper.c', - 'm_helper.c', - 'mve_helper.c', - 'neon_helper.c', - 'op_helper.c', - 'tlb_helper.c', - 'vec_helper.c', 'vfp_helper.c', 'cpu_tcg.c', )) @@ -22,11 +14,6 @@ arm_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c', '= kvm64.c'), if_false: fil arm_ss.add(when: 'TARGET_AARCH64', if_true: files( 'cpu64.c', 'gdbstub64.c', - 'helper-a64.c', - 'mte_helper.c', - 'pauth_helper.c', - 'sve_helper.c', - 'sme_helper.c', )) =20 arm_softmmu_ss =3D ss.source_set() @@ -43,6 +30,8 @@ subdir('hvf') =20 if 'CONFIG_TCG' in config_all subdir('tcg') +else + arm_ss.add(files('tcg-stubs.c')) endif =20 target_arch +=3D {'arm': arm_ss} diff --git a/target/arm/tcg/meson.build b/target/arm/tcg/meson.build index 044561bd4de..1f27ba1272e 100644 --- a/target/arm/tcg/meson.build +++ b/target/arm/tcg/meson.build @@ -23,10 +23,23 @@ arm_ss.add(files( 'translate-mve.c', 'translate-neon.c', 'translate-vfp.c', + 'crypto_helper.c', + 'iwmmxt_helper.c', + 'm_helper.c', + 'mve_helper.c', + 'neon_helper.c', + 'op_helper.c', + 'tlb_helper.c', + 'vec_helper.c', )) =20 arm_ss.add(when: 'TARGET_AARCH64', if_true: files( 'translate-a64.c', 'translate-sve.c', 'translate-sme.c', + 'helper-a64.c', + 'mte_helper.c', + 'pauth_helper.c', + 'sme_helper.c', + 'sve_helper.c', )) --=20 2.34.1 From nobody Tue May 14 10:40:27 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1677507187065100011 From: Claudio Fontana Signed-off-by: Claudio Fontana Signed-off-by: Fabiano Rosas Reviewed-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e Tested-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Peter Maydell --- target/arm/{ =3D> tcg}/psci.c | 0 target/arm/meson.build | 1 - target/arm/tcg/meson.build | 4 ++++ 3 files changed, 4 insertions(+), 1 deletion(-) rename target/arm/{ =3D> tcg}/psci.c (100%) diff --git a/target/arm/psci.c b/target/arm/tcg/psci.c similarity index 100% rename from target/arm/psci.c rename to target/arm/tcg/psci.c diff --git a/target/arm/meson.build b/target/arm/meson.build index 3e2f4030056..a5191b57e1c 100644 --- a/target/arm/meson.build +++ b/target/arm/meson.build @@ -22,7 +22,6 @@ arm_softmmu_ss.add(files( 'arm-powerctl.c', 'machine.c', 'monitor.c', - 'psci.c', 'ptw.c', )) =20 diff --git a/target/arm/tcg/meson.build b/target/arm/tcg/meson.build index 1f27ba1272e..fa8a9eab933 100644 --- a/target/arm/tcg/meson.build +++ b/target/arm/tcg/meson.build @@ -43,3 +43,7 @@ arm_ss.add(when: 'TARGET_AARCH64', if_true: files( 'sme_helper.c', 'sve_helper.c', )) + +arm_softmmu_ss.add(files( + 'psci.c', +)) --=20 2.34.1 From nobody Tue May 14 10:40:27 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id s9-20020a5d4249000000b002c5598c14acsm7158514wrr.6.2023.02.27.06.01.13 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Feb 2023 06:01:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=qA/3Z94irQbWBM1pbSkHlsvHgpn7DcaD1jcVgPus5vI=; b=UOK/XBgkCuLakUDjlRyQFBTIDa84LBgmj3ZZfUnOfd/YcNitORKfoxCMZ9BALbabqb oNaFR976pL2BdQ7w815XICuBT3ONxxeZHGcUuCEG/ozGt0MJVjj+tNNi0zpox+k/yQGe cTMX+70SieY3HizgqxorLIR0DNuF61SXciBOxj3VuhVD8A+bWdl3f27f+zhRqJdAfT0g Z5mNwZ72VWqPMu6r+7Y6aby24DXhCXFo91C/AkbPmvaUaJSnpBWsclfLvEIvbnLDIqgm MqY8vEa490eUGDFlbH7L3iKvqLw6BfmYpW04DFLfAhQSe7mB/c8XQKE9Zz+VmIrsd19Q EINQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=qA/3Z94irQbWBM1pbSkHlsvHgpn7DcaD1jcVgPus5vI=; b=C4iCiEXGmf/SmTmvqVvMBlGEaeLQTAJq8N0TmOV85zYO0msdfvqB0a5r+LK/ly9Gk/ 92yj6YCa892+AUvcn87TSNL74dCitk7Y+1Ul5QPM6hp2LnWgiCRaRMuVlxQjt8iKBln3 f2ZlAz+JwRSXpZrIr/1kdT4Pv4YZ4ZK0y4GjxqzsuA4m1mkFOt7z8Ak/ejxFK5pa2wex 4zU3S5xP7Wejbr6u3aogVFiPoC5EMPTiPSDPMoHgCGZxvv3paa5kCFHgFRs+yDC15oHe TZeWyhBuWolpZbzRNe8kA1pcplgHXYc4YQD08dmnTQacn6EfWqpHtL7G9ERhpC22DJJZ DrJw== X-Gm-Message-State: AO0yUKWm+dXGZEpq4f4mIqBhR0kGdXpl4wEh1BRDbXeLJAa7ytzefwuq uXn+0ml5wbNoEZTmSylRLucDH4tAsM2TpZ/a X-Google-Smtp-Source: AK7set/PzKnmwFgbniuoBPUmNKCvCddV8QZXBCxwo5RUWr8+oocGUACuwsZ6xyPgCa64pC95+N2oTg== X-Received: by 2002:a05:600c:3b8b:b0:3ea:ea6b:f9ad with SMTP id n11-20020a05600c3b8b00b003eaea6bf9admr11959801wms.31.1677506474680; Mon, 27 Feb 2023 06:01:14 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 07/25] target/arm: Wrap arm_rebuild_hflags calls with tcg_enabled Date: Mon, 27 Feb 2023 14:00:44 +0000 Message-Id: <20230227140102.3712344-8-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230227140102.3712344-1-peter.maydell@linaro.org> References: <20230227140102.3712344-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1677506631941100003 From: Fabiano Rosas This is in preparation to moving the hflags code into its own file under the tcg/ directory. Signed-off-by: Fabiano Rosas Reviewed-by: Richard Henderson Tested-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Peter Maydell --- hw/arm/boot.c | 6 +++++- hw/intc/armv7m_nvic.c | 20 +++++++++++++------- target/arm/arm-powerctl.c | 7 +++++-- target/arm/cpu.c | 3 ++- target/arm/helper.c | 18 +++++++++++++----- target/arm/machine.c | 5 ++++- 6 files changed, 42 insertions(+), 17 deletions(-) diff --git a/hw/arm/boot.c b/hw/arm/boot.c index 3d7d11f782f..1e021c4a340 100644 --- a/hw/arm/boot.c +++ b/hw/arm/boot.c @@ -15,6 +15,7 @@ #include "hw/arm/boot.h" #include "hw/arm/linux-boot-if.h" #include "sysemu/kvm.h" +#include "sysemu/tcg.h" #include "sysemu/sysemu.h" #include "sysemu/numa.h" #include "hw/boards.h" @@ -827,7 +828,10 @@ static void do_cpu_reset(void *opaque) info->secondary_cpu_reset_hook(cpu, info); } } - arm_rebuild_hflags(env); + + if (tcg_enabled()) { + arm_rebuild_hflags(env); + } } } =20 diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index e54553283f4..8e289051a40 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -18,6 +18,7 @@ #include "hw/intc/armv7m_nvic.h" #include "hw/irq.h" #include "hw/qdev-properties.h" +#include "sysemu/tcg.h" #include "sysemu/runstate.h" #include "target/arm/cpu.h" #include "exec/exec-all.h" @@ -2454,8 +2455,10 @@ static MemTxResult nvic_sysreg_write(void *opaque, h= waddr addr, /* This is UNPREDICTABLE; treat as RAZ/WI */ =20 exit_ok: - /* Ensure any changes made are reflected in the cached hflags. */ - arm_rebuild_hflags(&s->cpu->env); + if (tcg_enabled()) { + /* Ensure any changes made are reflected in the cached hflags. */ + arm_rebuild_hflags(&s->cpu->env); + } return MEMTX_OK; } =20 @@ -2636,11 +2639,14 @@ static void armv7m_nvic_reset(DeviceState *dev) } } =20 - /* - * We updated state that affects the CPU's MMUidx and thus its hflags; - * and we can't guarantee that we run before the CPU reset function. - */ - arm_rebuild_hflags(&s->cpu->env); + if (tcg_enabled()) { + /* + * We updated state that affects the CPU's MMUidx and thus its + * hflags; and we can't guarantee that we run before the CPU + * reset function. + */ + arm_rebuild_hflags(&s->cpu->env); + } } =20 static void nvic_systick_trigger(void *opaque, int n, int level) diff --git a/target/arm/arm-powerctl.c b/target/arm/arm-powerctl.c index b75f813b403..326a03153df 100644 --- a/target/arm/arm-powerctl.c +++ b/target/arm/arm-powerctl.c @@ -15,6 +15,7 @@ #include "arm-powerctl.h" #include "qemu/log.h" #include "qemu/main-loop.h" +#include "sysemu/tcg.h" =20 #ifndef DEBUG_ARM_POWERCTL #define DEBUG_ARM_POWERCTL 0 @@ -127,8 +128,10 @@ static void arm_set_cpu_on_async_work(CPUState *target= _cpu_state, target_cpu->env.regs[0] =3D info->context_id; } =20 - /* CP15 update requires rebuilding hflags */ - arm_rebuild_hflags(&target_cpu->env); + if (tcg_enabled()) { + /* CP15 update requires rebuilding hflags */ + arm_rebuild_hflags(&target_cpu->env); + } =20 /* Start the new CPU at the requested address */ cpu_set_pc(target_cpu_state, info->entry); diff --git a/target/arm/cpu.c b/target/arm/cpu.c index da416f7b1cb..0b333a749f6 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -542,8 +542,9 @@ static void arm_cpu_reset_hold(Object *obj) if (tcg_enabled()) { hw_breakpoint_update_all(cpu); hw_watchpoint_update_all(cpu); + + arm_rebuild_hflags(env); } - arm_rebuild_hflags(env); } =20 #if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) diff --git a/target/arm/helper.c b/target/arm/helper.c index 07d41003654..af72e6d16c0 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -5173,7 +5173,7 @@ static void sctlr_write(CPUARMState *env, const ARMCP= RegInfo *ri, /* This may enable/disable the MMU, so do a TLB flush. */ tlb_flush(CPU(cpu)); =20 - if (ri->type & ARM_CP_SUPPRESS_TB_END) { + if (tcg_enabled() && ri->type & ARM_CP_SUPPRESS_TB_END) { /* * Normally we would always end the TB on an SCTLR write; see the * comment in ARMCPRegInfo sctlr initialization below for why Xsca= le @@ -6841,7 +6841,9 @@ void aarch64_set_svcr(CPUARMState *env, uint64_t new,= uint64_t mask) memset(env->zarray, 0, sizeof(env->zarray)); } =20 - arm_rebuild_hflags(env); + if (tcg_enabled()) { + arm_rebuild_hflags(env); + } } =20 static void svcr_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -9886,7 +9888,7 @@ void cpsr_write(CPUARMState *env, uint32_t val, uint3= 2_t mask, } mask &=3D ~CACHED_CPSR_BITS; env->uncached_cpsr =3D (env->uncached_cpsr & ~mask) | (val & mask); - if (rebuild_hflags) { + if (tcg_enabled() && rebuild_hflags) { arm_rebuild_hflags(env); } } @@ -10445,7 +10447,10 @@ static void take_aarch32_exception(CPUARMState *en= v, int new_mode, env->regs[14] =3D env->regs[15] + offset; } env->regs[15] =3D newpc; - arm_rebuild_hflags(env); + + if (tcg_enabled()) { + arm_rebuild_hflags(env); + } } =20 static void arm_cpu_do_interrupt_aarch32_hyp(CPUState *cs) @@ -11001,7 +11006,10 @@ static void arm_cpu_do_interrupt_aarch64(CPUState = *cs) pstate_write(env, PSTATE_DAIF | new_mode); env->aarch64 =3D true; aarch64_restore_sp(env, new_el); - helper_rebuild_hflags_a64(env, new_el); + + if (tcg_enabled()) { + helper_rebuild_hflags_a64(env, new_el); + } =20 env->pc =3D addr; =20 diff --git a/target/arm/machine.c b/target/arm/machine.c index fd6323f6d8a..fc4a4a40644 100644 --- a/target/arm/machine.c +++ b/target/arm/machine.c @@ -871,7 +871,10 @@ static int cpu_post_load(void *opaque, int version_id) if (!kvm_enabled()) { pmu_op_finish(&cpu->env); } - arm_rebuild_hflags(&cpu->env); + + if (tcg_enabled()) { + arm_rebuild_hflags(&cpu->env); + } =20 return 0; } --=20 2.34.1 From nobody Tue May 14 10:40:27 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id s9-20020a5d4249000000b002c5598c14acsm7158514wrr.6.2023.02.27.06.01.14 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Feb 2023 06:01:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=Ku7kL3lIZ9ja7LCy0WnkJW4LdaPapwCQHS2Pc0hPYdE=; b=ncE+0WpMf1IGtvs+EJEwUAsZ5PX9TbxBeXbdDqaBgN//V7V7y77boUnjYalstWsUCw TDiaYeftx+mKypTA2hFBk3zIk/54iKBFSPjh/ipHzak0ByUN2gdZMo9+mVyz4rygi4zx T5BD2Q3g2Lx+hB3uDv9UqqcX86yZhaV+803/UQoS+pJhrCkPYxdWlFIOu4xtHALVeBoF EZVZ/HfUai2CkHAuUipotXDoe9x2A1hjDHDCsnhjvYvKU7auE87tndpnHpOSp/nQBq5w j1b7tY5iyiQsennlPq3Cza8vQMZtZXCg9tErGZDl4DQfRfQfqTid2CADOXlG+xPs5Wso 5F5Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Ku7kL3lIZ9ja7LCy0WnkJW4LdaPapwCQHS2Pc0hPYdE=; b=M00m4sQ+oBmcOsg/Ho9yypvUcomqPINKxGtg/gyD03RHARG14TvBSdtADs6bHJH8yy 3ymxQFyNN/Q3iHCzcm6SIN5iqrIziRoqaSAFcqH2006c22nTPMST5e0HRvApT/78QS/g OrrlfyiJpuHsMrEowjKz3mP4jt/V1/u5G+ihfrvL/2jvmd3OQt1RdTH2S3QeqvV6VRff +V4CqWh5WZUdujyiHky/VVYdDGj8HXr8ZZry9n50VcR+jHNRT77nNVqNrnAxO7gwoiSr Ub61dud96LAnrc7QioNTgV0pgN73kTt/aoyf4RZcs8N7ulEvIhBloLvLy6NP4713UA9z igcA== X-Gm-Message-State: AO0yUKVa1s+tv7kXg6IUjZjRpaqod5fzAcI3H2Zn+mZa57UbQ7IMgOLU zmbxD8XDJbX/zEhPsJYNmeB2MYJAmLhySHfu X-Google-Smtp-Source: AK7set/koj4Pj0Whme0pdYdKez5GZoS1wkZtz26Iq15SaHjpYC5fKj0qaYw7hch8Nbp+RYcS/bOsLg== X-Received: by 2002:adf:f247:0:b0:2c7:1e00:d514 with SMTP id b7-20020adff247000000b002c71e00d514mr11937768wrp.38.1677506475968; Mon, 27 Feb 2023 06:01:15 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 08/25] target/arm: Move hflags code into the tcg directory Date: Mon, 27 Feb 2023 14:00:45 +0000 Message-Id: <20230227140102.3712344-9-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230227140102.3712344-1-peter.maydell@linaro.org> References: <20230227140102.3712344-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1677506701435100001 From: Fabiano Rosas The hflags are used only for TCG code, so introduce a new file hflags.c to keep that code. Signed-off-by: Fabiano Rosas Reviewed-by: Richard Henderson Tested-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Peter Maydell --- target/arm/internals.h | 2 + target/arm/helper.c | 393 +----------------------------------- target/arm/tcg-stubs.c | 4 + target/arm/tcg/hflags.c | 403 +++++++++++++++++++++++++++++++++++++ target/arm/tcg/meson.build | 1 + 5 files changed, 411 insertions(+), 392 deletions(-) create mode 100644 target/arm/tcg/hflags.c diff --git a/target/arm/internals.h b/target/arm/internals.h index 759b70c646f..ed48f8c9a69 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1073,6 +1073,7 @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, = uint64_t va, =20 int aa64_va_parameter_tbi(uint64_t tcr, ARMMMUIdx mmu_idx); int aa64_va_parameter_tbid(uint64_t tcr, ARMMMUIdx mmu_idx); +int aa64_va_parameter_tcma(uint64_t tcr, ARMMMUIdx mmu_idx); =20 /* Determine if allocation tags are available. */ static inline bool allocation_tag_access_enabled(CPUARMState *env, int el, @@ -1383,4 +1384,5 @@ static inline bool arm_fgt_active(CPUARMState *env, i= nt el) (!arm_feature(env, ARM_FEATURE_EL3) || (env->cp15.scr_el3 & SCR_FG= TEN)); } =20 +void assert_hflags_rebuild_correctly(CPUARMState *env); #endif diff --git a/target/arm/helper.c b/target/arm/helper.c index af72e6d16c0..14af7ba0958 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6669,32 +6669,6 @@ int sme_exception_el(CPUARMState *env, int el) return 0; } =20 -/* This corresponds to the ARM pseudocode function IsFullA64Enabled(). */ -static bool sme_fa64(CPUARMState *env, int el) -{ - if (!cpu_isar_feature(aa64_sme_fa64, env_archcpu(env))) { - return false; - } - - if (el <=3D 1 && !el_is_in_host(env, el)) { - if (!FIELD_EX64(env->vfp.smcr_el[1], SMCR, FA64)) { - return false; - } - } - if (el <=3D 2 && arm_is_el2_enabled(env)) { - if (!FIELD_EX64(env->vfp.smcr_el[2], SMCR, FA64)) { - return false; - } - } - if (arm_feature(env, ARM_FEATURE_EL3)) { - if (!FIELD_EX64(env->vfp.smcr_el[3], SMCR, FA64)) { - return false; - } - } - - return true; -} - /* * Given that SVE is enabled, return the vector length for EL. */ @@ -11150,7 +11124,7 @@ int aa64_va_parameter_tbid(uint64_t tcr, ARMMMUIdx = mmu_idx) } } =20 -static int aa64_va_parameter_tcma(uint64_t tcr, ARMMMUIdx mmu_idx) +int aa64_va_parameter_tcma(uint64_t tcr, ARMMMUIdx mmu_idx) { if (regime_has_2_ranges(mmu_idx)) { return extract64(tcr, 57, 2); @@ -11861,371 +11835,6 @@ ARMMMUIdx arm_mmu_idx(CPUARMState *env) return arm_mmu_idx_el(env, arm_current_el(env)); } =20 -static inline bool fgt_svc(CPUARMState *env, int el) -{ - /* - * Assuming fine-grained-traps are active, return true if we - * should be trapping on SVC instructions. Only AArch64 can - * trap on an SVC at EL1, but we don't need to special-case this - * because if this is AArch32 EL1 then arm_fgt_active() is false. - * We also know el is 0 or 1. - */ - return el =3D=3D 0 ? - FIELD_EX64(env->cp15.fgt_exec[FGTREG_HFGITR], HFGITR_EL2, SVC_EL0)= : - FIELD_EX64(env->cp15.fgt_exec[FGTREG_HFGITR], HFGITR_EL2, SVC_EL1); -} - -static CPUARMTBFlags rebuild_hflags_common(CPUARMState *env, int fp_el, - ARMMMUIdx mmu_idx, - CPUARMTBFlags flags) -{ - DP_TBFLAG_ANY(flags, FPEXC_EL, fp_el); - DP_TBFLAG_ANY(flags, MMUIDX, arm_to_core_mmu_idx(mmu_idx)); - - if (arm_singlestep_active(env)) { - DP_TBFLAG_ANY(flags, SS_ACTIVE, 1); - } - - return flags; -} - -static CPUARMTBFlags rebuild_hflags_common_32(CPUARMState *env, int fp_el, - ARMMMUIdx mmu_idx, - CPUARMTBFlags flags) -{ - bool sctlr_b =3D arm_sctlr_b(env); - - if (sctlr_b) { - DP_TBFLAG_A32(flags, SCTLR__B, 1); - } - if (arm_cpu_data_is_big_endian_a32(env, sctlr_b)) { - DP_TBFLAG_ANY(flags, BE_DATA, 1); - } - DP_TBFLAG_A32(flags, NS, !access_secure_reg(env)); - - return rebuild_hflags_common(env, fp_el, mmu_idx, flags); -} - -static CPUARMTBFlags rebuild_hflags_m32(CPUARMState *env, int fp_el, - ARMMMUIdx mmu_idx) -{ - CPUARMTBFlags flags =3D {}; - uint32_t ccr =3D env->v7m.ccr[env->v7m.secure]; - - /* Without HaveMainExt, CCR.UNALIGN_TRP is RES1. */ - if (ccr & R_V7M_CCR_UNALIGN_TRP_MASK) { - DP_TBFLAG_ANY(flags, ALIGN_MEM, 1); - } - - if (arm_v7m_is_handler_mode(env)) { - DP_TBFLAG_M32(flags, HANDLER, 1); - } - - /* - * v8M always applies stack limit checks unless CCR.STKOFHFNMIGN - * is suppressing them because the requested execution priority - * is less than 0. - */ - if (arm_feature(env, ARM_FEATURE_V8) && - !((mmu_idx & ARM_MMU_IDX_M_NEGPRI) && - (ccr & R_V7M_CCR_STKOFHFNMIGN_MASK))) { - DP_TBFLAG_M32(flags, STACKCHECK, 1); - } - - if (arm_feature(env, ARM_FEATURE_M_SECURITY) && env->v7m.secure) { - DP_TBFLAG_M32(flags, SECURE, 1); - } - - return rebuild_hflags_common_32(env, fp_el, mmu_idx, flags); -} - -static CPUARMTBFlags rebuild_hflags_a32(CPUARMState *env, int fp_el, - ARMMMUIdx mmu_idx) -{ - CPUARMTBFlags flags =3D {}; - int el =3D arm_current_el(env); - - if (arm_sctlr(env, el) & SCTLR_A) { - DP_TBFLAG_ANY(flags, ALIGN_MEM, 1); - } - - if (arm_el_is_aa64(env, 1)) { - DP_TBFLAG_A32(flags, VFPEN, 1); - } - - if (el < 2 && env->cp15.hstr_el2 && arm_is_el2_enabled(env) && - (arm_hcr_el2_eff(env) & (HCR_E2H | HCR_TGE)) !=3D (HCR_E2H | HCR_T= GE)) { - DP_TBFLAG_A32(flags, HSTR_ACTIVE, 1); - } - - if (arm_fgt_active(env, el)) { - DP_TBFLAG_ANY(flags, FGT_ACTIVE, 1); - if (fgt_svc(env, el)) { - DP_TBFLAG_ANY(flags, FGT_SVC, 1); - } - } - - if (env->uncached_cpsr & CPSR_IL) { - DP_TBFLAG_ANY(flags, PSTATE__IL, 1); - } - - /* - * The SME exception we are testing for is raised via - * AArch64.CheckFPAdvSIMDEnabled(), as called from - * AArch32.CheckAdvSIMDOrFPEnabled(). - */ - if (el =3D=3D 0 - && FIELD_EX64(env->svcr, SVCR, SM) - && (!arm_is_el2_enabled(env) - || (arm_el_is_aa64(env, 2) && !(env->cp15.hcr_el2 & HCR_TGE))) - && arm_el_is_aa64(env, 1) - && !sme_fa64(env, el)) { - DP_TBFLAG_A32(flags, SME_TRAP_NONSTREAMING, 1); - } - - return rebuild_hflags_common_32(env, fp_el, mmu_idx, flags); -} - -static CPUARMTBFlags rebuild_hflags_a64(CPUARMState *env, int el, int fp_e= l, - ARMMMUIdx mmu_idx) -{ - CPUARMTBFlags flags =3D {}; - ARMMMUIdx stage1 =3D stage_1_mmu_idx(mmu_idx); - uint64_t tcr =3D regime_tcr(env, mmu_idx); - uint64_t sctlr; - int tbii, tbid; - - DP_TBFLAG_ANY(flags, AARCH64_STATE, 1); - - /* Get control bits for tagged addresses. */ - tbid =3D aa64_va_parameter_tbi(tcr, mmu_idx); - tbii =3D tbid & ~aa64_va_parameter_tbid(tcr, mmu_idx); - - DP_TBFLAG_A64(flags, TBII, tbii); - DP_TBFLAG_A64(flags, TBID, tbid); - - if (cpu_isar_feature(aa64_sve, env_archcpu(env))) { - int sve_el =3D sve_exception_el(env, el); - - /* - * If either FP or SVE are disabled, translator does not need len. - * If SVE EL > FP EL, FP exception has precedence, and translator - * does not need SVE EL. Save potential re-translations by forcing - * the unneeded data to zero. - */ - if (fp_el !=3D 0) { - if (sve_el > fp_el) { - sve_el =3D 0; - } - } else if (sve_el =3D=3D 0) { - DP_TBFLAG_A64(flags, VL, sve_vqm1_for_el(env, el)); - } - DP_TBFLAG_A64(flags, SVEEXC_EL, sve_el); - } - if (cpu_isar_feature(aa64_sme, env_archcpu(env))) { - int sme_el =3D sme_exception_el(env, el); - bool sm =3D FIELD_EX64(env->svcr, SVCR, SM); - - DP_TBFLAG_A64(flags, SMEEXC_EL, sme_el); - if (sme_el =3D=3D 0) { - /* Similarly, do not compute SVL if SME is disabled. */ - int svl =3D sve_vqm1_for_el_sm(env, el, true); - DP_TBFLAG_A64(flags, SVL, svl); - if (sm) { - /* If SVE is disabled, we will not have set VL above. */ - DP_TBFLAG_A64(flags, VL, svl); - } - } - if (sm) { - DP_TBFLAG_A64(flags, PSTATE_SM, 1); - DP_TBFLAG_A64(flags, SME_TRAP_NONSTREAMING, !sme_fa64(env, el)= ); - } - DP_TBFLAG_A64(flags, PSTATE_ZA, FIELD_EX64(env->svcr, SVCR, ZA)); - } - - sctlr =3D regime_sctlr(env, stage1); - - if (sctlr & SCTLR_A) { - DP_TBFLAG_ANY(flags, ALIGN_MEM, 1); - } - - if (arm_cpu_data_is_big_endian_a64(el, sctlr)) { - DP_TBFLAG_ANY(flags, BE_DATA, 1); - } - - if (cpu_isar_feature(aa64_pauth, env_archcpu(env))) { - /* - * In order to save space in flags, we record only whether - * pauth is "inactive", meaning all insns are implemented as - * a nop, or "active" when some action must be performed. - * The decision of which action to take is left to a helper. - */ - if (sctlr & (SCTLR_EnIA | SCTLR_EnIB | SCTLR_EnDA | SCTLR_EnDB)) { - DP_TBFLAG_A64(flags, PAUTH_ACTIVE, 1); - } - } - - if (cpu_isar_feature(aa64_bti, env_archcpu(env))) { - /* Note that SCTLR_EL[23].BT =3D=3D SCTLR_BT1. */ - if (sctlr & (el =3D=3D 0 ? SCTLR_BT0 : SCTLR_BT1)) { - DP_TBFLAG_A64(flags, BT, 1); - } - } - - /* Compute the condition for using AccType_UNPRIV for LDTR et al. */ - if (!(env->pstate & PSTATE_UAO)) { - switch (mmu_idx) { - case ARMMMUIdx_E10_1: - case ARMMMUIdx_E10_1_PAN: - /* TODO: ARMv8.3-NV */ - DP_TBFLAG_A64(flags, UNPRIV, 1); - break; - case ARMMMUIdx_E20_2: - case ARMMMUIdx_E20_2_PAN: - /* - * Note that EL20_2 is gated by HCR_EL2.E2H =3D=3D 1, but EL20= _0 is - * gated by HCR_EL2. =3D=3D '11', and so is LDTR. - */ - if (env->cp15.hcr_el2 & HCR_TGE) { - DP_TBFLAG_A64(flags, UNPRIV, 1); - } - break; - default: - break; - } - } - - if (env->pstate & PSTATE_IL) { - DP_TBFLAG_ANY(flags, PSTATE__IL, 1); - } - - if (arm_fgt_active(env, el)) { - DP_TBFLAG_ANY(flags, FGT_ACTIVE, 1); - if (FIELD_EX64(env->cp15.fgt_exec[FGTREG_HFGITR], HFGITR_EL2, ERET= )) { - DP_TBFLAG_A64(flags, FGT_ERET, 1); - } - if (fgt_svc(env, el)) { - DP_TBFLAG_ANY(flags, FGT_SVC, 1); - } - } - - if (cpu_isar_feature(aa64_mte, env_archcpu(env))) { - /* - * Set MTE_ACTIVE if any access may be Checked, and leave clear - * if all accesses must be Unchecked: - * 1) If no TBI, then there are no tags in the address to check, - * 2) If Tag Check Override, then all accesses are Unchecked, - * 3) If Tag Check Fail =3D=3D 0, then Checked access have no effe= ct, - * 4) If no Allocation Tag Access, then all accesses are Unchecked. - */ - if (allocation_tag_access_enabled(env, el, sctlr)) { - DP_TBFLAG_A64(flags, ATA, 1); - if (tbid - && !(env->pstate & PSTATE_TCO) - && (sctlr & (el =3D=3D 0 ? SCTLR_TCF0 : SCTLR_TCF))) { - DP_TBFLAG_A64(flags, MTE_ACTIVE, 1); - } - } - /* And again for unprivileged accesses, if required. */ - if (EX_TBFLAG_A64(flags, UNPRIV) - && tbid - && !(env->pstate & PSTATE_TCO) - && (sctlr & SCTLR_TCF0) - && allocation_tag_access_enabled(env, 0, sctlr)) { - DP_TBFLAG_A64(flags, MTE0_ACTIVE, 1); - } - /* Cache TCMA as well as TBI. */ - DP_TBFLAG_A64(flags, TCMA, aa64_va_parameter_tcma(tcr, mmu_idx)); - } - - return rebuild_hflags_common(env, fp_el, mmu_idx, flags); -} - -static CPUARMTBFlags rebuild_hflags_internal(CPUARMState *env) -{ - int el =3D arm_current_el(env); - int fp_el =3D fp_exception_el(env, el); - ARMMMUIdx mmu_idx =3D arm_mmu_idx_el(env, el); - - if (is_a64(env)) { - return rebuild_hflags_a64(env, el, fp_el, mmu_idx); - } else if (arm_feature(env, ARM_FEATURE_M)) { - return rebuild_hflags_m32(env, fp_el, mmu_idx); - } else { - return rebuild_hflags_a32(env, fp_el, mmu_idx); - } -} - -void arm_rebuild_hflags(CPUARMState *env) -{ - env->hflags =3D rebuild_hflags_internal(env); -} - -/* - * If we have triggered a EL state change we can't rely on the - * translator having passed it to us, we need to recompute. - */ -void HELPER(rebuild_hflags_m32_newel)(CPUARMState *env) -{ - int el =3D arm_current_el(env); - int fp_el =3D fp_exception_el(env, el); - ARMMMUIdx mmu_idx =3D arm_mmu_idx_el(env, el); - - env->hflags =3D rebuild_hflags_m32(env, fp_el, mmu_idx); -} - -void HELPER(rebuild_hflags_m32)(CPUARMState *env, int el) -{ - int fp_el =3D fp_exception_el(env, el); - ARMMMUIdx mmu_idx =3D arm_mmu_idx_el(env, el); - - env->hflags =3D rebuild_hflags_m32(env, fp_el, mmu_idx); -} - -/* - * If we have triggered a EL state change we can't rely on the - * translator having passed it to us, we need to recompute. - */ -void HELPER(rebuild_hflags_a32_newel)(CPUARMState *env) -{ - int el =3D arm_current_el(env); - int fp_el =3D fp_exception_el(env, el); - ARMMMUIdx mmu_idx =3D arm_mmu_idx_el(env, el); - env->hflags =3D rebuild_hflags_a32(env, fp_el, mmu_idx); -} - -void HELPER(rebuild_hflags_a32)(CPUARMState *env, int el) -{ - int fp_el =3D fp_exception_el(env, el); - ARMMMUIdx mmu_idx =3D arm_mmu_idx_el(env, el); - - env->hflags =3D rebuild_hflags_a32(env, fp_el, mmu_idx); -} - -void HELPER(rebuild_hflags_a64)(CPUARMState *env, int el) -{ - int fp_el =3D fp_exception_el(env, el); - ARMMMUIdx mmu_idx =3D arm_mmu_idx_el(env, el); - - env->hflags =3D rebuild_hflags_a64(env, el, fp_el, mmu_idx); -} - -static inline void assert_hflags_rebuild_correctly(CPUARMState *env) -{ -#ifdef CONFIG_DEBUG_TCG - CPUARMTBFlags c =3D env->hflags; - CPUARMTBFlags r =3D rebuild_hflags_internal(env); - - if (unlikely(c.flags !=3D r.flags || c.flags2 !=3D r.flags2)) { - fprintf(stderr, "TCG hflags mismatch " - "(current:(0x%08x,0x" TARGET_FMT_lx ")" - " rebuilt:(0x%08x,0x" TARGET_FMT_lx ")\n", - c.flags, c.flags2, r.flags, r.flags2); - abort(); - } -#endif -} - static bool mve_no_pred(CPUARMState *env) { /* diff --git a/target/arm/tcg-stubs.c b/target/arm/tcg-stubs.c index 1a7ddb36647..152b172e243 100644 --- a/target/arm/tcg-stubs.c +++ b/target/arm/tcg-stubs.c @@ -21,3 +21,7 @@ void raise_exception_ra(CPUARMState *env, uint32_t excp, = uint32_t syndrome, { g_assert_not_reached(); } +/* Temporarily while cpu_get_tb_cpu_state() is still in common code */ +void assert_hflags_rebuild_correctly(CPUARMState *env) +{ +} diff --git a/target/arm/tcg/hflags.c b/target/arm/tcg/hflags.c new file mode 100644 index 00000000000..b2ccd77cffc --- /dev/null +++ b/target/arm/tcg/hflags.c @@ -0,0 +1,403 @@ +/* + * ARM hflags + * + * This code is licensed under the GNU GPL v2 or later. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ +#include "qemu/osdep.h" +#include "cpu.h" +#include "internals.h" +#include "exec/helper-proto.h" +#include "cpregs.h" + +static inline bool fgt_svc(CPUARMState *env, int el) +{ + /* + * Assuming fine-grained-traps are active, return true if we + * should be trapping on SVC instructions. Only AArch64 can + * trap on an SVC at EL1, but we don't need to special-case this + * because if this is AArch32 EL1 then arm_fgt_active() is false. + * We also know el is 0 or 1. + */ + return el =3D=3D 0 ? + FIELD_EX64(env->cp15.fgt_exec[FGTREG_HFGITR], HFGITR_EL2, SVC_EL0)= : + FIELD_EX64(env->cp15.fgt_exec[FGTREG_HFGITR], HFGITR_EL2, SVC_EL1); +} + +static CPUARMTBFlags rebuild_hflags_common(CPUARMState *env, int fp_el, + ARMMMUIdx mmu_idx, + CPUARMTBFlags flags) +{ + DP_TBFLAG_ANY(flags, FPEXC_EL, fp_el); + DP_TBFLAG_ANY(flags, MMUIDX, arm_to_core_mmu_idx(mmu_idx)); + + if (arm_singlestep_active(env)) { + DP_TBFLAG_ANY(flags, SS_ACTIVE, 1); + } + + return flags; +} + +static CPUARMTBFlags rebuild_hflags_common_32(CPUARMState *env, int fp_el, + ARMMMUIdx mmu_idx, + CPUARMTBFlags flags) +{ + bool sctlr_b =3D arm_sctlr_b(env); + + if (sctlr_b) { + DP_TBFLAG_A32(flags, SCTLR__B, 1); + } + if (arm_cpu_data_is_big_endian_a32(env, sctlr_b)) { + DP_TBFLAG_ANY(flags, BE_DATA, 1); + } + DP_TBFLAG_A32(flags, NS, !access_secure_reg(env)); + + return rebuild_hflags_common(env, fp_el, mmu_idx, flags); +} + +static CPUARMTBFlags rebuild_hflags_m32(CPUARMState *env, int fp_el, + ARMMMUIdx mmu_idx) +{ + CPUARMTBFlags flags =3D {}; + uint32_t ccr =3D env->v7m.ccr[env->v7m.secure]; + + /* Without HaveMainExt, CCR.UNALIGN_TRP is RES1. */ + if (ccr & R_V7M_CCR_UNALIGN_TRP_MASK) { + DP_TBFLAG_ANY(flags, ALIGN_MEM, 1); + } + + if (arm_v7m_is_handler_mode(env)) { + DP_TBFLAG_M32(flags, HANDLER, 1); + } + + /* + * v8M always applies stack limit checks unless CCR.STKOFHFNMIGN + * is suppressing them because the requested execution priority + * is less than 0. + */ + if (arm_feature(env, ARM_FEATURE_V8) && + !((mmu_idx & ARM_MMU_IDX_M_NEGPRI) && + (ccr & R_V7M_CCR_STKOFHFNMIGN_MASK))) { + DP_TBFLAG_M32(flags, STACKCHECK, 1); + } + + if (arm_feature(env, ARM_FEATURE_M_SECURITY) && env->v7m.secure) { + DP_TBFLAG_M32(flags, SECURE, 1); + } + + return rebuild_hflags_common_32(env, fp_el, mmu_idx, flags); +} + +/* This corresponds to the ARM pseudocode function IsFullA64Enabled(). */ +static bool sme_fa64(CPUARMState *env, int el) +{ + if (!cpu_isar_feature(aa64_sme_fa64, env_archcpu(env))) { + return false; + } + + if (el <=3D 1 && !el_is_in_host(env, el)) { + if (!FIELD_EX64(env->vfp.smcr_el[1], SMCR, FA64)) { + return false; + } + } + if (el <=3D 2 && arm_is_el2_enabled(env)) { + if (!FIELD_EX64(env->vfp.smcr_el[2], SMCR, FA64)) { + return false; + } + } + if (arm_feature(env, ARM_FEATURE_EL3)) { + if (!FIELD_EX64(env->vfp.smcr_el[3], SMCR, FA64)) { + return false; + } + } + + return true; +} + +static CPUARMTBFlags rebuild_hflags_a32(CPUARMState *env, int fp_el, + ARMMMUIdx mmu_idx) +{ + CPUARMTBFlags flags =3D {}; + int el =3D arm_current_el(env); + + if (arm_sctlr(env, el) & SCTLR_A) { + DP_TBFLAG_ANY(flags, ALIGN_MEM, 1); + } + + if (arm_el_is_aa64(env, 1)) { + DP_TBFLAG_A32(flags, VFPEN, 1); + } + + if (el < 2 && env->cp15.hstr_el2 && arm_is_el2_enabled(env) && + (arm_hcr_el2_eff(env) & (HCR_E2H | HCR_TGE)) !=3D (HCR_E2H | HCR_T= GE)) { + DP_TBFLAG_A32(flags, HSTR_ACTIVE, 1); + } + + if (arm_fgt_active(env, el)) { + DP_TBFLAG_ANY(flags, FGT_ACTIVE, 1); + if (fgt_svc(env, el)) { + DP_TBFLAG_ANY(flags, FGT_SVC, 1); + } + } + + if (env->uncached_cpsr & CPSR_IL) { + DP_TBFLAG_ANY(flags, PSTATE__IL, 1); + } + + /* + * The SME exception we are testing for is raised via + * AArch64.CheckFPAdvSIMDEnabled(), as called from + * AArch32.CheckAdvSIMDOrFPEnabled(). + */ + if (el =3D=3D 0 + && FIELD_EX64(env->svcr, SVCR, SM) + && (!arm_is_el2_enabled(env) + || (arm_el_is_aa64(env, 2) && !(env->cp15.hcr_el2 & HCR_TGE))) + && arm_el_is_aa64(env, 1) + && !sme_fa64(env, el)) { + DP_TBFLAG_A32(flags, SME_TRAP_NONSTREAMING, 1); + } + + return rebuild_hflags_common_32(env, fp_el, mmu_idx, flags); +} + +static CPUARMTBFlags rebuild_hflags_a64(CPUARMState *env, int el, int fp_e= l, + ARMMMUIdx mmu_idx) +{ + CPUARMTBFlags flags =3D {}; + ARMMMUIdx stage1 =3D stage_1_mmu_idx(mmu_idx); + uint64_t tcr =3D regime_tcr(env, mmu_idx); + uint64_t sctlr; + int tbii, tbid; + + DP_TBFLAG_ANY(flags, AARCH64_STATE, 1); + + /* Get control bits for tagged addresses. */ + tbid =3D aa64_va_parameter_tbi(tcr, mmu_idx); + tbii =3D tbid & ~aa64_va_parameter_tbid(tcr, mmu_idx); + + DP_TBFLAG_A64(flags, TBII, tbii); + DP_TBFLAG_A64(flags, TBID, tbid); + + if (cpu_isar_feature(aa64_sve, env_archcpu(env))) { + int sve_el =3D sve_exception_el(env, el); + + /* + * If either FP or SVE are disabled, translator does not need len. + * If SVE EL > FP EL, FP exception has precedence, and translator + * does not need SVE EL. Save potential re-translations by forcing + * the unneeded data to zero. + */ + if (fp_el !=3D 0) { + if (sve_el > fp_el) { + sve_el =3D 0; + } + } else if (sve_el =3D=3D 0) { + DP_TBFLAG_A64(flags, VL, sve_vqm1_for_el(env, el)); + } + DP_TBFLAG_A64(flags, SVEEXC_EL, sve_el); + } + if (cpu_isar_feature(aa64_sme, env_archcpu(env))) { + int sme_el =3D sme_exception_el(env, el); + bool sm =3D FIELD_EX64(env->svcr, SVCR, SM); + + DP_TBFLAG_A64(flags, SMEEXC_EL, sme_el); + if (sme_el =3D=3D 0) { + /* Similarly, do not compute SVL if SME is disabled. */ + int svl =3D sve_vqm1_for_el_sm(env, el, true); + DP_TBFLAG_A64(flags, SVL, svl); + if (sm) { + /* If SVE is disabled, we will not have set VL above. */ + DP_TBFLAG_A64(flags, VL, svl); + } + } + if (sm) { + DP_TBFLAG_A64(flags, PSTATE_SM, 1); + DP_TBFLAG_A64(flags, SME_TRAP_NONSTREAMING, !sme_fa64(env, el)= ); + } + DP_TBFLAG_A64(flags, PSTATE_ZA, FIELD_EX64(env->svcr, SVCR, ZA)); + } + + sctlr =3D regime_sctlr(env, stage1); + + if (sctlr & SCTLR_A) { + DP_TBFLAG_ANY(flags, ALIGN_MEM, 1); + } + + if (arm_cpu_data_is_big_endian_a64(el, sctlr)) { + DP_TBFLAG_ANY(flags, BE_DATA, 1); + } + + if (cpu_isar_feature(aa64_pauth, env_archcpu(env))) { + /* + * In order to save space in flags, we record only whether + * pauth is "inactive", meaning all insns are implemented as + * a nop, or "active" when some action must be performed. + * The decision of which action to take is left to a helper. + */ + if (sctlr & (SCTLR_EnIA | SCTLR_EnIB | SCTLR_EnDA | SCTLR_EnDB)) { + DP_TBFLAG_A64(flags, PAUTH_ACTIVE, 1); + } + } + + if (cpu_isar_feature(aa64_bti, env_archcpu(env))) { + /* Note that SCTLR_EL[23].BT =3D=3D SCTLR_BT1. */ + if (sctlr & (el =3D=3D 0 ? SCTLR_BT0 : SCTLR_BT1)) { + DP_TBFLAG_A64(flags, BT, 1); + } + } + + /* Compute the condition for using AccType_UNPRIV for LDTR et al. */ + if (!(env->pstate & PSTATE_UAO)) { + switch (mmu_idx) { + case ARMMMUIdx_E10_1: + case ARMMMUIdx_E10_1_PAN: + /* TODO: ARMv8.3-NV */ + DP_TBFLAG_A64(flags, UNPRIV, 1); + break; + case ARMMMUIdx_E20_2: + case ARMMMUIdx_E20_2_PAN: + /* + * Note that EL20_2 is gated by HCR_EL2.E2H =3D=3D 1, but EL20= _0 is + * gated by HCR_EL2. =3D=3D '11', and so is LDTR. + */ + if (env->cp15.hcr_el2 & HCR_TGE) { + DP_TBFLAG_A64(flags, UNPRIV, 1); + } + break; + default: + break; + } + } + + if (env->pstate & PSTATE_IL) { + DP_TBFLAG_ANY(flags, PSTATE__IL, 1); + } + + if (arm_fgt_active(env, el)) { + DP_TBFLAG_ANY(flags, FGT_ACTIVE, 1); + if (FIELD_EX64(env->cp15.fgt_exec[FGTREG_HFGITR], HFGITR_EL2, ERET= )) { + DP_TBFLAG_A64(flags, FGT_ERET, 1); + } + if (fgt_svc(env, el)) { + DP_TBFLAG_ANY(flags, FGT_SVC, 1); + } + } + + if (cpu_isar_feature(aa64_mte, env_archcpu(env))) { + /* + * Set MTE_ACTIVE if any access may be Checked, and leave clear + * if all accesses must be Unchecked: + * 1) If no TBI, then there are no tags in the address to check, + * 2) If Tag Check Override, then all accesses are Unchecked, + * 3) If Tag Check Fail =3D=3D 0, then Checked access have no effe= ct, + * 4) If no Allocation Tag Access, then all accesses are Unchecked. + */ + if (allocation_tag_access_enabled(env, el, sctlr)) { + DP_TBFLAG_A64(flags, ATA, 1); + if (tbid + && !(env->pstate & PSTATE_TCO) + && (sctlr & (el =3D=3D 0 ? SCTLR_TCF0 : SCTLR_TCF))) { + DP_TBFLAG_A64(flags, MTE_ACTIVE, 1); + } + } + /* And again for unprivileged accesses, if required. */ + if (EX_TBFLAG_A64(flags, UNPRIV) + && tbid + && !(env->pstate & PSTATE_TCO) + && (sctlr & SCTLR_TCF0) + && allocation_tag_access_enabled(env, 0, sctlr)) { + DP_TBFLAG_A64(flags, MTE0_ACTIVE, 1); + } + /* Cache TCMA as well as TBI. */ + DP_TBFLAG_A64(flags, TCMA, aa64_va_parameter_tcma(tcr, mmu_idx)); + } + + return rebuild_hflags_common(env, fp_el, mmu_idx, flags); +} + +static CPUARMTBFlags rebuild_hflags_internal(CPUARMState *env) +{ + int el =3D arm_current_el(env); + int fp_el =3D fp_exception_el(env, el); + ARMMMUIdx mmu_idx =3D arm_mmu_idx_el(env, el); + + if (is_a64(env)) { + return rebuild_hflags_a64(env, el, fp_el, mmu_idx); + } else if (arm_feature(env, ARM_FEATURE_M)) { + return rebuild_hflags_m32(env, fp_el, mmu_idx); + } else { + return rebuild_hflags_a32(env, fp_el, mmu_idx); + } +} + +void arm_rebuild_hflags(CPUARMState *env) +{ + env->hflags =3D rebuild_hflags_internal(env); +} + +/* + * If we have triggered a EL state change we can't rely on the + * translator having passed it to us, we need to recompute. + */ +void HELPER(rebuild_hflags_m32_newel)(CPUARMState *env) +{ + int el =3D arm_current_el(env); + int fp_el =3D fp_exception_el(env, el); + ARMMMUIdx mmu_idx =3D arm_mmu_idx_el(env, el); + + env->hflags =3D rebuild_hflags_m32(env, fp_el, mmu_idx); +} + +void HELPER(rebuild_hflags_m32)(CPUARMState *env, int el) +{ + int fp_el =3D fp_exception_el(env, el); + ARMMMUIdx mmu_idx =3D arm_mmu_idx_el(env, el); + + env->hflags =3D rebuild_hflags_m32(env, fp_el, mmu_idx); +} + +/* + * If we have triggered a EL state change we can't rely on the + * translator having passed it to us, we need to recompute. + */ +void HELPER(rebuild_hflags_a32_newel)(CPUARMState *env) +{ + int el =3D arm_current_el(env); + int fp_el =3D fp_exception_el(env, el); + ARMMMUIdx mmu_idx =3D arm_mmu_idx_el(env, el); + env->hflags =3D rebuild_hflags_a32(env, fp_el, mmu_idx); +} + +void HELPER(rebuild_hflags_a32)(CPUARMState *env, int el) +{ + int fp_el =3D fp_exception_el(env, el); + ARMMMUIdx mmu_idx =3D arm_mmu_idx_el(env, el); + + env->hflags =3D rebuild_hflags_a32(env, fp_el, mmu_idx); +} + +void HELPER(rebuild_hflags_a64)(CPUARMState *env, int el) +{ + int fp_el =3D fp_exception_el(env, el); + ARMMMUIdx mmu_idx =3D arm_mmu_idx_el(env, el); + + env->hflags =3D rebuild_hflags_a64(env, el, fp_el, mmu_idx); +} + +void assert_hflags_rebuild_correctly(CPUARMState *env) +{ +#ifdef CONFIG_DEBUG_TCG + CPUARMTBFlags c =3D env->hflags; + CPUARMTBFlags r =3D rebuild_hflags_internal(env); + + if (unlikely(c.flags !=3D r.flags || c.flags2 !=3D r.flags2)) { + fprintf(stderr, "TCG hflags mismatch " + "(current:(0x%08x,0x" TARGET_FMT_lx ")" + " rebuilt:(0x%08x,0x" TARGET_FMT_lx ")\n", + c.flags, c.flags2, r.flags, r.flags2); + abort(); + } +#endif +} diff --git a/target/arm/tcg/meson.build b/target/arm/tcg/meson.build index fa8a9eab933..d27e76af6cb 100644 --- a/target/arm/tcg/meson.build +++ b/target/arm/tcg/meson.build @@ -24,6 +24,7 @@ arm_ss.add(files( 'translate-neon.c', 'translate-vfp.c', 'crypto_helper.c', + 'hflags.c', 'iwmmxt_helper.c', 'm_helper.c', 'mve_helper.c', --=20 2.34.1 From nobody Tue May 14 10:40:27 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id s9-20020a5d4249000000b002c5598c14acsm7158514wrr.6.2023.02.27.06.01.16 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Feb 2023 06:01:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=6hrZpnhPLRDXNa3A83fUHvIa4VTeZDIvb4ThTrNTe+A=; b=Kj1DMvseuh3f0ipPcHG5Sto6W8TOREEnezReAJy1Gu/ST4WQINTz8CivgrRvJ2mAQC UWbIDcW7iIOH0R+bfMK+194dJruazsloVtM02w0SodEKNkA+ndkwaiR27ItciFVoJ2lu zDv4FBoDg42h6KD1y9jhDLhd/n8Bx4QhBY6DZOfMXd9TmCCGvYhGOjLySzRXJhFJHuRn tg6B/Y7wAW+fgs1gEtxBHbx5lHrpcn9ofvEag2PIs1xqVL+KlLALDiLoxUKSq+W9fEDo qGCrXUl6UCDZFcbOEg/v4wYfI6iO9c3Zemjqkx1jYHL8R62YkttoRAMpDkb4qf2JN1hZ TLwg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=6hrZpnhPLRDXNa3A83fUHvIa4VTeZDIvb4ThTrNTe+A=; b=UAgAHzO/u+XphMdSUxgOWUAHfRgWL2Qk8OsER8mZHE0mYKNSnuLViEAbUhXlOSA6wF s5+P/Y+C5OjXBNpp6JIf3JHCrZd9shDfjtIT7qj1EBoS15h6prlGcAw6Wzgfksj37Qu9 3L6DD1jVPxGEPqFQiZrcTSiws+d/UygjqND4PxbI3SFm+LKUqFZhPuAH7j7Jw3VfoqIx 8ZBHjRjXM1DI8KTCbc9X1HKv85Xo1T+Uk0oDB5rA+YjtAaX5ip73ad7ZAixgI0APtO/r nrzDVobqAgs7YqvXu57LG03iIWlk0thJ7tA7Hf64V9VLnHijk8feP0SyuXPcI/zcOSH3 rsMQ== X-Gm-Message-State: AO0yUKWJgdC9zxP3ZpT2W8Tfc+uFifdaRnAngYr+vIZbOsrdZanFwRnW eOTjY0x5CELLeG06T3+gh3zds3ktTafF+JQW X-Google-Smtp-Source: AK7set8Ii9fEY+YAqTS9YZkMJXhBIHxpd/q74RDHPwIC52shtbeYBkfWSHBlYa6Ci+kMO7BRXJ7lYg== X-Received: by 2002:a7b:c384:0:b0:3ea:d620:570a with SMTP id s4-20020a7bc384000000b003ead620570amr12963128wmj.38.1677506477153; Mon, 27 Feb 2023 06:01:17 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 09/25] target/arm: Move regime_using_lpae_format into internal.h Date: Mon, 27 Feb 2023 14:00:46 +0000 Message-Id: <20230227140102.3712344-10-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230227140102.3712344-1-peter.maydell@linaro.org> References: <20230227140102.3712344-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1677508034616100001 From: Fabiano Rosas This function is needed by common code (ptw.c), so move it along with the other regime_* functions in internal.h. When we enable the build without TCG, the tlb_helper.c file will not be present. Signed-off-by: Fabiano Rosas Reviewed-by: Richard Henderson Tested-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Peter Maydell --- target/arm/internals.h | 21 ++++++++++++++++++--- target/arm/tcg/tlb_helper.c | 18 ------------------ 2 files changed, 18 insertions(+), 21 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index ed48f8c9a69..680c5747170 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -600,9 +600,6 @@ int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx); /* Return the MMU index for a v7M CPU in the specified security state */ ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate); =20 -/* Return true if the translation regime is using LPAE format page tables = */ -bool regime_using_lpae_format(CPUARMState *env, ARMMMUIdx mmu_idx); - /* * Return true if the stage 1 translation regime is using LPAE * format page tables @@ -767,6 +764,24 @@ static inline uint64_t regime_tcr(CPUARMState *env, AR= MMMUIdx mmu_idx) return env->cp15.tcr_el[regime_el(env, mmu_idx)]; } =20 +/* Return true if the translation regime is using LPAE format page tables = */ +static inline bool regime_using_lpae_format(CPUARMState *env, ARMMMUIdx mm= u_idx) +{ + int el =3D regime_el(env, mmu_idx); + if (el =3D=3D 2 || arm_el_is_aa64(env, el)) { + return true; + } + if (arm_feature(env, ARM_FEATURE_PMSA) && + arm_feature(env, ARM_FEATURE_V8)) { + return true; + } + if (arm_feature(env, ARM_FEATURE_LPAE) + && (regime_tcr(env, mmu_idx) & TTBCR_EAE)) { + return true; + } + return false; +} + /** * arm_num_brps: Return number of implemented breakpoints. * Note that the ID register BRPS field is "number of bps - 1", diff --git a/target/arm/tcg/tlb_helper.c b/target/arm/tcg/tlb_helper.c index 60abcbebe64..31eb77f7df9 100644 --- a/target/arm/tcg/tlb_helper.c +++ b/target/arm/tcg/tlb_helper.c @@ -12,24 +12,6 @@ #include "exec/helper-proto.h" =20 =20 -/* Return true if the translation regime is using LPAE format page tables = */ -bool regime_using_lpae_format(CPUARMState *env, ARMMMUIdx mmu_idx) -{ - int el =3D regime_el(env, mmu_idx); - if (el =3D=3D 2 || arm_el_is_aa64(env, el)) { - return true; - } - if (arm_feature(env, ARM_FEATURE_PMSA) && - arm_feature(env, ARM_FEATURE_V8)) { - return true; - } - if (arm_feature(env, ARM_FEATURE_LPAE) - && (regime_tcr(env, mmu_idx) & TTBCR_EAE)) { - return true; - } - return false; -} - /* * Returns true if the stage 1 translation regime is using LPAE format page * tables. Used when raising alignment exceptions, whose FSR changes depen= ding --=20 2.34.1 From nobody Tue May 14 10:40:27 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1677506527; cv=none; d=zohomail.com; s=zohoarc; b=KQVc54PAxX2D1rlsiJG4UjftyY42GYvG8TJ4TF0YvnqpQLwnx2sLBasA4X7kE5AFW1I8QyHxkRoEdLrpWYh1aHFkW/4Df7W9J9AueiY47V9DjnBIqlAgpEr3dn3HZEn9Qih1wKS9U9kZoYcdtmEXAks6zQHxALLkNfzrxI6uas0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1677506527; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=0HDhvD5xSaakovM1bRp/U074mbpNZA16y8F0RLm3wAY=; b=ckkSssn0MkEdt5cqDO9bQVeQCTNqaxbL8WrbvYTewIX1nY8bSvEf0meGzQbfC3QwiTDLLFAsCxOkhLyC1fQcYHj3Qu15f/bAfwcWdJ0yCZCUVdUn/TIdReikxkug8TfgFdQ+iKKNPfF49VAzdhZYjUWiE5dPSnaH9wkjEa72EQU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1677506527583314.9619610797972; Mon, 27 Feb 2023 06:02:07 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pWe4q-00019k-Ah; Mon, 27 Feb 2023 09:02:04 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pWe4B-0000eB-ST for qemu-devel@nongnu.org; Mon, 27 Feb 2023 09:01:29 -0500 Received: from mail-wr1-x433.google.com ([2a00:1450:4864:20::433]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pWe48-0007Y0-J3 for qemu-devel@nongnu.org; Mon, 27 Feb 2023 09:01:23 -0500 Received: by mail-wr1-x433.google.com with SMTP id h14so6337939wru.4 for ; Mon, 27 Feb 2023 06:01:20 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id s9-20020a5d4249000000b002c5598c14acsm7158514wrr.6.2023.02.27.06.01.17 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Feb 2023 06:01:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=0HDhvD5xSaakovM1bRp/U074mbpNZA16y8F0RLm3wAY=; b=Sj5jP/yTdFoAkecfQvfdeh42lr2ulSkySYpL4tAaIIlNACzRcUykV1ASZBZqDliQsf GHCGGG/HrYAmoRmAlt0UQlmlyNNKsoEM4ohmGjbNZcBpc7yqcdkMtJc3HFSZquwwjyg7 +Mj7UkKZqQCuiXtVBwFDfBUoMzTGLYPIvc4VCWysJ1vYXsMkq7onRFA8WzGds5AAzzOZ F9ebpGjxIFkoSfqhhtT2kz2S12oUnl4HmxeDTkqCbrfeLbswvPUxg4weh6s7Brl+koHa aS5XlsiWN50I49gkh0Pw/XJL/I3Np+8uGgim/0aPfhw7qo69ft1c7L5mswG412+DNAKD 70lA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=0HDhvD5xSaakovM1bRp/U074mbpNZA16y8F0RLm3wAY=; b=YnbZP67SYrUBqxgk0+lkvirRioLvfUoB0RfPg3gN0eAEAVdZ2tL3g3ohz1aAeMTT0x oEua9uhj+wGVl+VKmEtFVJSXqO9y3LxQ342JEsB4ufn3lgdWfNLEGEVW0ycwPinfqORm EUx1Al/05W4KKu5LJDY6fodCwRViQFKGWE0lMQDmY+Opik4Oi63TFSPKeF1Goi6cYscx eKq/6kHpc3Lx6fdlRnBJleig4JHSOwECUNS9dRbhU+fPodAyjBx8pLs9EgDqj9LxomZZ jqeV/MXShc0djPtAdioiho6IwOpAkQUVPs2Xe7f6XxjCVb33lLCPmZLTj8url0/OkGBC F5Gg== X-Gm-Message-State: AO0yUKVRd0Shulb46yukkK49t5KyYM0mTqMkjQRTcz8aRgOHL/Uc9iAY EpwhORka6NyC+C4jPuusipQskIKUqCEkwoc2 X-Google-Smtp-Source: AK7set9TB2RCvG1J81PlhLgZxPH/Z/hWvpzqgwsBr78sKlPEyuCFIn3DhiGbZFK4xX47JL5s18v0kQ== X-Received: by 2002:adf:f386:0:b0:2c7:995f:3030 with SMTP id m6-20020adff386000000b002c7995f3030mr7859613wro.60.1677506478827; Mon, 27 Feb 2023 06:01:18 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 10/25] target/arm: Don't access TCG code when debugging with KVM Date: Mon, 27 Feb 2023 14:00:47 +0000 Message-Id: <20230227140102.3712344-11-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230227140102.3712344-1-peter.maydell@linaro.org> References: <20230227140102.3712344-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1677506569948100001 From: Fabiano Rosas When TCG is disabled this part of the code should not be reachable, so wrap it with an ifdef for now. Signed-off-by: Fabiano Rosas Reviewed-by: Richard Henderson Tested-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Peter Maydell --- target/arm/ptw.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 2b125fff446..be0cc6bc15f 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -254,6 +254,7 @@ static bool S1_ptw_translate(CPUARMState *env, S1Transl= ate *ptw, ptw->out_host =3D NULL; ptw->out_rw =3D false; } else { +#ifdef CONFIG_TCG CPUTLBEntryFull *full; int flags; =20 @@ -270,6 +271,9 @@ static bool S1_ptw_translate(CPUARMState *env, S1Transl= ate *ptw, ptw->out_rw =3D full->prot & PAGE_WRITE; pte_attrs =3D full->pte_attrs; pte_secure =3D full->attrs.secure; +#else + g_assert_not_reached(); +#endif } =20 if (regime_is_stage2(s2_mmu_idx)) { --=20 2.34.1 From nobody Tue May 14 10:40:27 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1677506940; cv=none; d=zohomail.com; s=zohoarc; b=IDGesEjdRaZQPjBIM+tDmzsY6e/E3qQF99lJamBmhr6lNnTbZej3M8Ooyp9/5uG62sr9ERGy4XDY+2ybjEhY3lsEKG9doDZxZqdKXBwQfxi2TtX9vd/BJgkV4HRDLI7g85Kweew3WUYWwsphw+9Y/1IEX7fTQrUY+6guO2oBlgg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1677506940; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=FhwqGr42a8O7VHpaKqpcSkL5g78mGefM0X1jMjxurOQ=; b=CtCUit7gplnwslv45X3c5ug7QBqOoSKVcmjP+EGxzQ9ziqWEKboIEXoe2PnZghvny68DQ8UVZMc7HkIPRD3Ev3lXUo+BG8JwSKq9cSVMnigA9N2WNelxmEkU736n5LV7/8gbIwAFMCpcrzVCaZocaK8GHoFDBpQg6Zb2yoxQIdM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1677506939979659.652752813451; Mon, 27 Feb 2023 06:08:59 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pWe58-0002ES-KK; Mon, 27 Feb 2023 09:02:22 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pWe4B-0000eA-S8 for qemu-devel@nongnu.org; Mon, 27 Feb 2023 09:01:29 -0500 Received: from mail-wm1-x330.google.com ([2a00:1450:4864:20::330]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pWe49-0007XC-U8 for qemu-devel@nongnu.org; Mon, 27 Feb 2023 09:01:23 -0500 Received: by mail-wm1-x330.google.com with SMTP id o38-20020a05600c512600b003e8320d1c11so6627824wms.1 for ; Mon, 27 Feb 2023 06:01:20 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id s9-20020a5d4249000000b002c5598c14acsm7158514wrr.6.2023.02.27.06.01.19 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Feb 2023 06:01:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=FhwqGr42a8O7VHpaKqpcSkL5g78mGefM0X1jMjxurOQ=; b=yB5sAnZzMUf8BK4mQ6+/evWC0D4cShyIVQjzxTYHaettME7cOIVNuxwVpSBOsP2mAK LE8ybqYu5RvUOysW2f4reNejpKdqK8YAuyuo+BK1vnpozPEl4fS/J6QyoS3GDGmVi87e IfRX5inTknv9dKNpj42OMmDcZ7BRpKCHq37vyp7kKyqZ2s2NEp7v8ar8pJtssMFDllU8 2NOHXIQv48yAB4DbpATL2nFxGV5bj4ITp8Ud3Cn9F1LEsJkIKwnFtWZ46HAv2RA4FJ5j EDUFhrvZAuBy4TcFXFg597L+gOmx0l+Knv7IxwkaToQATm0t7KVhrzjixFTmsWORE1XO zP3w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=FhwqGr42a8O7VHpaKqpcSkL5g78mGefM0X1jMjxurOQ=; b=676MCe7ieC8twkQhApyJwAaqYkSxiOrjnHWGLN6sDoz3rmOK0ktrDo43R64zgPegX0 UuhrOuaGJ0SYsmI5Sh7XQeMsn3mxHng9GLz9vu/w71T8nRgFZjxCxjsPs2ttW8ecokEl DmO+b0EwHGc3vTXoN4PP0pznphFmXRQo5WUG29SEj0iIkXDqsMLOvGfW+lDPgxaBMlwv BpnK4FDwl4JQT8mNN8hHJtFrUcjS5+tq+LTAzIYoltwjfzSj6SoOnlFxfBPpTSrF0yxo /uxGupgow4i1mUhdfYDfq68WsMVbKU7pQ1iPbzTWdtVd6ISwD78Yq8wmGu8b72MSXpSC h7qw== X-Gm-Message-State: AO0yUKVGn7FPH+Cde7pW304OJTtSEFRcL6lqGSAGRdf7/aULyJ9yoibg 17DEpjXiM5tcBQZBzptR+cWO19/VNr/iDR6u X-Google-Smtp-Source: AK7set8wGZr3V94Zdzj9IZKsq2QhmLug8iA0bSTDQcKB+pwSjG+UOtQYA+LAPFB6dULWhI3fZ0Lzfg== X-Received: by 2002:a05:600c:810:b0:3dc:557f:6123 with SMTP id k16-20020a05600c081000b003dc557f6123mr18705719wmp.1.1677506480195; Mon, 27 Feb 2023 06:01:20 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 11/25] cpu-defs.h: Expose CPUTLBEntryFull to non-TCG code Date: Mon, 27 Feb 2023 14:00:48 +0000 Message-Id: <20230227140102.3712344-12-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230227140102.3712344-1-peter.maydell@linaro.org> References: <20230227140102.3712344-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1677506941081100011 From: Fabiano Rosas This struct has no dependencies on TCG code and it is being used in target/arm/ptw.c to simplify the passing around of page table walk results. Those routines can be reached by KVM code via the gdbstub breakpoint code, so take the structure out of CONFIG_TCG to make it visible when building with --disable-tcg. Signed-off-by: Fabiano Rosas Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Peter Maydell --- include/exec/cpu-defs.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h index 21309cf567a..d5a4f307178 100644 --- a/include/exec/cpu-defs.h +++ b/include/exec/cpu-defs.h @@ -135,6 +135,10 @@ typedef struct CPUTLBEntry { =20 QEMU_BUILD_BUG_ON(sizeof(CPUTLBEntry) !=3D (1 << CPU_TLB_ENTRY_BITS)); =20 + +#endif /* !CONFIG_USER_ONLY && CONFIG_TCG */ + +#if !defined(CONFIG_USER_ONLY) /* * The full TLB entry, which is not accessed by generated TCG code, * so the layout is not as critical as that of CPUTLBEntry. This is @@ -176,7 +180,9 @@ typedef struct CPUTLBEntryFull { TARGET_PAGE_ENTRY_EXTRA #endif } CPUTLBEntryFull; +#endif /* !CONFIG_USER_ONLY */ =20 +#if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG) /* * Data elements that are per MMU mode, minus the bits accessed by * the TCG fast path. --=20 2.34.1 From nobody Tue May 14 10:40:27 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1677507302; cv=none; d=zohomail.com; s=zohoarc; b=ZGylhwCnoSg4nJh3JkkJRQ1vDKwsAJv/JS1S9+NQ58c+RThrDVaiauILXjINHrjIBL0RPzFW3SOdBPgXfVgmysmHEpnzDr5U+ZlEvxoyLOKm/xMsOv0lrgBTRIxsUItaw5ERh3B9l5mI/NzoRuucdLhqKZyeawl4CUpl6s/rcU4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1677507302; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=WQzF5MTagtjkGDrk69RrslbmWiJlU48DYJ35+pc8mww=; b=YtLghnJ7ia/Pev8j+TYvYhRUmX0bL6JoK7HLK3PDk+U6P+xflmes+ZzjOGGnc641x4otc6xGEUymohRQTzwaHUxF2/U1z3T82FcMh+m3bw2Eyd0dXWqyHdRtJSB1qKq2Mx/341U1PN8Ikdrs8EpOu3t/PWQrbN0OKN2cVD0J264= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1677507302168275.5581674029771; Mon, 27 Feb 2023 06:15:02 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pWe5B-0002MD-3h; Mon, 27 Feb 2023 09:02:25 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pWe4C-0000eF-Oc for qemu-devel@nongnu.org; Mon, 27 Feb 2023 09:01:33 -0500 Received: from mail-wr1-x436.google.com ([2a00:1450:4864:20::436]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pWe4A-0007WH-Pv for qemu-devel@nongnu.org; Mon, 27 Feb 2023 09:01:24 -0500 Received: by mail-wr1-x436.google.com with SMTP id bx12so3174848wrb.11 for ; Mon, 27 Feb 2023 06:01:22 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1677507304225100001 From: Fabiano Rosas This test currently fails when run on a host for which the QEMU target has no default machine set: ERROR| Output: qemu-system-aarch64: No machine specified, and there is no default Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Fabiano Rosas Signed-off-by: Peter Maydell --- tests/avocado/version.py | 1 + 1 file changed, 1 insertion(+) diff --git a/tests/avocado/version.py b/tests/avocado/version.py index ded7f039c1b..dd775955eb8 100644 --- a/tests/avocado/version.py +++ b/tests/avocado/version.py @@ -15,6 +15,7 @@ class Version(QemuSystemTest): """ :avocado: tags=3Dquick + :avocado: tags=3Dmachine:none """ def test_qmp_human_info_version(self): self.vm.add_args('-nodefaults') --=20 2.34.1 From nobody Tue May 14 10:40:27 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id s9-20020a5d4249000000b002c5598c14acsm7158514wrr.6.2023.02.27.06.01.22 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Feb 2023 06:01:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=/KzSvjX9f4BCGIMkUG2tIfmdibE7Hacb/lDW3ntcm+Y=; b=wYdBEPwFeJ9dtloednwvpgqd2a3dmH9iCt2y2zuh/1aqxEKhEstoy318C8gaXaH6JO uQnSouejSOIllwnHROaREn1E38v61OQhqzXbgUtS+1l1r4cYxiD1wb+LlpHBdPK5X3Ck 3hB4ric1YZ0PT/PjRIk2PyjxRpUBRP+/jV1tJs+Piag/6hWMx2qjql6lCYFbF3sRgdaR XOcSeckxm4Ah6hm0QLaJC1OmZmH6qq3NkY1cEuEr0DEfMcleBCNPjcxAVt1BVtXWq+yZ C3bmm2n+2a2gOWN6yKCEmfziZfojKKkYdi5YAZdswYvF2qZGc9GsejfHXfIQGM+WNjpT sEuA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=/KzSvjX9f4BCGIMkUG2tIfmdibE7Hacb/lDW3ntcm+Y=; b=Q0paCAMjDxM+NtdnuvKCRsk5y42plomSeThsgw89cDSa7zKrR7+Naq9EghBPXh0aPz 8cSSTJDgORrTODJREs+3dNOgoku+zCuyuVcOVH2ccSxHE3hNb+2XX3e9jTuh2Xf+Huhi 9J+twpfIDP7NOIZ1ZCqbfDyDw4RVEXUSKpVaxMqs31vb26FesXNiz4miVjMxUnNxFQR+ 6xfuvDwEmC+a9RmiNTCwHjZxv4byuYp2qnL07vyqgNUjWJdXptID/LB4WrrlIbXjEArL upJPUOKIsUIWoa3HQ1stELRroBsLz6teDV5wUfB1IaKruSARS22DTS9DTBmnyymIAJbP FZeQ== X-Gm-Message-State: AO0yUKW3cqokAG9g6itn0QhQP4MB8WvebvFg0nV88FJI0SOBonXw2fEA JnU0qLUOYWB6oz3+chW/uyVf+C7rmI7YyAoX X-Google-Smtp-Source: AK7set80suw588oUiYmCIOsVeU+o4gBOPnvqAB+HhipYkzcFcAKCt+Kb9srii+VG3r3J5taO+aj/yQ== X-Received: by 2002:adf:f34f:0:b0:2c7:fcc:2501 with SMTP id e15-20020adff34f000000b002c70fcc2501mr12136896wrp.28.1677506483327; Mon, 27 Feb 2023 06:01:23 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 13/25] hw/gpio/max7310: Simplify max7310_realize() Date: Mon, 27 Feb 2023 14:00:50 +0000 Message-Id: <20230227140102.3712344-14-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230227140102.3712344-1-peter.maydell@linaro.org> References: <20230227140102.3712344-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1677507498249100004 From: Philippe Mathieu-Daud=C3=A9 Since &I2C_SLAVE(dev)->qdev =3D=3D dev, no need to go back and forth with QOM type casting. Directly use 'dev'. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Message-id: 20230220115114.25237-2-philmd@linaro.org Signed-off-by: Peter Maydell --- hw/gpio/max7310.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/hw/gpio/max7310.c b/hw/gpio/max7310.c index db6b5e3d764..031482d9398 100644 --- a/hw/gpio/max7310.c +++ b/hw/gpio/max7310.c @@ -183,11 +183,10 @@ static void max7310_gpio_set(void *opaque, int line, = int level) * but also accepts sequences that are not SMBus so return an I2C device. = */ static void max7310_realize(DeviceState *dev, Error **errp) { - I2CSlave *i2c =3D I2C_SLAVE(dev); MAX7310State *s =3D MAX7310(dev); =20 - qdev_init_gpio_in(&i2c->qdev, max7310_gpio_set, 8); - qdev_init_gpio_out(&i2c->qdev, s->handler, 8); + qdev_init_gpio_in(dev, max7310_gpio_set, ARRAY_SIZE(s->handler)); + qdev_init_gpio_out(dev, s->handler, ARRAY_SIZE(s->handler)); } =20 static void max7310_class_init(ObjectClass *klass, void *data) --=20 2.34.1 From nobody Tue May 14 10:40:27 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1677506657; cv=none; d=zohomail.com; s=zohoarc; b=hQgYAxpwt2DDxMotnAeCdKz0lqEyT4JN8SyrMgeFWIGgDn/ENiL/x0Dm8Qq4LP+lEJOUp+DX5eSOAaB4xvRx7SYwdEedRcsV8+XJgyZlblmCgdkmePfWIfZpduj5AuFbZY4GpGUaCOQF44w3Wge6fMtTteELE+42vCWvZvOaYtQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1677506657; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=jYGZU16lCx9TTfWKSjti8JTz2r03DCjlL5gG1/zGeXY=; b=PEbrmtEFfBymBKoRzaX35Aq2beC5GVqtAIPhFd6sMoKMm8ziMGLtJW/rfHQGy8cOVuBj+NNwFO3i+Tjho8M0ImHG6Luw7Y1iODXYzOJplDwFLwTnryRXU+7ebLv+03TtMZ+8j0u9lu+Cq7ekBjgLIBbglCqPqSVPnzcZXYGyizs= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1677506657582462.24426435064163; Mon, 27 Feb 2023 06:04:17 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pWe55-00023u-Hv; Mon, 27 Feb 2023 09:02:19 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pWe4G-0000iC-7U for qemu-devel@nongnu.org; Mon, 27 Feb 2023 09:01:33 -0500 Received: from mail-wr1-x42c.google.com ([2a00:1450:4864:20::42c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pWe4E-0007WR-D8 for qemu-devel@nongnu.org; Mon, 27 Feb 2023 09:01:27 -0500 Received: by mail-wr1-x42c.google.com with SMTP id r7so6330594wrz.6 for ; Mon, 27 Feb 2023 06:01:25 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id s9-20020a5d4249000000b002c5598c14acsm7158514wrr.6.2023.02.27.06.01.23 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Feb 2023 06:01:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=jYGZU16lCx9TTfWKSjti8JTz2r03DCjlL5gG1/zGeXY=; b=R3h+lMfQ++CYNsE0UU2FacFfDQFkk6Rwy2Mvjm4/MsZ1OkaezdHPQeRfE0UXeQsxDv MXb6n4TSc6HtKm21fIASYdW9kiMHzNOuvz/fYE81wraOguwmWtqE/u7cun3QFbH+2Zi1 x2b/GMMX/BwHDiamJSCZcKdJLB1sOUDKzgdl9LQCPADjST572yGkLgw+uKQwFzaN0DoN jEMhlj0r8UtlulQzLwgWBL0t09Zq6aK9TeuEoC66n2ViLvAvtOt7efW+oBPLoNcJLEi/ RmzPyvuiIrWdnGYOGdoXFRV5JVpxYR8Mr4BPLPZPWrsbzgs7IH+GCwOkxKBP0/CppXJd VDZQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=jYGZU16lCx9TTfWKSjti8JTz2r03DCjlL5gG1/zGeXY=; b=u2T3FbMkPmQJtZmlvo/+sZEHWCtmflnXyklymNxcKlQ1A7RMW/+52yrvGZS+J5mg1S OjcR9UzwzbX6KFJsyrrKqp18Ksyo0rv4Ju+Veh/Pbt2bIirOzEFAjriEr18tKMXK4Ytk HA0Wxhga1sRzKVaZKjtIWqhKZWEJY+9UT7NiMBRNQ0Y/wn8I2qrN79StrIJb3Iq2z/i5 K5dcN2dd2SXHA1b5qAZObkjBytzrnsTB23S32rqfcKFNcuSnPwkd0gzuoRuBBYMncHUN s/TZYNgohBuEIX/jeyz2VfVC3ePP1mGa5w+Exr8nwbhnn8s7y+kuTP8MWOV4PjpdOYk+ bRnw== X-Gm-Message-State: AO0yUKWKLN9hZ/ewtmBIL5padcP0lRkNGoT6kKnraW7bndB3fvSFIEhb MWRvXnBfKFkyVbpXzdvA342YKLhtcLjaowBv X-Google-Smtp-Source: AK7set81STUvXGSkFwZ5YKqvEw+c4ELrTeq2QoOOOoWwi0BAOMlaRi4GK5H1cLf4jmzEZZKxTaJV9A== X-Received: by 2002:adf:f5cb:0:b0:2cc:be:be0 with SMTP id k11-20020adff5cb000000b002cc00be0be0mr1846159wrp.41.1677506484575; Mon, 27 Feb 2023 06:01:24 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 14/25] hw/char/pl011: Un-inline pl011_create() Date: Mon, 27 Feb 2023 14:00:51 +0000 Message-Id: <20230227140102.3712344-15-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230227140102.3712344-1-peter.maydell@linaro.org> References: <20230227140102.3712344-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1677506710483100001 From: Philippe Mathieu-Daud=C3=A9 pl011_create() is only used in DeviceRealize handlers, not a hot-path. Inlining is not justified. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Richard Henderson Message-id: 20230220115114.25237-3-philmd@linaro.org Signed-off-by: Peter Maydell --- include/hw/char/pl011.h | 19 +------------------ hw/char/pl011.c | 17 +++++++++++++++++ 2 files changed, 18 insertions(+), 18 deletions(-) diff --git a/include/hw/char/pl011.h b/include/hw/char/pl011.h index 926322e242d..d82870c0069 100644 --- a/include/hw/char/pl011.h +++ b/include/hw/char/pl011.h @@ -15,10 +15,8 @@ #ifndef HW_PL011_H #define HW_PL011_H =20 -#include "hw/qdev-properties.h" #include "hw/sysbus.h" #include "chardev/char-fe.h" -#include "qapi/error.h" #include "qom/object.h" =20 #define TYPE_PL011 "pl011" @@ -57,22 +55,7 @@ struct PL011State { const unsigned char *id; }; =20 -static inline DeviceState *pl011_create(hwaddr addr, - qemu_irq irq, - Chardev *chr) -{ - DeviceState *dev; - SysBusDevice *s; - - dev =3D qdev_new("pl011"); - s =3D SYS_BUS_DEVICE(dev); - qdev_prop_set_chr(dev, "chardev", chr); - sysbus_realize_and_unref(s, &error_fatal); - sysbus_mmio_map(s, 0, addr); - sysbus_connect_irq(s, 0, irq); - - return dev; -} +DeviceState *pl011_create(hwaddr addr, qemu_irq irq, Chardev *chr); =20 static inline DeviceState *pl011_luminary_create(hwaddr addr, qemu_irq irq, diff --git a/hw/char/pl011.c b/hw/char/pl011.c index c15cb7af20b..77bbc2a982b 100644 --- a/hw/char/pl011.c +++ b/hw/char/pl011.c @@ -19,10 +19,12 @@ */ =20 #include "qemu/osdep.h" +#include "qapi/error.h" #include "hw/char/pl011.h" #include "hw/irq.h" #include "hw/sysbus.h" #include "hw/qdev-clock.h" +#include "hw/qdev-properties.h" #include "hw/qdev-properties-system.h" #include "migration/vmstate.h" #include "chardev/char-fe.h" @@ -31,6 +33,21 @@ #include "qemu/module.h" #include "trace.h" =20 +DeviceState *pl011_create(hwaddr addr, qemu_irq irq, Chardev *chr) +{ + DeviceState *dev; + SysBusDevice *s; + + dev =3D qdev_new("pl011"); + s =3D SYS_BUS_DEVICE(dev); + qdev_prop_set_chr(dev, "chardev", chr); + sysbus_realize_and_unref(s, &error_fatal); + sysbus_mmio_map(s, 0, addr); + sysbus_connect_irq(s, 0, irq); + + return dev; +} + #define PL011_INT_TX 0x20 #define PL011_INT_RX 0x10 =20 --=20 2.34.1 From nobody Tue May 14 10:40:27 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1677506528; cv=none; d=zohomail.com; s=zohoarc; b=Qte+3WUDZplggasnBcal3Rq3n7Nf9ThE2w8ndcw8HzimT5tV23hG2C7d3mvdT716d6w5UvsznEtiXoTgt+kdWGI8BDVGjG+ITc3YBssfxtL3pJwent1lKtFaY30pQ6xN87mQg3uanUM5YMEi7njpL2T1+1x0vuL/Rr28v5S9PY8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1677506528; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=VDLsCaYW69zOK5yA/VohVYicyAoFr83OJm2v2NkJmG4=; b=UYLFB23dh8AtuJM5f0sAcPljuA9Whdx4HYhj9BV7/L9a2+1vLL0DqEpDbHzYIPflQf1a7yK89UF7+iY8yVK/6VqwJoaREI+5YEezWUPe5QmX0kcHDuCQseBtGge8VjLnI4RuggdP9T9L0CSZ+TCjHUezJ4K/C8nbs3afNhc1uj0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1677506528144350.5641230434163; Mon, 27 Feb 2023 06:02:08 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pWe4p-000141-SV; Mon, 27 Feb 2023 09:02:03 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pWe4G-0000iD-E6 for qemu-devel@nongnu.org; Mon, 27 Feb 2023 09:01:33 -0500 Received: from mail-wr1-x42b.google.com ([2a00:1450:4864:20::42b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pWe4E-0007WC-Qq for qemu-devel@nongnu.org; Mon, 27 Feb 2023 09:01:28 -0500 Received: by mail-wr1-x42b.google.com with SMTP id q16so6349603wrw.2 for ; Mon, 27 Feb 2023 06:01:26 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id s9-20020a5d4249000000b002c5598c14acsm7158514wrr.6.2023.02.27.06.01.25 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Feb 2023 06:01:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=VDLsCaYW69zOK5yA/VohVYicyAoFr83OJm2v2NkJmG4=; b=Z8RRajFTajjarHPlSLuYjskv0irQqL1MoEiJs/ZhS8CCRuMQ8SJIKJXcCTDTfrmCu/ 7yVK44jYkAVA67Dyfco5afdfoCJNfePneuKcklv4hUroRyG4kCa29sXZ1g7Jcm5g+XDo 3djoRlFwW6XPf9nvfd48BLR69E73WF9+KIVzZaLB+jMsqvOIpT6opEmrzUei/rjN84za Ru+tLL9JFdTThfJqNUQBFsQW6dR8WJu/gkh4z7HXNaCCiLBhNMYlwQyYAldK++3cEgli 6J0Rl3rrR54tksVdHYsRczsYcMkxtGHZu0KtvDdC1auGEL753oGMv/CPwtKaACgzAi11 +tyQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=VDLsCaYW69zOK5yA/VohVYicyAoFr83OJm2v2NkJmG4=; b=ZVYTLdh+p2cPp2Xt1mVm4Lxj+qf2hfc6H/5VIWS8/jtMoSXddH1+IIibUq6qIcI9ii t107sKgSYAdzW5MuV6kd1zD5koD6avGTZPxLD2jk8mCJ5JdQbAQa53p9TC6ZB2qmozuA MPvt+hA2RPuDqFSqUXfz9v9vw7ptXXJn3+S9mEHh+V2Z3iinCslW1tP/R70xyh0ju8Ym kaK/oWW1GQFburnzcwuyDipt922oFkWlFj5lCDPhEzbj3EJtQfBzXFjNOhY+YDp1B2sA oGdYuBdDPmRP0dt6bAxl8KdtjJFhp6l67nkT6jW8kKvE51Vc0meVAczoEu4dirB2DBly BzPg== X-Gm-Message-State: AO0yUKWY3A3SpOMWNGe/LUUA374mj2iORbFnapVfBkXQC+fBROG7uWhk G9rJ01xncEIsrR5PPoBI+HGZ9pjRSxK5V/tf X-Google-Smtp-Source: AK7set8Y5yOcOI7cqY8zofkt0ZLFNhTn6DZ7qCOEMTBOfXv7EF4th0WjeYaT5Nya4Mw/qmHX5UD80A== X-Received: by 2002:adf:e887:0:b0:2c7:1c36:3c67 with SMTP id d7-20020adfe887000000b002c71c363c67mr9889631wrm.23.1677506486138; Mon, 27 Feb 2023 06:01:26 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 15/25] hw/char/pl011: Open-code pl011_luminary_create() Date: Mon, 27 Feb 2023 14:00:52 +0000 Message-Id: <20230227140102.3712344-16-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230227140102.3712344-1-peter.maydell@linaro.org> References: <20230227140102.3712344-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1677506588036100001 From: Philippe Mathieu-Daud=C3=A9 pl011_luminary_create() is only used for the Stellaris board, open-code it. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Richard Henderson Message-id: 20230220115114.25237-4-philmd@linaro.org Signed-off-by: Peter Maydell --- include/hw/char/pl011.h | 17 ----------------- hw/arm/stellaris.c | 11 ++++++++--- 2 files changed, 8 insertions(+), 20 deletions(-) diff --git a/include/hw/char/pl011.h b/include/hw/char/pl011.h index d82870c0069..d8538021323 100644 --- a/include/hw/char/pl011.h +++ b/include/hw/char/pl011.h @@ -57,21 +57,4 @@ struct PL011State { =20 DeviceState *pl011_create(hwaddr addr, qemu_irq irq, Chardev *chr); =20 -static inline DeviceState *pl011_luminary_create(hwaddr addr, - qemu_irq irq, - Chardev *chr) -{ - DeviceState *dev; - SysBusDevice *s; - - dev =3D qdev_new("pl011_luminary"); - s =3D SYS_BUS_DEVICE(dev); - qdev_prop_set_chr(dev, "chardev", chr); - sysbus_realize_and_unref(s, &error_fatal); - sysbus_mmio_map(s, 0, addr); - sysbus_connect_irq(s, 0, irq); - - return dev; -} - #endif diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c index 67a2293d35f..f7e99baf623 100644 --- a/hw/arm/stellaris.c +++ b/hw/arm/stellaris.c @@ -1146,9 +1146,14 @@ static void stellaris_init(MachineState *ms, stellar= is_board_info *board) =20 for (i =3D 0; i < 4; i++) { if (board->dc2 & (1 << i)) { - pl011_luminary_create(0x4000c000 + i * 0x1000, - qdev_get_gpio_in(nvic, uart_irq[i]), - serial_hd(i)); + SysBusDevice *sbd; + + dev =3D qdev_new("pl011_luminary"); + sbd =3D SYS_BUS_DEVICE(dev); + qdev_prop_set_chr(dev, "chardev", serial_hd(i)); + sysbus_realize_and_unref(sbd, &error_fatal); + sysbus_mmio_map(sbd, 0, 0x4000c000 + i * 0x1000); + sysbus_connect_irq(sbd, 0, qdev_get_gpio_in(nvic, uart_irq[i])= ); } } if (board->dc2 & (1 << 4)) { --=20 2.34.1 From nobody Tue May 14 10:40:27 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1677506571; cv=none; d=zohomail.com; s=zohoarc; b=QNcDZ2YEewr2nfrS/VPXh7T68QYxXJlUgsQbzzYnGqPGCvwh3Oq5RBJGgO+CLZkC69lzTMDQK648rsBwXAEX4cKV0lpOOUqrJdz5r6vqJIS7p4yklGaahGEFEE0hNUrpF2RVPTpDLtwf8sIs4+XaD3JXQ1l+dxME066WuLkVw9s= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1677506571; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=KlVlw+pS2hFrB7UptmYDw7cy3LLQizZlFOoz6eLzmsM=; b=QrjY+i5nNgJLmN1s1TqKr25FkHkJmFv3dLvDNK9zYoVfRxd026avhqerWmkB9KfQTVADLN2hW/ID07CO7dSO/B+UwSJZrDEk6CIpC7GTK1VTE9OAoWPh2avSOBgVEQJ9lyX3HWFUSZinjoE4y8ID2k22kuX+aciSVSl2ChCBg7w= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1677506571436163.71827404850535; Mon, 27 Feb 2023 06:02:51 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pWe4t-0001Go-Qx; Mon, 27 Feb 2023 09:02:07 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pWe4K-0000lS-C6 for qemu-devel@nongnu.org; Mon, 27 Feb 2023 09:01:34 -0500 Received: from mail-wr1-x42e.google.com ([2a00:1450:4864:20::42e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pWe4H-0007a0-9R for qemu-devel@nongnu.org; Mon, 27 Feb 2023 09:01:30 -0500 Received: by mail-wr1-x42e.google.com with SMTP id bv17so6337274wrb.5 for ; Mon, 27 Feb 2023 06:01:28 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id s9-20020a5d4249000000b002c5598c14acsm7158514wrr.6.2023.02.27.06.01.26 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Feb 2023 06:01:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=KlVlw+pS2hFrB7UptmYDw7cy3LLQizZlFOoz6eLzmsM=; b=cxXGaEndh7+OuX+TZ2yTc+x+y7rL/E4bsZJDXjEvRXtTTLJpdBK7JDx8EkeLx9qGwo nW22qX0VAK18PSNR4hHGKLFe0UaRaM3FQR5lAebRS60jIVwi7vrif47uurlErnwlwtSM aBkVaJrBiNSJWFFJ7fS1AuzJ39NqMID8OWc+levdCR0jbFth3fyuTEfm2zvBfZmagGVl U8WltLxFLSZQPw+4vHHEhkxMXbEPvCINVxUtNG+mBJgnHHJiC7k2eAvXQT1Aj6uqBIRs DUEtbcXTKVQ7GVo/018Pvh4G2u2A+4mjC7IJIBZZQAgoMX+i3lvPyUWgFjqXJ2b6WKhZ 93yg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1677506614919100003 From: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Richard Henderson Message-id: 20230220115114.25237-5-philmd@linaro.org Signed-off-by: Peter Maydell --- include/hw/char/xilinx_uartlite.h | 6 +++++- hw/char/xilinx_uartlite.c | 4 +--- 2 files changed, 6 insertions(+), 4 deletions(-) diff --git a/include/hw/char/xilinx_uartlite.h b/include/hw/char/xilinx_uar= tlite.h index dd09c068019..753d3a453ec 100644 --- a/include/hw/char/xilinx_uartlite.h +++ b/include/hw/char/xilinx_uartlite.h @@ -18,6 +18,10 @@ #include "hw/qdev-properties.h" #include "hw/sysbus.h" #include "qapi/error.h" +#include "qom/object.h" + +#define TYPE_XILINX_UARTLITE "xlnx.xps-uartlite" +OBJECT_DECLARE_SIMPLE_TYPE(XilinxUARTLite, XILINX_UARTLITE) =20 static inline DeviceState *xilinx_uartlite_create(hwaddr addr, qemu_irq irq, @@ -26,7 +30,7 @@ static inline DeviceState *xilinx_uartlite_create(hwaddr = addr, DeviceState *dev; SysBusDevice *s; =20 - dev =3D qdev_new("xlnx.xps-uartlite"); + dev =3D qdev_new(TYPE_XILINX_UARTLITE); s =3D SYS_BUS_DEVICE(dev); qdev_prop_set_chr(dev, "chardev", chr); sysbus_realize_and_unref(s, &error_fatal); diff --git a/hw/char/xilinx_uartlite.c b/hw/char/xilinx_uartlite.c index 99b9a6f851e..180bb97202c 100644 --- a/hw/char/xilinx_uartlite.c +++ b/hw/char/xilinx_uartlite.c @@ -24,6 +24,7 @@ =20 #include "qemu/osdep.h" #include "qemu/log.h" +#include "hw/char/xilinx_uartlite.h" #include "hw/irq.h" #include "hw/qdev-properties.h" #include "hw/qdev-properties-system.h" @@ -53,9 +54,6 @@ #define CONTROL_RST_RX 0x02 #define CONTROL_IE 0x10 =20 -#define TYPE_XILINX_UARTLITE "xlnx.xps-uartlite" -OBJECT_DECLARE_SIMPLE_TYPE(XilinxUARTLite, XILINX_UARTLITE) - struct XilinxUARTLite { SysBusDevice parent_obj; =20 --=20 2.34.1 From nobody Tue May 14 10:40:27 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id s9-20020a5d4249000000b002c5598c14acsm7158514wrr.6.2023.02.27.06.01.27 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Feb 2023 06:01:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=vzsUur0Aw/LlsgsbO3t88OL+32rrRcXjZlMZhRcStSQ=; b=bCdhMYzmUz1147AEbgy2qrIzzG28Smey6nbuTnIM30alPqs1VHkp0TrrP43F4Kw45+ aEEfOeuez71v7ZsOMzpR/5z+m/BpfsJewWLKTyFEvisIjJu+uaNuFs3OsisYqz/IQMyU Im9gkw7XgB3o7zWvcgBXGaTb75au6cY9O6K9w1bpmZaQand5T27C51TfmYJlv2k90EPi s6rK0Gv6Lo2hkQe8+G98yhblmHtZixFO6BAgUfSRLFLb8rvRqrjIDjGs+AaWyE5wQWt9 ij0yY/LEua5TfTkvpyxRi7QJp0MkB/KmUcdbgmebPKsZx+wF48H1No3Qdh1DuaN4w9+p K1XQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=vzsUur0Aw/LlsgsbO3t88OL+32rrRcXjZlMZhRcStSQ=; b=mRYaXa67JFO0s9BEPsV1n7vhH4LQimATD9i2nikb2qRrQPBv2nm4zs8XRHhGfuZniH 8Q1JHiclDMoO4hz4BqtG2ofGVDnQkhLgKUe6TazKGSkawMWsMVeedLRpSlQsXXm3mB+t 8Yp22jK2i+XocExDSo7F+8VZD+wTWDzGsAgC0Ly9+TGXsc8Cca1nO0d7ed6gnubW1tXd k/qR5IvNWJ+qZtrnLOhITKUV8D0H+n8y6UbFS/1RQrIf+qnr2fa4/3mPFv79IwPSUvhi 2Iq7F5R2jateeTeYUyVM6t5ZqcDHFiRevHQ6onAfIm70EGxs7xfcEZmjwACpCnX3uxjZ xT4A== X-Gm-Message-State: AO0yUKU9LjbfbfhiUQvW0LlkvrKdO6RLTau3rolqmZbHNv9ECxZ+F6r3 MnG1EFDV1UdDZXDT8iiQpkWzzecocUGM3UL4 X-Google-Smtp-Source: AK7set/0zSOW0nMh9LHDjyZRxmw7TcDsB+z1UCz/o7Xj245nlmZE8tG/vqd/Trk/S04qu94mDAt73w== X-Received: by 2002:a05:600c:44d4:b0:3eb:2de9:8aed with SMTP id f20-20020a05600c44d400b003eb2de98aedmr7407506wmo.41.1677506488560; Mon, 27 Feb 2023 06:01:28 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 17/25] hw/char/xilinx_uartlite: Open-code xilinx_uartlite_create() Date: Mon, 27 Feb 2023 14:00:54 +0000 Message-Id: <20230227140102.3712344-18-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230227140102.3712344-1-peter.maydell@linaro.org> References: <20230227140102.3712344-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1677506661742100001 From: Philippe Mathieu-Daud=C3=A9 Open-code the single use of xilinx_uartlite_create(). Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Richard Henderson Message-id: 20230220115114.25237-6-philmd@linaro.org Signed-off-by: Peter Maydell --- include/hw/char/xilinx_uartlite.h | 20 -------------------- hw/microblaze/petalogix_s3adsp1800_mmu.c | 7 +++++-- 2 files changed, 5 insertions(+), 22 deletions(-) diff --git a/include/hw/char/xilinx_uartlite.h b/include/hw/char/xilinx_uar= tlite.h index 753d3a453ec..36d4e8444da 100644 --- a/include/hw/char/xilinx_uartlite.h +++ b/include/hw/char/xilinx_uartlite.h @@ -15,29 +15,9 @@ #ifndef XILINX_UARTLITE_H #define XILINX_UARTLITE_H =20 -#include "hw/qdev-properties.h" -#include "hw/sysbus.h" -#include "qapi/error.h" #include "qom/object.h" =20 #define TYPE_XILINX_UARTLITE "xlnx.xps-uartlite" OBJECT_DECLARE_SIMPLE_TYPE(XilinxUARTLite, XILINX_UARTLITE) =20 -static inline DeviceState *xilinx_uartlite_create(hwaddr addr, - qemu_irq irq, - Chardev *chr) -{ - DeviceState *dev; - SysBusDevice *s; - - dev =3D qdev_new(TYPE_XILINX_UARTLITE); - s =3D SYS_BUS_DEVICE(dev); - qdev_prop_set_chr(dev, "chardev", chr); - sysbus_realize_and_unref(s, &error_fatal); - sysbus_mmio_map(s, 0, addr); - sysbus_connect_irq(s, 0, irq); - - return dev; -} - #endif diff --git a/hw/microblaze/petalogix_s3adsp1800_mmu.c b/hw/microblaze/petal= ogix_s3adsp1800_mmu.c index 9d959d1ad80..505639c2980 100644 --- a/hw/microblaze/petalogix_s3adsp1800_mmu.c +++ b/hw/microblaze/petalogix_s3adsp1800_mmu.c @@ -100,8 +100,11 @@ petalogix_s3adsp1800_init(MachineState *machine) irq[i] =3D qdev_get_gpio_in(dev, i); } =20 - xilinx_uartlite_create(UARTLITE_BASEADDR, irq[UARTLITE_IRQ], - serial_hd(0)); + dev =3D qdev_new(TYPE_XILINX_UARTLITE); + qdev_prop_set_chr(dev, "chardev", serial_hd(0)); + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); + sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, UARTLITE_BASEADDR); + sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq[UARTLITE_IRQ]); =20 /* 2 timers at irq 2 @ 62 Mhz. */ dev =3D qdev_new("xlnx.xps-timer"); --=20 2.34.1 From nobody Tue May 14 10:40:27 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1677506673; cv=none; d=zohomail.com; s=zohoarc; b=ZgZIBeqi27L4AyR0E2LFdNS6Bujzg2icc3UVZ8Q/hRpSL3ihbBZ9bMr7SsBT5qZ94ebVN4SOj3d+CJE2ODmmameVJkd1Qa3EKIY0xfiyG5eNgrVEAaYVwGTKZIDTL/jakTbxRkiVCWa+FcuL68usqq2jR71W7toFhk4vws63d+w= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1677506673; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=qm89jNZzQrE8sBPqBWdhslClrvicJCmDVh4kNrz6Gcg=; b=jBzyj0Z1kbWwsHgaxBcLblWOVLo64mSDSGp0quHdbhGZxgEOdjqAjJXBN536E+Lk2pjJxRQnqpTsRXGwDHT4y9Odc2HG0E30RexpAttSb2ZEEPY9Rx2pLCNqg2C10elu1vOGc1jLhwVe3A77i/L1C9v4vKnCOJEoPOBklgDPNtk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1677506673190127.60073310968414; Mon, 27 Feb 2023 06:04:33 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pWe5H-0003Uv-A7; Mon, 27 Feb 2023 09:02:31 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pWe4N-0000lm-7w for qemu-devel@nongnu.org; Mon, 27 Feb 2023 09:01:36 -0500 Received: from mail-wr1-x42d.google.com ([2a00:1450:4864:20::42d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pWe4K-0007c6-5I for qemu-devel@nongnu.org; Mon, 27 Feb 2023 09:01:34 -0500 Received: by mail-wr1-x42d.google.com with SMTP id bt28so6326858wrb.8 for ; Mon, 27 Feb 2023 06:01:31 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id s9-20020a5d4249000000b002c5598c14acsm7158514wrr.6.2023.02.27.06.01.28 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Feb 2023 06:01:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=qm89jNZzQrE8sBPqBWdhslClrvicJCmDVh4kNrz6Gcg=; b=D7CntBw7raCyyiA7qN+bhq/iWLoOdtJHd5z1WsXKP/AWlUWHlj85IvtYz53rrV2tJ2 ZsQRXZBsnWBZ0EtCBIokjtAo+Cul0iJYKa2pCgzeziFv8epzD5UsQT4Qrb7MAUHBjM9k M7xP1lV0cQLgx2qgttmncy/DdtTGAI1XJDGcPF0VC24E618BiBYhrCvwItGmmxqr1Of6 I04fAA7wWeQo0+F49LUIw0fJ5epJKQwP6TVChoY8tD0o8zCFROHKwVYZGP3KXsvoHZp8 4PPJfEbVi3mSJMWxqB3e836LEX5PrSSf5Xvb6POuQw2jcVuYICcxWwhv0Fhr01R/TClE 2wFw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=qm89jNZzQrE8sBPqBWdhslClrvicJCmDVh4kNrz6Gcg=; b=rstdMuRySFaBWq56cLEee0EM/4DwIrooKXzSPtFaW56on49LXohV+kLgcCWFRib1+B KP1wCIO+EJ51lvMGuIWd1mXvX5+zFZQ31gNHiMVCeQcKNPnSECKySdxc+l1llcwW4s36 6ykJ0f3gVn4JAUYD46DeS4cjkgpgIDy3C87QCb//WkxOBv7ueHTFqTMp3CFDqwNAfk2q RROwIqYX9kREKZ/uApUWJXGSTAT1MQ40PT+CIipTPyj6LwGY30Y42YjCezYmeQlEVFqr JHUMaXOkXVv6KuydSDPXC5qIjPTNhZMSl5r0iqPjmLbn4h+Gi7cq5EWmHZvLIq+YQALq DcYA== X-Gm-Message-State: AO0yUKXMl5Yplq62X0HghOfIPRPH6s72ejREjpMqmx1phRU60gB9cxdy IeAoKI7y5WO5w0T7YiOB2ip0yIZZtNC6tA/4 X-Google-Smtp-Source: AK7set/ks4AhZBlvUYlUVcauH8CtwY+3s61cmuq3ZIwzwljaepzfuiOTGkBN8jwFhw/gggZCvgh4ug== X-Received: by 2002:a5d:60ca:0:b0:2c7:e909:5fcf with SMTP id x10-20020a5d60ca000000b002c7e9095fcfmr8141292wrt.3.1677506489697; Mon, 27 Feb 2023 06:01:29 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 18/25] hw/char/cmsdk-apb-uart: Open-code cmsdk_apb_uart_create() Date: Mon, 27 Feb 2023 14:00:55 +0000 Message-Id: <20230227140102.3712344-19-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230227140102.3712344-1-peter.maydell@linaro.org> References: <20230227140102.3712344-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1677506721452100001 From: Philippe Mathieu-Daud=C3=A9 cmsdk_apb_uart_create() is only used twice in the same file. Open-code it. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Peter Maydell Message-id: 20230220115114.25237-7-philmd@linaro.org Signed-off-by: Peter Maydell --- include/hw/char/cmsdk-apb-uart.h | 34 -------------------------- hw/arm/mps2.c | 41 +++++++++++++++++++++----------- 2 files changed, 27 insertions(+), 48 deletions(-) diff --git a/include/hw/char/cmsdk-apb-uart.h b/include/hw/char/cmsdk-apb-u= art.h index 64b0a3d5345..7de8f8d1b94 100644 --- a/include/hw/char/cmsdk-apb-uart.h +++ b/include/hw/char/cmsdk-apb-uart.h @@ -12,10 +12,8 @@ #ifndef CMSDK_APB_UART_H #define CMSDK_APB_UART_H =20 -#include "hw/qdev-properties.h" #include "hw/sysbus.h" #include "chardev/char-fe.h" -#include "qapi/error.h" #include "qom/object.h" =20 #define TYPE_CMSDK_APB_UART "cmsdk-apb-uart" @@ -45,36 +43,4 @@ struct CMSDKAPBUART { uint8_t rxbuf; }; =20 -/** - * cmsdk_apb_uart_create - convenience function to create TYPE_CMSDK_APB_U= ART - * @addr: location in system memory to map registers - * @chr: Chardev backend to connect UART to, or NULL if no backend - * @pclk_frq: frequency in Hz of the PCLK clock (used for calculating baud= rate) - */ -static inline DeviceState *cmsdk_apb_uart_create(hwaddr addr, - qemu_irq txint, - qemu_irq rxint, - qemu_irq txovrint, - qemu_irq rxovrint, - qemu_irq uartint, - Chardev *chr, - uint32_t pclk_frq) -{ - DeviceState *dev; - SysBusDevice *s; - - dev =3D qdev_new(TYPE_CMSDK_APB_UART); - s =3D SYS_BUS_DEVICE(dev); - qdev_prop_set_chr(dev, "chardev", chr); - qdev_prop_set_uint32(dev, "pclk-frq", pclk_frq); - sysbus_realize_and_unref(s, &error_fatal); - sysbus_mmio_map(s, 0, addr); - sysbus_connect_irq(s, 0, txint); - sysbus_connect_irq(s, 1, rxint); - sysbus_connect_irq(s, 2, txovrint); - sysbus_connect_irq(s, 3, rxovrint); - sysbus_connect_irq(s, 4, uartint); - return dev; -} - #endif diff --git a/hw/arm/mps2.c b/hw/arm/mps2.c index a86a994dbac..d92fd60684c 100644 --- a/hw/arm/mps2.c +++ b/hw/arm/mps2.c @@ -35,6 +35,7 @@ #include "hw/boards.h" #include "exec/address-spaces.h" #include "sysemu/sysemu.h" +#include "hw/qdev-properties.h" #include "hw/misc/unimp.h" #include "hw/char/cmsdk-apb-uart.h" #include "hw/timer/cmsdk-apb-timer.h" @@ -282,6 +283,9 @@ static void mps2_common_init(MachineState *machine) qdev_connect_gpio_out(orgate_dev, 0, qdev_get_gpio_in(armv7m, 12)); =20 for (i =3D 0; i < 5; i++) { + DeviceState *dev; + SysBusDevice *s; + static const hwaddr uartbase[] =3D {0x40004000, 0x40005000, 0x40006000, 0x40007000, 0x40009000}; @@ -294,12 +298,16 @@ static void mps2_common_init(MachineState *machine) rxovrint =3D qdev_get_gpio_in(orgate_dev, i * 2 + 1); } =20 - cmsdk_apb_uart_create(uartbase[i], - qdev_get_gpio_in(armv7m, uartirq[i] + 1), - qdev_get_gpio_in(armv7m, uartirq[i]), - txovrint, rxovrint, - NULL, - serial_hd(i), SYSCLK_FRQ); + dev =3D qdev_new(TYPE_CMSDK_APB_UART); + s =3D SYS_BUS_DEVICE(dev); + qdev_prop_set_chr(dev, "chardev", serial_hd(i)); + qdev_prop_set_uint32(dev, "pclk-frq", SYSCLK_FRQ); + sysbus_realize_and_unref(s, &error_fatal); + sysbus_mmio_map(s, 0, uartbase[i]); + sysbus_connect_irq(s, 0, qdev_get_gpio_in(armv7m, uartirq[i] += 1)); + sysbus_connect_irq(s, 1, qdev_get_gpio_in(armv7m, uartirq[i])); + sysbus_connect_irq(s, 2, txovrint); + sysbus_connect_irq(s, 3, rxovrint); } break; } @@ -324,7 +332,8 @@ static void mps2_common_init(MachineState *machine) 0x4002c000, 0x4002d000, 0x4002e000}; Object *txrx_orgate; - DeviceState *txrx_orgate_dev; + DeviceState *txrx_orgate_dev, *dev; + SysBusDevice *s; =20 txrx_orgate =3D object_new(TYPE_OR_IRQ); object_property_set_int(txrx_orgate, "num-lines", 2, &error_fa= tal); @@ -332,13 +341,17 @@ static void mps2_common_init(MachineState *machine) txrx_orgate_dev =3D DEVICE(txrx_orgate); qdev_connect_gpio_out(txrx_orgate_dev, 0, qdev_get_gpio_in(armv7m, uart_txrx_irqno= [i])); - cmsdk_apb_uart_create(uartbase[i], - qdev_get_gpio_in(txrx_orgate_dev, 0), - qdev_get_gpio_in(txrx_orgate_dev, 1), - qdev_get_gpio_in(orgate_dev, i * 2), - qdev_get_gpio_in(orgate_dev, i * 2 + 1), - NULL, - serial_hd(i), SYSCLK_FRQ); + + dev =3D qdev_new(TYPE_CMSDK_APB_UART); + s =3D SYS_BUS_DEVICE(dev); + qdev_prop_set_chr(dev, "chardev", serial_hd(i)); + qdev_prop_set_uint32(dev, "pclk-frq", SYSCLK_FRQ); + sysbus_realize_and_unref(s, &error_fatal); + sysbus_mmio_map(s, 0, uartbase[i]); + sysbus_connect_irq(s, 0, qdev_get_gpio_in(txrx_orgate_dev, 0)); + sysbus_connect_irq(s, 1, qdev_get_gpio_in(txrx_orgate_dev, 1)); + sysbus_connect_irq(s, 2, qdev_get_gpio_in(orgate_dev, i * 2)); + sysbus_connect_irq(s, 3, qdev_get_gpio_in(orgate_dev, i * 2 + = 1)); } break; } --=20 2.34.1 From nobody Tue May 14 10:40:27 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1677506882; cv=none; d=zohomail.com; s=zohoarc; b=A4vzEeXg5CSWn8lOpR5bQ/BO5VcSwIAocPlR14xsDts2FPIsa+Fks+UzxN+Up94nSU1hzLSFQ7F/v3gKnW87uRexka9cbeT+NhM/eKPzbZudD8wA2+cx5JhYZdouFQpxGlHgHIVmhx2XK/8hjU9tOArUPGRpQrCGAck1UGA5Jdk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1677506882; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, TVD_SPACE_RATIO=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1677506884495100001 From: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Alex Benn=C3=A9e Message-id: 20230220115114.25237-8-philmd@linaro.org Signed-off-by: Peter Maydell --- include/hw/timer/cmsdk-apb-timer.h | 1 - 1 file changed, 1 deletion(-) diff --git a/include/hw/timer/cmsdk-apb-timer.h b/include/hw/timer/cmsdk-ap= b-timer.h index c4c7eae8499..2dd615d1be9 100644 --- a/include/hw/timer/cmsdk-apb-timer.h +++ b/include/hw/timer/cmsdk-apb-timer.h @@ -12,7 +12,6 @@ #ifndef CMSDK_APB_TIMER_H #define CMSDK_APB_TIMER_H =20 -#include "hw/qdev-properties.h" #include "hw/sysbus.h" #include "hw/ptimer.h" #include "hw/clock.h" --=20 2.34.1 From nobody Tue May 14 10:40:27 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id s9-20020a5d4249000000b002c5598c14acsm7158514wrr.6.2023.02.27.06.01.30 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Feb 2023 06:01:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=a/LUrffyQW57nzfvUKYl3CFpJsURKsL4yXJqSOTnUyw=; b=iY7AT3Aq+MFTlX/QpmZBttEhj4wTBY4adRx3cneP7IomS5z1VebshN8SHmQWuCqZ2l lzPy82vnt8hn4eDv6N1VkvkYAg8mn8H8PYJcwUTs4DNP+kc/NIG2Uq1PPumWSJ/flWNR JNR9KiwNs1LzZ/yOEF4fk+tpAv0qtKf1cEJHRq8R5byUH0ZMuGxy+ou7zpXqRN282Csq n3QJY6SttMKbwvhsvjyT1B5qbJ1lU8pwSL9F0l2PRwCR1HzMqzL5eUUEV67s+M6Cjbbz W416pKRG1n6C5Gz4Ve1coUYow1yMdEcH4lcyf1wzmFxkF420hAbMflVONDI3zWhKON19 nXZA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=a/LUrffyQW57nzfvUKYl3CFpJsURKsL4yXJqSOTnUyw=; b=MTJXsDu2LcBes0cIDVSccGvZSxkSR9oJLSScq1axB/1uZsS9MPBoK5/9qx60IvcoAR XtcVKIOJXlo+w6Tn0sJEo+4AnuQdjVKPr8/+E+xE/ZMFYLJMadVfkiOyLcFe9UoonSPN LCSWk/3Y4nBVKGTiMp3zqzEFnMsritPafo7a5HPGPotT4aLzO/RCQJIE83EVeVp0Ve9U 9wwfuGwuyl+xXi7qlZCZeNymB1DCpqJz1qzzD8tVHsKB8E3ZQorIwVPEaKmGT4bmv1U6 iQrbPuyvjAjoLkLhulA5bcpG11UF0vulb/YbJ00AsQnyPLwOy+qIOsak1yYV1cfLtZFj KzWw== X-Gm-Message-State: AO0yUKU/D8/dvrIJCFH9x3KfANw/9rbpj4e8myB/3UsAVlIX6NjpweaF xKCjALKl6ZJ+8rE3bdD8PVnRidZ4d+ktlJXU X-Google-Smtp-Source: AK7set/YZ43CJ8DyAKyth9/JrwvpF0DP70wdHrSvCJ+c0fLwajYt5z+oa0kU5rhBpbZkHUgQ7oSaLA== X-Received: by 2002:adf:f1c1:0:b0:2c5:598c:14b0 with SMTP id z1-20020adff1c1000000b002c5598c14b0mr20196526wro.20.1677506492100; Mon, 27 Feb 2023 06:01:32 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 20/25] hw/intc/armv7m_nvic: Use QOM cast CPU() macro Date: Mon, 27 Feb 2023 14:00:57 +0000 Message-Id: <20230227140102.3712344-21-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230227140102.3712344-1-peter.maydell@linaro.org> References: <20230227140102.3712344-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1677507359762100001 From: Philippe Mathieu-Daud=C3=A9 Avoid accessing 'parent_obj' directly. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Alex Benn=C3=A9e Message-id: 20230220115114.25237-9-philmd@linaro.org Signed-off-by: Peter Maydell --- hw/intc/armv7m_nvic.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index 8e289051a40..63afe1fdf58 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -578,7 +578,7 @@ static void do_armv7m_nvic_set_pending(void *opaque, in= t irq, bool secure, * which saves having to have an extra argument is_terminal * that we'd only use in one place. */ - cpu_abort(&s->cpu->parent_obj, + cpu_abort(CPU(s->cpu), "Lockup: can't take terminal derived exception " "(original exception priority %d)\n", s->vectpending_prio); @@ -644,7 +644,7 @@ static void do_armv7m_nvic_set_pending(void *opaque, in= t irq, bool secure, * Lockup condition due to a guest bug. We don't model * Lockup, so report via cpu_abort() instead. */ - cpu_abort(&s->cpu->parent_obj, + cpu_abort(CPU(s->cpu), "Lockup: can't escalate %d to HardFault " "(current priority %d)\n", irq, running); } @@ -742,7 +742,7 @@ void armv7m_nvic_set_pending_lazyfp(NVICState *s, int i= rq, bool secure) * We want to escalate to HardFault but the context the * FP state belongs to prevents the exception pre-empting. */ - cpu_abort(&s->cpu->parent_obj, + cpu_abort(CPU(s->cpu), "Lockup: can't escalate to HardFault during " "lazy FP register stacking\n"); } --=20 2.34.1 From nobody Tue May 14 10:40:27 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1677508265; cv=none; d=zohomail.com; s=zohoarc; b=GWjfomAE3uOPpMuFoqzQ62NMIEanEp8GQu7uFJ+c7zNPLDFn14GqcbkqWnpcELM4U56+RK9NDoU22WxijNqxIjW1Z8Ls3iBdWZ4J0DJ4d+Mswmqp83xTKvlWDabPyfhHaIxwMLVMxnS9qs1Zk1U4mNv8W0eTOu7SMDqb5TXQ13o= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1677508265; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=s3p4BYVS0fXofW3OGu8iWGz+dlE7VopRg+VENQUXfKg=; b=PzmbHkMcwSQ0nQ7qoAGWbqax0IR0WJDhJzvJKVEAyJDInM2biL3JfhvewJqA7KGvmSaRA6f5EpVY6sJ5KGWQ0wD3rrgPvouLX8A3GSr2WammLZHFfr4tYVKMeJGPjcQzj/mE6VMHIoJ515bmBFXaBBHRPwyHaPPjwuE7Tg7TH/E= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1677508265511519.3818678628138; Mon, 27 Feb 2023 06:31:05 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pWe5I-0003mo-U0; Mon, 27 Feb 2023 09:02:33 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pWe4P-0000o6-Kh for qemu-devel@nongnu.org; Mon, 27 Feb 2023 09:01:42 -0500 Received: from mail-lf1-x136.google.com ([2a00:1450:4864:20::136]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pWe4N-0007dh-Uo for qemu-devel@nongnu.org; Mon, 27 Feb 2023 09:01:37 -0500 Received: by mail-lf1-x136.google.com with SMTP id s22so8642071lfi.9 for ; Mon, 27 Feb 2023 06:01:35 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id s9-20020a5d4249000000b002c5598c14acsm7158514wrr.6.2023.02.27.06.01.32 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Feb 2023 06:01:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=s3p4BYVS0fXofW3OGu8iWGz+dlE7VopRg+VENQUXfKg=; b=Vn1OL1xDJJy/CCs7G1bkkFkMBB+lGrlM4TzYq2N+XuwO1rct9INP4clQJmUfDubxeH frLuHbhUCiWhGCalrTV7mSYBfMXq8E6IGVdTtNLHTxY/Uhhqs3P8rCLhbp5SLMvje2VU RnrVuVxdWQkZ9TElNNWUa5XoqwHEtSxobInn55wgUfPsImtQqvw9ydW/6FFJ/2u8317F nK3l8GLuHKV9/eOaG8n4XvfqSHgrpTNepn4k0W79KLpLyw4iSNkIokr0X9Wrb41lNtvT Fup2RtJ/AWbQ8rp6M4ZmGDZx4S3x4IYfrTWqVDInoWuL2jV0Pv4GD7xWaMlTkAHxY19l 6j0A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::136; envelope-from=peter.maydell@linaro.org; helo=mail-lf1-x136.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1677508267826100001 From: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Signed-off-by: Peter Maydell --- hw/arm/musicpal.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/hw/arm/musicpal.c b/hw/arm/musicpal.c index 89b66606c32..06d9add7c72 100644 --- a/hw/arm/musicpal.c +++ b/hw/arm/musicpal.c @@ -1072,7 +1072,6 @@ struct musicpal_key_state { SysBusDevice parent_obj; /*< public >*/ =20 - MemoryRegion iomem; uint32_t kbd_extended; uint32_t pressed_keys; qemu_irq out[8]; @@ -1161,9 +1160,6 @@ static void musicpal_key_init(Object *obj) DeviceState *dev =3D DEVICE(sbd); musicpal_key_state *s =3D MUSICPAL_KEY(dev); =20 - memory_region_init(&s->iomem, obj, "dummy", 0); - sysbus_init_mmio(sbd, &s->iomem); - s->kbd_extended =3D 0; s->pressed_keys =3D 0; =20 --=20 2.34.1 From nobody Tue May 14 10:40:27 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1677506902; cv=none; d=zohomail.com; s=zohoarc; b=gFwRIfZKZaA89DkkBvcfnOQtuhvb+Bc0MtCzcnpm0e5/N25cbVmBIKFj5EI3wXk+O652rbTME7MjdvIfF5xf/gFoM759Po49Mu0JlRFN5YrgQd24ZiG1bRe1f8zDtYq8l3f8EjVVVlKqB9ko8XmEv06D3WQN1TKQh7SBujZ5Vns= ARC-Message-Signature: i=1; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id s9-20020a5d4249000000b002c5598c14acsm7158514wrr.6.2023.02.27.06.01.33 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Feb 2023 06:01:33 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=eMvi4KhirUzuoIPRZhoENemFll4CeurZVpqkoOYKjcs=; b=tyUSwV3/PCCXvaHAcHhrUDAbn/V97nEHaHd3imUbBajQm3TxP+PscISkVuBpJzI0hO MPYiuu8+L6ShtIf97bRFzz8BHNZ6lU9ekHAW+bSjQC3lYbiAdfAhXIPqKzGCxKfFWMpO GPDoH5JWSZBdADo/G0QqGcm3gBv659ya1MnH8VlioKyXOdqtWTX2iuBDImlG4uhfiz8X S+TAQ0asRIMjusaimquGDCOGXBSAm48zBo5XE26s3yiH2uZwSI5aQ4shA2YrjLa5kgAr m2YhiBGKueWO13HrOrDkcAp+6/yXB1KVbrwFQ+ZEPbbwnctNUhxK+JEa4A2VoWyof6FG ZGJw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=eMvi4KhirUzuoIPRZhoENemFll4CeurZVpqkoOYKjcs=; b=2judL8hsvjs6XbkzsHmEf7lMJfKJ09+0mr5I4BfkOAD16RImECXErs+fEUSE6iBM9q 2TtXnFPOz7dRwpPPd/LSYn+5xTI18S2HEdSAyzgyiZ7P1/92TPpoppGLSMaIB5mTHp4V L8+9cYUsW8X1OZhRz9D/PRZlQiqWvx9PfvgxBW4KLWxSeUVLHvNnO2PI6oFXLMW4munn wZC+tl9GQ0azwVACHhgaEDyl0XG7ABH2B76GMOal5ri2H+IP8HLfdT5O4Q+HVG+UeYA0 Hvp7s/NhoCxb30J6e2ra7k3xRzyNPHIHEaOJ7IZVEb61biTjeLY4iOgMUghN9+No8Wij pjlA== X-Gm-Message-State: AO0yUKXLs+YXSnXAaQnVDfWQPhXmiIKZQTH6+q1wKzMg+fO743h6v/Bc 0XQ4gKMvpyIKACa/ctfgI5/UB4S2Cu8dRwA3 X-Google-Smtp-Source: AK7set9+tT21/jvoil/DWXhbJDQg7zEBhvejo/sSx55qdyO1hWZ4q2GDg7nyEyt5K6E6M1Oi4nBmqw== X-Received: by 2002:a5d:66c3:0:b0:2c9:79f4:101f with SMTP id k3-20020a5d66c3000000b002c979f4101fmr6247404wrw.34.1677506494660; Mon, 27 Feb 2023 06:01:34 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 22/25] iothread: Remove unused IOThreadClass / IOTHREAD_CLASS Date: Mon, 27 Feb 2023 14:00:59 +0000 Message-Id: <20230227140102.3712344-23-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230227140102.3712344-1-peter.maydell@linaro.org> References: <20230227140102.3712344-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1677506902572100005 From: Philippe Mathieu-Daud=C3=A9 Since commit be8d853766 ("iothread: add I/O thread object") we never used IOThreadClass / IOTHREAD_CLASS() / IOTHREAD_GET_CLASS(), remove these definitions. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Stefan Hajnoczi Reviewed-by: Alistair Francis Message-id: 20230113200138.52869-2-philmd@linaro.org Signed-off-by: Peter Maydell --- iothread.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/iothread.c b/iothread.c index 3862a644712..b41c305bd96 100644 --- a/iothread.c +++ b/iothread.c @@ -25,10 +25,6 @@ #include "qemu/rcu.h" #include "qemu/main-loop.h" =20 -typedef ObjectClass IOThreadClass; - -DECLARE_CLASS_CHECKERS(IOThreadClass, IOTHREAD, - TYPE_IOTHREAD) =20 #ifdef CONFIG_POSIX /* Benchmark results from 2016 on NVMe SSD drives show max polling times a= round --=20 2.34.1 From nobody Tue May 14 10:40:27 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1677506632; cv=none; d=zohomail.com; s=zohoarc; b=H6fR5irVmDI6wJcslvrcyyvJT/zQiqhcPq6BwpSeKlju888TNggcl8defSH9zxmRlfH9M67pCNgHKp0CNLO//QstS+VyMV0yDwBXgcaWnTmrIlv2CpS1emok790iM4DOkcz5aaeskstRV57IEgfgAZhikLD7Kljrh98kfVEcB3s= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1677506632; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=ABw6Fx7bvROh29XWw3RjhC64oEfI8tf4qJj38BnQL70=; b=gSuGn792VsKbBJOokXyB93XYayAHrUFrXNtRV/0eV3mzs6l8eUSjwS6RG2/4KR+LEvc6OseNk+9OxLQ0c2pZTMyrFWyGKKx4Gs0ODlbcSS8wgB1scmr3bbdVcImdIDTyCYZYEpcezkVsOBiRVqU1y7V2ao/UcuMovGp9Vfmu6BY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1677506631992334.283878294174; Mon, 27 Feb 2023 06:03:51 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pWe55-000234-75; Mon, 27 Feb 2023 09:02:19 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pWe4R-0000pi-2E for qemu-devel@nongnu.org; Mon, 27 Feb 2023 09:01:46 -0500 Received: from mail-wm1-x32a.google.com ([2a00:1450:4864:20::32a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pWe4O-0007at-PT for qemu-devel@nongnu.org; Mon, 27 Feb 2023 09:01:38 -0500 Received: by mail-wm1-x32a.google.com with SMTP id j19-20020a05600c1c1300b003e9b564fae9so7244782wms.2 for ; Mon, 27 Feb 2023 06:01:36 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id s9-20020a5d4249000000b002c5598c14acsm7158514wrr.6.2023.02.27.06.01.34 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Feb 2023 06:01:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=ABw6Fx7bvROh29XWw3RjhC64oEfI8tf4qJj38BnQL70=; b=IHNhWW1nPJp1x+JsdMTC/DS7cfoXtSfW9EulLFGyKR4XXpZNqI+A93av3I75VEqM3l cBQF9j6ph3eYwapXxt8W+X4u6Ssg6aoxklXy+WB6SdVNb3cTYEBNvOEEJrZHyigg7Pwp wanz4klSsKLag6vnqE7P7CHw8eAG6I+H9MaiR00i+Wiw9Tu3PWnhqLHJota8b5QNv+eF QdTWeu737K8DjQEgqz78kFbfg1e8LxAc/6HBkvaSS6FuuOx6o+pnDHAycgp0T6cBKwHu 1pYY6akByTti6pA+vXZNPuVOnSwPqcC5euuTq4L0JiXS1zDgjTBTcCdWDUIU79WVNbRk xCPQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ABw6Fx7bvROh29XWw3RjhC64oEfI8tf4qJj38BnQL70=; b=RgEYVgXJJM79NCayFNmsIZ7sYNHwJwxkjDVWbycmsbiTyySyEpdfie7JJEDWhPnVbz 7Z5VXyIqkmb35YtSQ40jILSjPLGykUOR+dhhde4Bldxi/xVVQgI+rJKwFLlh8RYz1t0K hSRICqQ8cROQCNPJnwak8pqeptbI3YuDAfg4ITw2n+PNz0JSu8rvrF6zHycF2oaD56JD k9W25yfrzMJX1sJTK0aj9WytgyvxjaL5LPntJaDoQjwWjba63JOCMEsq3TgCd9kOqeau Y1yaZ0wkkZejfouXcSkJdc9DnAQGNVoj2WE0i7kKeMns4y+wpR/lcQqGon2ps8esIeWX njyg== X-Gm-Message-State: AO0yUKXeeDVWep1zlHWaF1eS3juWXKE/QSDbSQsPjYH//qsE/HeSuv95 bcbvSu9oPgOfdzCwoHGPCgxJERisW/BfgorJ X-Google-Smtp-Source: AK7set+pdo75a2l0qAnuSMecCvVsrjxvW1YpT2f9HtjY0rIjoExpNas/NurZ0lA8sg6dojDDeJxYCA== X-Received: by 2002:a05:600c:1616:b0:3eb:383c:187d with SMTP id m22-20020a05600c161600b003eb383c187dmr5457148wmn.27.1677506495931; Mon, 27 Feb 2023 06:01:35 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 23/25] hw/irq: Declare QOM macros using OBJECT_DECLARE_SIMPLE_TYPE() Date: Mon, 27 Feb 2023 14:01:00 +0000 Message-Id: <20230227140102.3712344-24-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230227140102.3712344-1-peter.maydell@linaro.org> References: <20230227140102.3712344-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1677506682371100001 From: Philippe Mathieu-Daud=C3=A9 QOM *DECLARE* macros expect a typedef as first argument, not a structure. Replace 'struct IRQState' by 'IRQState' to avoid when modifying the macros: ../hw/core/irq.c:29:1: error: declaration of anonymous struct must be a d= efinition DECLARE_INSTANCE_CHECKER(struct IRQState, IRQ, ^ Use OBJECT_DECLARE_SIMPLE_TYPE instead of DECLARE_INSTANCE_CHECKER. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Stefan Hajnoczi Reviewed-by: Alistair Francis Message-id: 20230113200138.52869-3-philmd@linaro.org Signed-off-by: Peter Maydell --- hw/core/irq.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/hw/core/irq.c b/hw/core/irq.c index 3623f711fe6..3f14e2dda74 100644 --- a/hw/core/irq.c +++ b/hw/core/irq.c @@ -26,8 +26,7 @@ #include "hw/irq.h" #include "qom/object.h" =20 -DECLARE_INSTANCE_CHECKER(struct IRQState, IRQ, - TYPE_IRQ) +OBJECT_DECLARE_SIMPLE_TYPE(IRQState, IRQ) =20 struct IRQState { Object parent_obj; @@ -68,7 +67,7 @@ qemu_irq *qemu_allocate_irqs(qemu_irq_handler handler, vo= id *opaque, int n) =20 qemu_irq qemu_allocate_irq(qemu_irq_handler handler, void *opaque, int n) { - struct IRQState *irq; + IRQState *irq; =20 irq =3D IRQ(object_new(TYPE_IRQ)); irq->handler =3D handler; @@ -94,7 +93,7 @@ void qemu_free_irq(qemu_irq irq) =20 static void qemu_notirq(void *opaque, int line, int level) { - struct IRQState *irq =3D opaque; + IRQState *irq =3D opaque; =20 irq->handler(irq->opaque, irq->n, !level); } @@ -120,7 +119,7 @@ void qemu_irq_intercept_in(qemu_irq *gpio_in, qemu_irq_= handler handler, int n) static const TypeInfo irq_type_info =3D { .name =3D TYPE_IRQ, .parent =3D TYPE_OBJECT, - .instance_size =3D sizeof(struct IRQState), + .instance_size =3D sizeof(IRQState), }; =20 static void irq_register_types(void) --=20 2.34.1 From nobody Tue May 14 10:40:27 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1677507182; cv=none; d=zohomail.com; s=zohoarc; b=j4WxRcIR7XHs8s4riE4Df/cGGtpvSpFHCp0vYPI3VwRSqkofLbWSyfjpDGgLPgisirRX+XN70RGZvRaFUH/W4j0X2q8eqm/Ru7gR5uLVrb+GsxW3E5j+x4Df105iPuJoROlIcE72D2O1EZ5MO8mCN1gabAOVZLx6+F/34WasLnE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1677507182; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=UjsmPr4NI1xBRDaPfLgfuSMFB/tmuf/54srjtmPP27c=; b=DJZQvVPWc2bAhWWnFgrzFBJkAjd5YliX+tDulLcEeM5XrTD48dQmDmBqjDXRKnztqvFtZmOd51xUBSR/o11bBnquErU40likSUKp/7CPcXt37iKcH2Ur4z8MfPjWkp71Ugde3N+62n2iHJLzhLtJ7Y6Hsfrp/vIsXsjqcu/+rco= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 16775071822101017.428328039032; Mon, 27 Feb 2023 06:13:02 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pWe5K-0003vF-9f; Mon, 27 Feb 2023 09:02:34 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pWe4S-0000px-Oi for qemu-devel@nongnu.org; Mon, 27 Feb 2023 09:01:46 -0500 Received: from mail-wr1-x436.google.com ([2a00:1450:4864:20::436]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pWe4P-0007WH-M9 for qemu-devel@nongnu.org; Mon, 27 Feb 2023 09:01:39 -0500 Received: by mail-wr1-x436.google.com with SMTP id bx12so3175870wrb.11 for ; Mon, 27 Feb 2023 06:01:37 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id s9-20020a5d4249000000b002c5598c14acsm7158514wrr.6.2023.02.27.06.01.36 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Feb 2023 06:01:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=UjsmPr4NI1xBRDaPfLgfuSMFB/tmuf/54srjtmPP27c=; b=EhnD367YwV75/gp9l5edA72NTiWkJlJR4DFKmtpXOPN+GRxXwLE+tvYxqExQb7GQ0k //yqcFdMrHIgztELWGcQCrhrLQWv3zHJ4rdHZ+LeoT7bumAS/rOiZ8IHpVG8b4n6znlI ziXhwrXXTmPcZ2AjYbsmrwEOHnmmeYZN9LBNs3KUhKtO/7IOQMxfiWgzyWVerLtHJz5y 3Kl8pm9YKbrXa4NZCCv8U8+hNL0bg8gmJr1vq0s66TPq/hgTScgzUTgSrnmFrDoaLU1J 5JvA4YgxfMDo5aM/nRE50IgrOyvQUu7ls8usa6KgTX6sVm+7Q8I5oY8uqvBqzII2TW8e 0ogA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=UjsmPr4NI1xBRDaPfLgfuSMFB/tmuf/54srjtmPP27c=; b=ZhmWCic+h2zN0QSeSFHrUdHztcbyuwX+BpC9FTmIeHHZoS8CNtwsK9P8V/yl7rOE1w dr505hrlwwuvpsMfdRw8noLUhhyeS02j21nIAKn0ulR4bUxRKZOerZ4fhB5U7dOqY6xi /bbIZ2CgXurvaaSQR2tSDwt4MzzrBKfClBOPHdDI8HcbAZ0YCqv9qwxxJe1lBgaBplLv yXl8vtqfUCY1aDvjZyGud7KpQNciJTe17p/7AHVTU+Ck9trpCK6ixrfvvg1sFA7eee5F yW8MAgeoufagbiGrHEFhq+XVOcoJk4G3xo/7Q0v7a2DttjLGmIWKvGF0RQ0TOZEk6cX0 Gjdw== X-Gm-Message-State: AO0yUKUlZezSpPxagcq+y5swp972EvGIVVYrY9FRRi7baZYpU5eru+o0 lIuRD+sP4IN1fhzcZbqWqkUI7iwPXSrwIrSj X-Google-Smtp-Source: AK7set8I1THzidQ+SjLUP21UWvJUl+tRVDlMc5kLeIFWBWD+LirIY0f1aRgi7iFYx1fxhnYKUJGmVg== X-Received: by 2002:a5d:6e88:0:b0:2cc:1935:1ae8 with SMTP id k8-20020a5d6e88000000b002cc19351ae8mr1972459wrz.47.1677506496973; Mon, 27 Feb 2023 06:01:36 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 24/25] hw/or-irq: Declare QOM macros using OBJECT_DECLARE_SIMPLE_TYPE() Date: Mon, 27 Feb 2023 14:01:01 +0000 Message-Id: <20230227140102.3712344-25-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230227140102.3712344-1-peter.maydell@linaro.org> References: <20230227140102.3712344-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1677507183042100003 From: Philippe Mathieu-Daud=C3=A9 Missed during automatic conversion from commit 8063396bf3 ("Use OBJECT_DECLARE_SIMPLE_TYPE when possible"). Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Stefan Hajnoczi Reviewed-by: Alistair Francis Message-id: 20230113200138.52869-4-philmd@linaro.org Signed-off-by: Peter Maydell --- include/hw/or-irq.h | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/include/hw/or-irq.h b/include/hw/or-irq.h index f2f0a273810..131abc2e0c7 100644 --- a/include/hw/or-irq.h +++ b/include/hw/or-irq.h @@ -37,8 +37,7 @@ =20 typedef struct OrIRQState qemu_or_irq; =20 -DECLARE_INSTANCE_CHECKER(qemu_or_irq, OR_IRQ, - TYPE_OR_IRQ) +OBJECT_DECLARE_SIMPLE_TYPE(OrIRQState, OR_IRQ) =20 struct OrIRQState { DeviceState parent_obj; --=20 2.34.1 From nobody Tue May 14 10:40:27 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1677506709; cv=none; d=zohomail.com; s=zohoarc; b=Ihqnx1XmPSdenyglaDgV3vkg1j1opCnHF4YEMObTD8kmyTHxAQyMzzhhFgvvj9LFTdJR5CXyMpVLhLxP+h+acLB/L5D8FYhS9z5oaN6aF2g+gzWLMkso+dldAnwac3aCcPHAnViNNl95gSfvjJZDYlpo8MXIxl3QU5Oh8zHbCaE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1677506709; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=ZaphTkHMH0LsRYFTiO6wvd3PA01MvbeRtFqcDhu3XaQ=; b=d9yJMJgUNXYR3JmQjVRSQDOGoStwIBhUw1tRxiht5juhjg6Ud8emC3A7Yn39hxpCoURY9UndPEyzKeW7G9VD+C/M9LBfOI3s4eFc1Jgturaqj5hPBQQljz6emHutql1RjmGzCsBmPkRFbKHueR6hyqzPDt4KJlphwKJOy3O0fZ4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1677506709766640.656282212357; Mon, 27 Feb 2023 06:05:09 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pWe5C-0002jg-4G; Mon, 27 Feb 2023 09:02:26 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pWe4T-0000q3-3c for qemu-devel@nongnu.org; Mon, 27 Feb 2023 09:01:46 -0500 Received: from mail-wr1-x42e.google.com ([2a00:1450:4864:20::42e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pWe4R-0007a0-05 for qemu-devel@nongnu.org; Mon, 27 Feb 2023 09:01:40 -0500 Received: by mail-wr1-x42e.google.com with SMTP id bv17so6337953wrb.5 for ; Mon, 27 Feb 2023 06:01:38 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id s9-20020a5d4249000000b002c5598c14acsm7158514wrr.6.2023.02.27.06.01.37 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Feb 2023 06:01:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=ZaphTkHMH0LsRYFTiO6wvd3PA01MvbeRtFqcDhu3XaQ=; b=S/HnXpUMeEgAyUmvPZ287VoQLOvAYoCnviR1N3Rmh+27XekHhR9OqOXl6QxoP2buja nnBSeSFUHCoG2kx7kqcn5CVgWaUMc0bux9ldM/x3j8aY3oKvIhQxRh1fJ8E76vqvDTVY EeoeggCyHGb7exxisNnzsQCjdBqVxCJWcu4Mo9xN0LqSGpTPduKqES56Q5fAgggJyFV5 qOw8qv9I81oMotnKhGRGs5i5NmdrThVoF0qjN+6gacMEvJnEhWyESVlz5T+e+gUweTFQ NJcPHudOaICAtREkeztlSIELovHBqE3ErcxHD5nU/6CdCRhLpDW5W2X1ZKBjXA4fyBGd obKg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ZaphTkHMH0LsRYFTiO6wvd3PA01MvbeRtFqcDhu3XaQ=; b=QXhH6/ZYFvTQPV/2nWnMkl0S21Ww+l7Iud4LzsRcgcZYCN+P7Nt7fjn2MF0HaYlzYN 93YCChTVDEhIWEU0/8iTu4L6W1eeJ8b7APwBT5FRzE0jP0lxiEDUlHlr919bMVKZZMvJ iNHdD3nUdqzRmvBjnIBTJd7fQFOiWCGTBTCqFAgb4lh3sXjJ4Ze7W+UjmwuxGlYuptJJ y2CqdCsWeXcTi7iYrqVa5ohYFRmX3d+ieA4ym2rPqlV7bAYya5bkTrMGi7yX2pjsd3Fz WDQ/JsS9yG7fLVGjK66m/iqtvXS0xOtcepEdJ+KA+WLfkf5GcU5GhmHO8idAY41ektij piZA== X-Gm-Message-State: AO0yUKW5t212jKtpe/xmzIMeGMq8FxRSJ69a13aBvFidkppQu0ybtFbL 8rDLBlocP+IUdXdSgZazCkE0sI21itaMT/8g X-Google-Smtp-Source: AK7set9GaHDZQi0OdMH2WCjtqSD4nU28ht3W1vKTfiR5VafW+TZbqHeM7hLODdxnRCxx+Q5p787evQ== X-Received: by 2002:a5d:522e:0:b0:2c3:db9e:4b06 with SMTP id i14-20020a5d522e000000b002c3db9e4b06mr21780943wra.45.1677506498215; Mon, 27 Feb 2023 06:01:38 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 25/25] hw: Replace qemu_or_irq typedef by OrIRQState Date: Mon, 27 Feb 2023 14:01:02 +0000 Message-Id: <20230227140102.3712344-26-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230227140102.3712344-1-peter.maydell@linaro.org> References: <20230227140102.3712344-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1677506740324100001 From: Philippe Mathieu-Daud=C3=A9 OBJECT_DECLARE_SIMPLE_TYPE() macro provides the OrIRQState declaration for free. Besides, the QOM code style is to use the structure name as typedef, and QEMU style is to use Camel Case, so rename qemu_or_irq as OrIRQState. Mechanical change using: $ sed -i -e 's/qemu_or_irq/OrIRQState/g' $(git grep -l qemu_or_irq) Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Stefan Hajnoczi Reviewed-by: Alistair Francis Message-id: 20230113200138.52869-5-philmd@linaro.org Signed-off-by: Peter Maydell --- include/hw/arm/armsse.h | 6 +++--- include/hw/arm/bcm2835_peripherals.h | 2 +- include/hw/arm/exynos4210.h | 4 ++-- include/hw/arm/stm32f205_soc.h | 2 +- include/hw/arm/stm32f405_soc.h | 2 +- include/hw/arm/xlnx-versal.h | 6 +++--- include/hw/arm/xlnx-zynqmp.h | 2 +- include/hw/or-irq.h | 2 -- hw/arm/exynos4210.c | 4 ++-- hw/arm/mps2-tz.c | 2 +- hw/core/or-irq.c | 18 +++++++++--------- hw/pci-host/raven.c | 2 +- 12 files changed, 25 insertions(+), 27 deletions(-) diff --git a/include/hw/arm/armsse.h b/include/hw/arm/armsse.h index 9648e7a4193..cd0931d0a0b 100644 --- a/include/hw/arm/armsse.h +++ b/include/hw/arm/armsse.h @@ -155,12 +155,12 @@ struct ARMSSE { TZPPC apb_ppc[NUM_INTERNAL_PPCS]; TZMPC mpc[IOTS_NUM_MPC]; CMSDKAPBTimer timer[3]; - qemu_or_irq ppc_irq_orgate; + OrIRQState ppc_irq_orgate; SplitIRQ sec_resp_splitter; SplitIRQ ppc_irq_splitter[NUM_PPCS]; SplitIRQ mpc_irq_splitter[IOTS_NUM_EXP_MPC + IOTS_NUM_MPC]; - qemu_or_irq mpc_irq_orgate; - qemu_or_irq nmi_orgate; + OrIRQState mpc_irq_orgate; + OrIRQState nmi_orgate; =20 SplitIRQ cpu_irq_splitter[NUM_SSE_IRQS]; =20 diff --git a/include/hw/arm/bcm2835_peripherals.h b/include/hw/arm/bcm2835_= peripherals.h index c9d25d493e0..d724a2fc28a 100644 --- a/include/hw/arm/bcm2835_peripherals.h +++ b/include/hw/arm/bcm2835_peripherals.h @@ -56,7 +56,7 @@ struct BCM2835PeripheralState { BCM2835AuxState aux; BCM2835FBState fb; BCM2835DMAState dma; - qemu_or_irq orgated_dma_irq; + OrIRQState orgated_dma_irq; BCM2835ICState ic; BCM2835PropertyState property; BCM2835RngState rng; diff --git a/include/hw/arm/exynos4210.h b/include/hw/arm/exynos4210.h index 97353f1c02f..68db19f0cb7 100644 --- a/include/hw/arm/exynos4210.h +++ b/include/hw/arm/exynos4210.h @@ -96,8 +96,8 @@ struct Exynos4210State { MemoryRegion boot_secondary; MemoryRegion bootreg_mem; I2CBus *i2c_if[EXYNOS4210_I2C_NUMBER]; - qemu_or_irq pl330_irq_orgate[EXYNOS4210_NUM_DMA]; - qemu_or_irq cpu_irq_orgate[EXYNOS4210_NCPUS]; + OrIRQState pl330_irq_orgate[EXYNOS4210_NUM_DMA]; + OrIRQState cpu_irq_orgate[EXYNOS4210_NCPUS]; A9MPPrivState a9mpcore; Exynos4210GicState ext_gic; Exynos4210CombinerState int_combiner; diff --git a/include/hw/arm/stm32f205_soc.h b/include/hw/arm/stm32f205_soc.h index 849d3ed8891..5a4f7762642 100644 --- a/include/hw/arm/stm32f205_soc.h +++ b/include/hw/arm/stm32f205_soc.h @@ -63,7 +63,7 @@ struct STM32F205State { STM32F2XXADCState adc[STM_NUM_ADCS]; STM32F2XXSPIState spi[STM_NUM_SPIS]; =20 - qemu_or_irq *adc_irqs; + OrIRQState *adc_irqs; =20 MemoryRegion sram; MemoryRegion flash; diff --git a/include/hw/arm/stm32f405_soc.h b/include/hw/arm/stm32f405_soc.h index 249ab5434ec..c968ce3ab23 100644 --- a/include/hw/arm/stm32f405_soc.h +++ b/include/hw/arm/stm32f405_soc.h @@ -63,7 +63,7 @@ struct STM32F405State { STM32F4xxExtiState exti; STM32F2XXUsartState usart[STM_NUM_USARTS]; STM32F2XXTimerState timer[STM_NUM_TIMERS]; - qemu_or_irq adc_irqs; + OrIRQState adc_irqs; STM32F2XXADCState adc[STM_NUM_ADCS]; STM32F2XXSPIState spi[STM_NUM_SPIS]; =20 diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h index cbe8a19c10f..b6786e9832d 100644 --- a/include/hw/arm/xlnx-versal.h +++ b/include/hw/arm/xlnx-versal.h @@ -85,7 +85,7 @@ struct Versal { } rpu; =20 struct { - qemu_or_irq irq_orgate; + OrIRQState irq_orgate; XlnxXramCtrl ctrl[XLNX_VERSAL_NR_XRAM]; } xram; =20 @@ -103,7 +103,7 @@ struct Versal { XlnxCSUDMA dma_src; XlnxCSUDMA dma_dst; MemoryRegion linear_mr; - qemu_or_irq irq_orgate; + OrIRQState irq_orgate; } ospi; } iou; =20 @@ -113,7 +113,7 @@ struct Versal { XlnxVersalEFuseCtrl efuse_ctrl; XlnxVersalEFuseCache efuse_cache; =20 - qemu_or_irq apb_irq_orgate; + OrIRQState apb_irq_orgate; } pmc; =20 struct { diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h index 20bdf894aa0..687c75e3b03 100644 --- a/include/hw/arm/xlnx-zynqmp.h +++ b/include/hw/arm/xlnx-zynqmp.h @@ -130,7 +130,7 @@ struct XlnxZynqMPState { XlnxZDMA gdma[XLNX_ZYNQMP_NUM_GDMA_CH]; XlnxZDMA adma[XLNX_ZYNQMP_NUM_ADMA_CH]; XlnxCSUDMA qspi_dma; - qemu_or_irq qspi_irq_orgate; + OrIRQState qspi_irq_orgate; XlnxZynqMPAPUCtrl apu_ctrl; XlnxZynqMPCRF crf; CadenceTTCState ttc[XLNX_ZYNQMP_NUM_TTC]; diff --git a/include/hw/or-irq.h b/include/hw/or-irq.h index 131abc2e0c7..c0a42f37112 100644 --- a/include/hw/or-irq.h +++ b/include/hw/or-irq.h @@ -35,8 +35,6 @@ */ #define MAX_OR_LINES 48 =20 -typedef struct OrIRQState qemu_or_irq; - OBJECT_DECLARE_SIMPLE_TYPE(OrIRQState, OR_IRQ) =20 struct OrIRQState { diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c index 8dafa2215b6..6f2dda13f63 100644 --- a/hw/arm/exynos4210.c +++ b/hw/arm/exynos4210.c @@ -507,7 +507,7 @@ static uint64_t exynos4210_calc_affinity(int cpu) return (0x9 << ARM_AFF1_SHIFT) | cpu; } =20 -static DeviceState *pl330_create(uint32_t base, qemu_or_irq *orgate, +static DeviceState *pl330_create(uint32_t base, OrIRQState *orgate, qemu_irq irq, int nreq, int nevents, int = width) { SysBusDevice *busdev; @@ -806,7 +806,7 @@ static void exynos4210_init(Object *obj) =20 for (i =3D 0; i < ARRAY_SIZE(s->pl330_irq_orgate); i++) { char *name =3D g_strdup_printf("pl330-irq-orgate%d", i); - qemu_or_irq *orgate =3D &s->pl330_irq_orgate[i]; + OrIRQState *orgate =3D &s->pl330_irq_orgate[i]; =20 object_initialize_child(obj, name, orgate, TYPE_OR_IRQ); g_free(name); diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c index 284c09c91d3..07aecd9497d 100644 --- a/hw/arm/mps2-tz.c +++ b/hw/arm/mps2-tz.c @@ -152,7 +152,7 @@ struct MPS2TZMachineState { TZMSC msc[4]; CMSDKAPBUART uart[6]; SplitIRQ sec_resp_splitter; - qemu_or_irq uart_irq_orgate; + OrIRQState uart_irq_orgate; DeviceState *lan9118; SplitIRQ cpu_irq_splitter[MPS2TZ_NUMIRQ_MAX]; Clock *sysclk; diff --git a/hw/core/or-irq.c b/hw/core/or-irq.c index d8f3754e967..1df4bc05a7c 100644 --- a/hw/core/or-irq.c +++ b/hw/core/or-irq.c @@ -31,7 +31,7 @@ =20 static void or_irq_handler(void *opaque, int n, int level) { - qemu_or_irq *s =3D OR_IRQ(opaque); + OrIRQState *s =3D OR_IRQ(opaque); int or_level =3D 0; int i; =20 @@ -46,7 +46,7 @@ static void or_irq_handler(void *opaque, int n, int level) =20 static void or_irq_reset(DeviceState *dev) { - qemu_or_irq *s =3D OR_IRQ(dev); + OrIRQState *s =3D OR_IRQ(dev); int i; =20 for (i =3D 0; i < MAX_OR_LINES; i++) { @@ -56,7 +56,7 @@ static void or_irq_reset(DeviceState *dev) =20 static void or_irq_realize(DeviceState *dev, Error **errp) { - qemu_or_irq *s =3D OR_IRQ(dev); + OrIRQState *s =3D OR_IRQ(dev); =20 assert(s->num_lines <=3D MAX_OR_LINES); =20 @@ -65,7 +65,7 @@ static void or_irq_realize(DeviceState *dev, Error **errp) =20 static void or_irq_init(Object *obj) { - qemu_or_irq *s =3D OR_IRQ(obj); + OrIRQState *s =3D OR_IRQ(obj); =20 qdev_init_gpio_out(DEVICE(obj), &s->out_irq, 1); } @@ -84,7 +84,7 @@ static void or_irq_init(Object *obj) =20 static bool vmstate_extras_needed(void *opaque) { - qemu_or_irq *s =3D OR_IRQ(opaque); + OrIRQState *s =3D OR_IRQ(opaque); =20 return s->num_lines >=3D OLD_MAX_OR_LINES; } @@ -95,7 +95,7 @@ static const VMStateDescription vmstate_or_irq_extras =3D= { .minimum_version_id =3D 1, .needed =3D vmstate_extras_needed, .fields =3D (VMStateField[]) { - VMSTATE_VARRAY_UINT16_UNSAFE(levels, qemu_or_irq, num_lines, 0, + VMSTATE_VARRAY_UINT16_UNSAFE(levels, OrIRQState, num_lines, 0, vmstate_info_bool, bool), VMSTATE_END_OF_LIST(), }, @@ -106,7 +106,7 @@ static const VMStateDescription vmstate_or_irq =3D { .version_id =3D 1, .minimum_version_id =3D 1, .fields =3D (VMStateField[]) { - VMSTATE_BOOL_SUB_ARRAY(levels, qemu_or_irq, 0, OLD_MAX_OR_LINES), + VMSTATE_BOOL_SUB_ARRAY(levels, OrIRQState, 0, OLD_MAX_OR_LINES), VMSTATE_END_OF_LIST(), }, .subsections =3D (const VMStateDescription*[]) { @@ -116,7 +116,7 @@ static const VMStateDescription vmstate_or_irq =3D { }; =20 static Property or_irq_properties[] =3D { - DEFINE_PROP_UINT16("num-lines", qemu_or_irq, num_lines, 1), + DEFINE_PROP_UINT16("num-lines", OrIRQState, num_lines, 1), DEFINE_PROP_END_OF_LIST(), }; =20 @@ -136,7 +136,7 @@ static void or_irq_class_init(ObjectClass *klass, void = *data) static const TypeInfo or_irq_type_info =3D { .name =3D TYPE_OR_IRQ, .parent =3D TYPE_DEVICE, - .instance_size =3D sizeof(qemu_or_irq), + .instance_size =3D sizeof(OrIRQState), .instance_init =3D or_irq_init, .class_init =3D or_irq_class_init, }; diff --git a/hw/pci-host/raven.c b/hw/pci-host/raven.c index cdfb62ac2ec..072ffe3c5e2 100644 --- a/hw/pci-host/raven.c +++ b/hw/pci-host/raven.c @@ -60,7 +60,7 @@ DECLARE_INSTANCE_CHECKER(PREPPCIState, RAVEN_PCI_HOST_BRI= DGE, struct PRePPCIState { PCIHostState parent_obj; =20 - qemu_or_irq *or_irq; + OrIRQState *or_irq; qemu_irq pci_irqs[PCI_NUM_PINS]; PCIBus pci_bus; AddressSpace pci_io_as; --=20 2.34.1