[v1] Add basic ACPI support for risc-v virt

[PATCH 00/10] Add basic ACPI support for risc-v virt

Sunil V L posted 10 patches 1 year, 2 months ago

Diff against v2 v3 v4 v5
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Patches applied successfully (tree, apply log)
git fetch https://github.com/patchew-project/qemu tags/patchew/20230202045223.2594627-1-sunilvl@ventanamicro.com

Maintainers: Palmer Dabbelt <palmer@dabbelt.com>, Alistair Francis <alistair.francis@wdc.com>, Bin Meng <bin.meng@windriver.com>, Sunil V L <sunilvl@ventanamicro.com>

There is a newer version of this series

MAINTAINERS                |   6 +
hw/riscv/Kconfig           |   3 +
hw/riscv/meson.build       |   1 +
hw/riscv/virt-acpi-build.c | 391 +++++++++++++++++++++++++++++++++++++
hw/riscv/virt.c            |  48 +++++
include/hw/riscv/virt.h    |   6 +
6 files changed, 455 insertions(+)
create mode 100644 hw/riscv/virt-acpi-build.c

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[PATCH 00/10] Add basic ACPI support for risc-v virt

Posted by Sunil V L 1 year, 2 months ago

This series adds the basic ACPI support for the RISC-V virt machine. 
Currently only INTC interrupt controller specification is approved by the
UEFI forum. External interrupt controller support in ACPI is in progress.

The basic infrstructure changes are mostly leveraged from ARM.

This adds support for INTC and RHCT tables as specified in below ECR links
which are approved by UEFI forum.
RINTC - https://drive.google.com/file/d/1R6k4MshhN3WTT-hwqAquu5nX6xSEqK2l/view
RHCT - https://drive.google.com/file/d/1nP3nFiH4jkPMp6COOxP6123DCZKR-tia/view

These changes are also available @
https://github.com/vlsunil/qemu/tree/acpi_b1_us_review

The series is tested using SBI HVC console and initrd.

Test instructions:
1) Build Qemu with ACPI support (this series)

2) Build EDK2 as per instructions in
https://github.com/vlsunil/riscv-uefi-edk2-docs/wiki/RISC-V-Qemu-Virt-support

3) Build Linux with ACPI support using below branch
https://github.com/vlsunil/linux/commits/acpi_b1_us_review_ipi17
after enabling SBI HVC and SBI earlycon options.

CONFIG_RISCV_SBI_V01=y
CONFIG_SERIAL_EARLYCON_RISCV_SBI=y
CONFIG_HVC_RISCV_SBI=y

4) Build buildroot.

Run with below command.
qemu-system-riscv64   -nographic \
-drive file=Build/RiscVVirtQemu/RELEASE_GCC5/FV/RISCV_VIRT.fd,if=pflash,format=raw,unit=1 \
-machine virt,acpi=on -smp 16 -m 2G \
-kernel arch/riscv/boot/Image \
-initrd buildroot/output/images/rootfs.cpio \
-append "root=/dev/ram ro console=hvc0 earlycon=sbi"

Sunil V L (10):
  hw/riscv/virt: Add OEM_ID and OEM_TABLE_ID fields
  hw/riscv/virt: Add a switch to enable/disable ACPI
  hw/riscv/virt: Add memmap pointer to RiscVVirtState
  hw/riscv/virt: virt-acpi-build.c: Add basic ACPI tables
  hw/riscv/virt: virt-acpi-build.c: Add RINTC in MADT
  hw/riscv/virt: virt-acpi-build.c: Add RHCT Table
  hw/riscv: meson.build: Build virt-acpi-build.c
  hw/riscv/Kconfig: virt: Enable ACPI config options
  hw/riscv/virt.c: Initialize the ACPI tables
  MAINTAINERS: Add entry for RISC-V ACPI

 MAINTAINERS                |   6 +
 hw/riscv/Kconfig           |   3 +
 hw/riscv/meson.build       |   1 +
 hw/riscv/virt-acpi-build.c | 391 +++++++++++++++++++++++++++++++++++++
 hw/riscv/virt.c            |  48 +++++
 include/hw/riscv/virt.h    |   6 +
 6 files changed, 455 insertions(+)
 create mode 100644 hw/riscv/virt-acpi-build.c

-- 
2.38.0