On Sun, 05 Mar 2023 15:45:05 PST (-0800), Palmer Dabbelt wrote:
> On Thu, 02 Mar 2023 01:12:04 PST (-0800), sunilvl@ventanamicro.com wrote:
>> This series adds the basic ACPI support for the RISC-V virt machine.
>> Currently only RINTC interrupt controller specification is approved by the
>> UEFI forum. External interrupt controller support in ACPI is in progress.
>>
>> This adds support for RINTC and RHCT tables as specified in below ECR links
>> which are approved by UEFI forum.
>> RINTC - https://drive.google.com/file/d/1R6k4MshhN3WTT-hwqAquu5nX6xSEqK2l/view
>> RHCT - https://drive.google.com/file/d/1nP3nFiH4jkPMp6COOxP6123DCZKR-tia/view
>>
>> These changes are also available @
>> https://github.com/vlsunil/qemu/tree/acpi_b1_us_review_V5
>>
>> Changes since V4:
>> 1) Used possible_cpus to create cpu topology in DSDT, MADT and RHCT as
>> per Igor's feedback.
>
> Thanks. These all look good to me, but given that Igor had some
> feedback on the v4 and it's pretty much just been weekend since t hese
> went out I'm going to hold off until tomorrow before merging anything.
> They're all staged and passing the tests on my end, so everything's good
> as far as I'm concerned.
I've queued these up on riscv-to-apply.next. I know it's pretty last
minute, but IMO we're better off having these a cycle earlier as a lot
of the dependencies here are cross-project and it'll be better tested if
released.
If anyone has an issue please say something, I'll be tagging a PR soon.
>
>> 2) Moved MAINTAINER entries below ACPI/SMBIOS entry as per Drew's
>> feedback
>> Changes since V3:
>> 1) Added back acpi_align_size() wrapper as per Drew's feedback
>> 2) Updated RB tags
>>
>> Changes since V2:
>> 1) Squashed commits and updated commit message as per feedback from Daniel.
>> 2) Addressed comments from Drew.
>> 3) Updated tags.
>>
>> Changes since V1:
>> 1) Addressed comments from Bin Meng.
>> 2) Made acpi switch default AUTO similar to other architectures.
>> 3) Re-based and added RB and ACKs.
>>
>> The series is tested using SBI HVC console and initrd.
>>
>> Test instructions:
>> 1) Build Qemu with ACPI support (this series)
>>
>> 2) Build EDK2 as per instructions in
>> https://github.com/vlsunil/riscv-uefi-edk2-docs/wiki/RISC-V-Qemu-Virt-support
>>
>> 3) Build Linux with ACPI support using below branch
>> https://github.com/vlsunil/linux/commits/acpi_b1_us_review_ipi17_V2
>> after enabling SBI HVC and SBI earlycon options.
>>
>> CONFIG_RISCV_SBI_V01=y
>> CONFIG_SERIAL_EARLYCON_RISCV_SBI=y
>> CONFIG_HVC_RISCV_SBI=y
>>
>> 4) Build buildroot.
>>
>> Run with below command.
>> qemu-system-riscv64 -nographic \
>> -drive file=Build/RiscVVirtQemu/RELEASE_GCC5/FV/RISCV_VIRT.fd,if=pflash,format=raw,unit=1 \
>> -machine virt -smp 16 -m 2G \
>> -kernel arch/riscv/boot/Image \
>> -initrd buildroot/output/images/rootfs.cpio \
>> -append "root=/dev/ram ro console=hvc0 earlycon=sbi"
>>
>>
>> Sunil V L (8):
>> hw/riscv/virt: Add OEM_ID and OEM_TABLE_ID fields
>> hw/riscv/virt: Add a switch to disable ACPI
>> hw/riscv/virt: Add memmap pointer to RiscVVirtState
>> hw/riscv/virt: Enable basic ACPI infrastructure
>> hw/riscv/virt: virt-acpi-build.c: Add RINTC in MADT
>> hw/riscv/virt: virt-acpi-build.c: Add RHCT Table
>> hw/riscv/virt.c: Initialize the ACPI tables
>> MAINTAINERS: Add entry for RISC-V ACPI
>>
>> MAINTAINERS | 18 +-
>> hw/riscv/Kconfig | 1 +
>> hw/riscv/meson.build | 1 +
>> hw/riscv/virt-acpi-build.c | 416 +++++++++++++++++++++++++++++++++++++
>> hw/riscv/virt.c | 40 ++++
>> include/hw/riscv/virt.h | 6 +
>> 6 files changed, 476 insertions(+), 6 deletions(-)
>> create mode 100644 hw/riscv/virt-acpi-build.c