[v3] target/ppc: Implement Dynamic Execution Control Registers

[PATCH v3 0/2] target/ppc: Implement Dynamic Execution Control Registers

Nicholas Miehlbradt posted 2 patches 1 year, 4 months ago

Diff against v1 v2
Download series mbox

Patches applied successfully (tree, apply log)
git fetch https://github.com/patchew-project/qemu tags/patchew/20221220042330.2387944-1-nicholas@linux.ibm.com

Maintainers: Daniel Henrique Barboza <danielhb413@gmail.com>, "Cédric Le Goater" <clg@kaod.org>, David Gibson <david@gibson.dropbear.id.au>, Greg Kurz <groug@kaod.org>

target/ppc/cpu.h         | 19 +++++++++++++
target/ppc/cpu_init.c    | 25 +++++++++++++++++
target/ppc/excp_helper.c | 58 +++++++++++++++++++++++++++++-----------
target/ppc/spr_common.h  |  1 +
target/ppc/translate.c   | 19 +++++++++++++
5 files changed, 107 insertions(+), 15 deletions(-)

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[PATCH v3 0/2] target/ppc: Implement Dynamic Execution Control Registers

Posted by Nicholas Miehlbradt 1 year, 4 months ago

Implements the Dynamic Execution Control Register (DEXCR) and the
Hypervisor Dynamic Execution Control Register (HDEXCR) in TCG as
defined in Power ISA 3.1B. Only aspects 5 (Non-privileged hash instruction
enable) and 6 (Privileged hash instruction enable) have architectural
effects. Other aspects can be manipulated but have no effect on execution.

Adds checks to these registers in the hashst and hashchk instructions so
that they are executed as nops when not enabled.

There is currently an RFC for the kernel interface for the DEXCR on the 
Linux PPC mailing list:
https://lore.kernel.org/linuxppc-dev/20221128024458.46121-1-bgray@linux.ibm.com/

v3:
 - Fix typos

v2:
 - Clearing of upper 32 bits of userspace registers is now performed on 
   register read rather than register write. 

Nicholas Miehlbradt (2):
  target/ppc: Implement the DEXCR and HDEXCR
  target/ppc: Check DEXCR on hash{st, chk} instructions

 target/ppc/cpu.h         | 19 +++++++++++++
 target/ppc/cpu_init.c    | 25 +++++++++++++++++
 target/ppc/excp_helper.c | 58 +++++++++++++++++++++++++++++-----------
 target/ppc/spr_common.h  |  1 +
 target/ppc/translate.c   | 19 +++++++++++++
 5 files changed, 107 insertions(+), 15 deletions(-)

-- 
2.34.1

Re: [PATCH v3 0/2] target/ppc: Implement Dynamic Execution Control Registers

Posted by Daniel Henrique Barboza 1 year, 4 months ago

Queued in gitlab.com/danielhb/qemu/tree/ppc-next. Thanks,


Daniel

On 12/20/22 01:23, Nicholas Miehlbradt wrote:
> Implements the Dynamic Execution Control Register (DEXCR) and the
> Hypervisor Dynamic Execution Control Register (HDEXCR) in TCG as
> defined in Power ISA 3.1B. Only aspects 5 (Non-privileged hash instruction
> enable) and 6 (Privileged hash instruction enable) have architectural
> effects. Other aspects can be manipulated but have no effect on execution.
> 
> Adds checks to these registers in the hashst and hashchk instructions so
> that they are executed as nops when not enabled.
> 
> There is currently an RFC for the kernel interface for the DEXCR on the
> Linux PPC mailing list:
> https://lore.kernel.org/linuxppc-dev/20221128024458.46121-1-bgray@linux.ibm.com/
> 
> v3:
>   - Fix typos
> 
> v2:
>   - Clearing of upper 32 bits of userspace registers is now performed on
>     register read rather than register write.
> 
> Nicholas Miehlbradt (2):
>    target/ppc: Implement the DEXCR and HDEXCR
>    target/ppc: Check DEXCR on hash{st, chk} instructions
> 
>   target/ppc/cpu.h         | 19 +++++++++++++
>   target/ppc/cpu_init.c    | 25 +++++++++++++++++
>   target/ppc/excp_helper.c | 58 +++++++++++++++++++++++++++++-----------
>   target/ppc/spr_common.h  |  1 +
>   target/ppc/translate.c   | 19 +++++++++++++
>   5 files changed, 107 insertions(+), 15 deletions(-)
>