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(haven.au.ibm.com [9.192.254.114]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.au.ibm.com (Postfix) with ESMTPSA id 66117604A7; Tue, 20 Dec 2022 15:23:41 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding; s=pp1; bh=RpPNYKJK+4s6gwhQm2AunQMcStb1vYsnm7FIWCOYM10=; b=k5IEBEzabPof9CLcpXxX/NgvPnHONY7n8iXVnUvKd3u50+HWadUjNG0dd6nU8zD4XW79 An/gPTKhj67qIuTs5YtQqAs4VnDHU32aDl7LtPwOAqms0S3ZYy1jwqIw8PZkJ9UNdU0B kATAL6aBCoHdT6QEfxsO8JAUcWFr9a86pWoWlfF6merrvJ446lbG55lfIGO+rf1PKPgH gYB2qweat4eCkRUIb9tJn8N6xlcLURdqx9MDLtM2OvuAbeE2hxoiGCjVa91MQnSK1xPw LXCcEAHf9pLvQmCYehcq9Moug+5rOvOTDlTgEkudvpGr57rk6akAoIRiowpjXrjUY2dy Ow== From: Nicholas Miehlbradt To: qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, danielhb413@gmail.com, clg@kaod.org, david@gibson.dropbear.id.au, groug@kaod.org, victor.colombo@eldorado.org.br, Nicholas Miehlbradt Subject: [PATCH v3 1/2] target/ppc: Implement the DEXCR and HDEXCR Date: Tue, 20 Dec 2022 04:23:29 +0000 Message-Id: <20221220042330.2387944-2-nicholas@linux.ibm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221220042330.2387944-1-nicholas@linux.ibm.com> References: <20221220042330.2387944-1-nicholas@linux.ibm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: b1uYK_UoAIotIjsGLJnZyBhnW6fgaNth X-Proofpoint-GUID: l_0dtzFplS9a-4Qpt4APx5GjEG4RQ4gd X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.923,Hydra:6.0.545,FMLib:17.11.122.1 definitions=2022-12-19_05,2022-12-15_02,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 impostorscore=0 mlxlogscore=999 lowpriorityscore=0 mlxscore=0 bulkscore=0 malwarescore=0 suspectscore=0 priorityscore=1501 adultscore=0 clxscore=1015 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2212070000 definitions=main-2212200034 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=148.163.158.5; envelope-from=nicholas@linux.ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1671510307786100005 Content-Type: text/plain; charset="utf-8" Define the DEXCR and HDEXCR as special purpose registers. Each register occupies two SPR indicies, one which can be read in an unprivileged state and one which can be modified in the appropriate priviliged state, however both indicies refer to the same underlying value. Note that the ISA uses the abbreviation UDEXCR in two different contexts: the userspace DEXCR, the SPR index which can be read from userspace (implemented in this patch), and the ultravisor DEXCR, the equivalent register for the ultravisor state (not implemented). Signed-off-by: Nicholas Miehlbradt Reviewed-by: Daniel Henrique Barboza --- v2: Clearing of upper 32 bits of DEXCR is now performed on read from problem state rather than on write in privileged state. v3: Fix typos --- target/ppc/cpu.h | 19 +++++++++++++++++++ target/ppc/cpu_init.c | 25 +++++++++++++++++++++++++ target/ppc/spr_common.h | 1 + target/ppc/translate.c | 19 +++++++++++++++++++ 4 files changed, 64 insertions(+) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 81d4263a07..3923f174f8 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -1068,6 +1068,21 @@ struct ppc_radix_page_info { uint32_t entries[PPC_PAGE_SIZES_MAX_SZ]; }; =20 +/*************************************************************************= ****/ +/* Dynamic Execution Control Register */ + +#define DEXCR_ASPECT(name, num) \ +FIELD(DEXCR, PNH_##name, PPC_BIT_NR(num), 1) \ +FIELD(DEXCR, PRO_##name, PPC_BIT_NR(num + 32), 1) \ +FIELD(HDEXCR, HNU_##name, PPC_BIT_NR(num), 1) \ +FIELD(HDEXCR, ENF_##name, PPC_BIT_NR(num + 32), 1) \ + +DEXCR_ASPECT(SBHE, 0) +DEXCR_ASPECT(IBRTPD, 1) +DEXCR_ASPECT(SRAPD, 4) +DEXCR_ASPECT(NPHIE, 5) +DEXCR_ASPECT(PHIE, 6) + /*************************************************************************= ****/ /* The whole PowerPC CPU context */ =20 @@ -1674,9 +1689,11 @@ void ppc_compat_add_property(Object *obj, const char= *name, #define SPR_BOOKE_GIVOR13 (0x1BC) #define SPR_BOOKE_GIVOR14 (0x1BD) #define SPR_TIR (0x1BE) +#define SPR_UHDEXCR (0x1C7) #define SPR_PTCR (0x1D0) #define SPR_HASHKEYR (0x1D4) #define SPR_HASHPKEYR (0x1D5) +#define SPR_HDEXCR (0x1D7) #define SPR_BOOKE_SPEFSCR (0x200) #define SPR_Exxx_BBEAR (0x201) #define SPR_Exxx_BBTAR (0x202) @@ -1865,8 +1882,10 @@ void ppc_compat_add_property(Object *obj, const char= *name, #define SPR_RCPU_L2U_RA2 (0x32A) #define SPR_MPC_MD_DBRAM1 (0x32A) #define SPR_RCPU_L2U_RA3 (0x32B) +#define SPR_UDEXCR (0x32C) #define SPR_TAR (0x32F) #define SPR_ASDR (0x330) +#define SPR_DEXCR (0x33C) #define SPR_IC (0x350) #define SPR_VTB (0x351) #define SPR_MMCRC (0x353) diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index cbf0081374..6433f4fdfd 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -5727,6 +5727,30 @@ static void register_power10_hash_sprs(CPUPPCState *= env) hashpkeyr_initial_value); } =20 +static void register_power10_dexcr_sprs(CPUPPCState *env) +{ + spr_register(env, SPR_DEXCR, "DEXCR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0); + + spr_register(env, SPR_UDEXCR, "DEXCR", + &spr_read_dexcr_ureg, SPR_NOACCESS, + &spr_read_dexcr_ureg, SPR_NOACCESS, + 0); + + spr_register_hv(env, SPR_HDEXCR, "HDEXCR", + SPR_NOACCESS, SPR_NOACCESS, + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0); + + spr_register(env, SPR_UHDEXCR, "HDEXCR", + &spr_read_dexcr_ureg, SPR_NOACCESS, + &spr_read_dexcr_ureg, SPR_NOACCESS, + 0); +} + /* * Initialize PMU counter overflow timers for Power8 and * newer Power chips when using TCG. @@ -6402,6 +6426,7 @@ static void init_proc_POWER10(CPUPPCState *env) register_power8_rpr_sprs(env); register_power9_mmu_sprs(env); register_power10_hash_sprs(env); + register_power10_dexcr_sprs(env); =20 /* FIXME: Filter fields properly based on privilege level */ spr_register_kvm_hv(env, SPR_PSSCR, "PSSCR", NULL, NULL, NULL, NULL, diff --git a/target/ppc/spr_common.h b/target/ppc/spr_common.h index b5a5bc6895..8437eb0340 100644 --- a/target/ppc/spr_common.h +++ b/target/ppc/spr_common.h @@ -195,6 +195,7 @@ void spr_read_ebb_upper32(DisasContext *ctx, int gprn, = int sprn); void spr_write_ebb_upper32(DisasContext *ctx, int sprn, int gprn); void spr_write_hmer(DisasContext *ctx, int sprn, int gprn); void spr_write_lpcr(DisasContext *ctx, int sprn, int gprn); +void spr_read_dexcr_ureg(DisasContext *ctx, int gprn, int sprn); #endif =20 void register_low_BATs(CPUPPCState *env); diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 19c1d17cb0..0e4cabcf54 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -1249,6 +1249,25 @@ void spr_write_ebb_upper32(DisasContext *ctx, int sp= rn, int gprn) gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); spr_write_prev_upper32(ctx, sprn, gprn); } + +void spr_read_dexcr_ureg(DisasContext *ctx, int gprn, int sprn) +{ + TCGv t0 =3D tcg_temp_new(); + + /* + * Access to the (H)DEXCR in problem state is done using seperate=20 + * SPR indexes which are 16 below the SPR indexes which have full + * access to the (H)DEXCR in privileged state. Problem state can + * only read bits 32:63, bits 0:31 return 0. + * + * See section 9.3.1-9.3.2 of PowerISA v3.1B + */ + + gen_load_spr(t0, sprn + 16); + tcg_gen_ext32u_tl(cpu_gpr[gprn], t0); + + tcg_temp_free(t0); +} #endif =20 #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) = \ --=20 2.34.1 From nobody Wed May 15 14:29:11 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=linux.ibm.com ARC-Seal: i=1; a=rsa-sha256; t=1671510305; cv=none; d=zohomail.com; s=zohoarc; b=R0pDGfSWoBQyNHLuRYlGXZJFQveKAlmouHYYyE+NiPRo8A6EcplG7HxHNdOTE8XTAzo/k2M0w1oL2wiaJoPjkoE6cBHGIcEcI0/jPQM9YfJMuWoH2ujFmUpoaB4xG9YhSNJnM7PQ0Ix0eqAcouqnGpyU12hLHebx/sBs+LZVoDQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1671510305; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=POKYxpHIHQUKpBc19d1Q5JCvO7MWTJtN7VX3VgKeYQk=; b=O+GHbtc0iRB/RTZE80EZ653dRrTG1Rm/ID7EXR6uPV7lk4atYphL6tGvusqcVu4Q4MGk+aA+xChpY73aZgxt29c3UIV6G7ozhFhvgaT43A+VjVqCB22ohP2df67FqeSZ67cy2WaN2rm3CsjX2OQuhF8C2B1YZgZPr85RGIItdXI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1671510305381874.9349148569495; Mon, 19 Dec 2022 20:25:05 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1p7UAl-0000eG-2N; Mon, 19 Dec 2022 23:24:11 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1p7UAh-0000cm-Lg; Mon, 19 Dec 2022 23:24:07 -0500 Received: from mx0b-001b2d01.pphosted.com ([148.163.158.5] helo=mx0a-001b2d01.pphosted.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1p7UAf-0002hh-7o; Mon, 19 Dec 2022 23:24:07 -0500 Received: from pps.filterd (m0098416.ppops.net [127.0.0.1]) by mx0b-001b2d01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 2BK4E5qQ014096; Tue, 20 Dec 2022 04:23:50 GMT Received: from pps.reinject (localhost [127.0.0.1]) by mx0b-001b2d01.pphosted.com (PPS) with ESMTPS id 3mk5u985vj-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 20 Dec 2022 04:23:49 +0000 Received: from m0098416.ppops.net (m0098416.ppops.net [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 2BK4K7s6000632; Tue, 20 Dec 2022 04:23:49 GMT Received: from ppma04fra.de.ibm.com (6a.4a.5195.ip4.static.sl-reverse.com [149.81.74.106]) by mx0b-001b2d01.pphosted.com (PPS) with ESMTPS id 3mk5u985v2-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 20 Dec 2022 04:23:49 +0000 Received: from pps.filterd (ppma04fra.de.ibm.com [127.0.0.1]) by ppma04fra.de.ibm.com (8.17.1.19/8.17.1.19) with ESMTP id 2BJLeuKq016895; Tue, 20 Dec 2022 04:23:47 GMT Received: from smtprelay07.fra02v.mail.ibm.com ([9.218.2.229]) by ppma04fra.de.ibm.com (PPS) with ESMTPS id 3mh6yw2fdb-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 20 Dec 2022 04:23:47 +0000 Received: from smtpav01.fra02v.mail.ibm.com (smtpav01.fra02v.mail.ibm.com [10.20.54.100]) by smtprelay07.fra02v.mail.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 2BK4Nivj37487098 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Tue, 20 Dec 2022 04:23:45 GMT Received: from smtpav01.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id D262B20040; Tue, 20 Dec 2022 04:23:44 +0000 (GMT) Received: from smtpav01.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id DABF420049; Tue, 20 Dec 2022 04:23:43 +0000 (GMT) Received: from ozlabs.au.ibm.com (unknown [9.192.253.14]) by smtpav01.fra02v.mail.ibm.com (Postfix) with ESMTP; Tue, 20 Dec 2022 04:23:43 +0000 (GMT) Received: from nicholasmvm.. (haven.au.ibm.com [9.192.254.114]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.au.ibm.com (Postfix) with ESMTPSA id 39026604A8; Tue, 20 Dec 2022 15:23:42 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding; s=pp1; bh=POKYxpHIHQUKpBc19d1Q5JCvO7MWTJtN7VX3VgKeYQk=; b=gg3+rLMekUUn2YnuiqI8DPdw20qUKH9rJZBFUie/LZLjy16e83j1CRKbJIFrpUlxeIwg Zu3BRo0trJ2Ps8JSEBNtS5D5CHuhaKTg2/7ZGaNHB//aEQuCf/Vy0TFhYgYcnupbYERI KJ5tz1gzD9zgidqhUZgz68NhvqXM7jQ75LAXul8xwRPzUkIhpZdCsLUvaTEQ0KHlWEYt HdiPItJwCIkY3/QQxXhdJ/to6YJB8ff+7qpCGGKGixwwSYCCZt2jLrZK3I4L5YzTb+pG gqK8migfgK8qnWnqPDgFKatV9fHMyCnI3xBEo8DHFT5O96NCt9La3VEgQbQ+l3pzPjSM xA== From: Nicholas Miehlbradt To: qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, danielhb413@gmail.com, clg@kaod.org, david@gibson.dropbear.id.au, groug@kaod.org, victor.colombo@eldorado.org.br, Nicholas Miehlbradt Subject: [PATCH v3 2/2] target/ppc: Check DEXCR on hash{st, chk} instructions Date: Tue, 20 Dec 2022 04:23:30 +0000 Message-Id: <20221220042330.2387944-3-nicholas@linux.ibm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221220042330.2387944-1-nicholas@linux.ibm.com> References: <20221220042330.2387944-1-nicholas@linux.ibm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: NqXthWtgYzq68D_DPSBhyVlihVkS25en X-Proofpoint-GUID: OuQPai6l6mK-or5UsxN32kDczfKg1Lf5 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.923,Hydra:6.0.545,FMLib:17.11.122.1 definitions=2022-12-19_05,2022-12-15_02,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 impostorscore=0 mlxlogscore=869 lowpriorityscore=0 mlxscore=0 bulkscore=0 malwarescore=0 suspectscore=0 priorityscore=1501 adultscore=0 clxscore=1015 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2212070000 definitions=main-2212200034 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=148.163.158.5; envelope-from=nicholas@linux.ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1671510305720100001 Content-Type: text/plain; charset="utf-8" Adds checks to the hashst and hashchk instructions to only execute if enabled by the relevant aspect in the DEXCR and HDEXCR. This behaviour is guarded behind TARGET_PPC64 since Power10 is currently the only implementation which has the DEXCR. Reviewed-by: Daniel Henrique Barboza Signed-off-by: Nicholas Miehlbradt --- target/ppc/excp_helper.c | 58 +++++++++++++++++++++++++++++----------- 1 file changed, 43 insertions(+), 15 deletions(-) diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index 94adcb766b..add4d54ae7 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -2902,29 +2902,57 @@ static uint64_t hash_digest(uint64_t ra, uint64_t r= b, uint64_t key) return stage1_h ^ stage1_l; } =20 +static void do_hash(CPUPPCState *env, target_ulong ea, target_ulong ra, + target_ulong rb, uint64_t key, bool store) +{ + uint64_t calculated_hash =3D hash_digest(ra, rb, key), loaded_hash; + + if (store) { + cpu_stq_data_ra(env, ea, calculated_hash, GETPC()); + } else { + loaded_hash =3D cpu_ldq_data_ra(env, ea, GETPC()); + if (loaded_hash !=3D calculated_hash) { + raise_exception_err_ra(env, POWERPC_EXCP_PROGRAM, + POWERPC_EXCP_TRAP, GETPC()); + } + } +} + #include "qemu/guest-random.h" =20 -#define HELPER_HASH(op, key, store) = \ +#ifdef TARGET_PPC64 +#define HELPER_HASH(op, key, store, dexcr_aspect) = \ void helper_##op(CPUPPCState *env, target_ulong ea, target_ulong ra, = \ target_ulong rb) = \ { = \ - uint64_t calculated_hash =3D hash_digest(ra, rb, key), loaded_hash; = \ - = \ - if (store) { = \ - cpu_stq_data_ra(env, ea, calculated_hash, GETPC()); = \ - } else { = \ - loaded_hash =3D cpu_ldq_data_ra(env, ea, GETPC()); = \ - if (loaded_hash !=3D calculated_hash) { = \ - raise_exception_err_ra(env, POWERPC_EXCP_PROGRAM, = \ - POWERPC_EXCP_TRAP, GETPC()); = \ - } = \ + if (env->msr & R_MSR_PR_MASK) { = \ + if (!(env->spr[SPR_DEXCR] & R_DEXCR_PRO_##dexcr_aspect##_MASK || = \ + env->spr[SPR_HDEXCR] & R_HDEXCR_ENF_##dexcr_aspect##_MASK)) = \ + return; = \ + } else if (!(env->msr & R_MSR_HV_MASK)) { = \ + if (!(env->spr[SPR_DEXCR] & R_DEXCR_PNH_##dexcr_aspect##_MASK || = \ + env->spr[SPR_HDEXCR] & R_HDEXCR_ENF_##dexcr_aspect##_MASK)) = \ + return; = \ + } else if (!(env->msr & R_MSR_S_MASK)) { = \ + if (!(env->spr[SPR_HDEXCR] & R_HDEXCR_HNU_##dexcr_aspect##_MASK)) = \ + return; = \ } = \ + = \ + do_hash(env, ea, ra, rb, key, store); = \ +} +#else +#define HELPER_HASH(op, key, store, dexcr_aspect) = \ +void helper_##op(CPUPPCState *env, target_ulong ea, target_ulong ra, = \ + target_ulong rb) = \ +{ = \ + do_hash(env, ea, ra, rb, key, store); = \ } +#endif /* TARGET_PPC64 */ =20 -HELPER_HASH(HASHST, env->spr[SPR_HASHKEYR], true) -HELPER_HASH(HASHCHK, env->spr[SPR_HASHKEYR], false) -HELPER_HASH(HASHSTP, env->spr[SPR_HASHPKEYR], true) -HELPER_HASH(HASHCHKP, env->spr[SPR_HASHPKEYR], false) +HELPER_HASH(HASHST, env->spr[SPR_HASHKEYR], true, NPHIE) +HELPER_HASH(HASHCHK, env->spr[SPR_HASHKEYR], false, NPHIE) +HELPER_HASH(HASHSTP, env->spr[SPR_HASHPKEYR], true, PHIE) +HELPER_HASH(HASHCHKP, env->spr[SPR_HASHPKEYR], false, PHIE) #endif /* CONFIG_TCG */ =20 #if !defined(CONFIG_USER_ONLY) --=20 2.34.1