Bernhard posted his "Consolidate PIIX south bridges" v3 series:
https://lore.kernel.org/qemu-devel/20221204190553.3274-1-shentey@gmail.com/

However in order to simplify it, on the Malta board we need to set
the PIIX IRQC[A:D] routing values via the embedded bootloader (used
when no external BIOS is provided). Jiaxun added a "bootloader
generator API" for 32-bit wide instructions, and we use it in the
write_bootloader() function.
This series provides the nanoMIPS equivalent generated instructions
and update the write_bootloader_nanomips() function.
That allow fixing the TODO left in
https://lore.kernel.org/qemu-devel/20221027204720.33611-3-philmd@linaro.org/
and apply Bernhard's consolidation.

Please review,

Phil.

Philippe Mathieu-Daudé (7):
  hw/mips/bootloader: Handle buffers as opaque arrays
  hw/mips/bootloader: Pass 32-bit immediate value to LUI opcode
    generator
  hw/mips/bootloader: Implement nanoMIPS NOP opcode
  hw/mips/bootloader: Implement nanoMIPS LUI opcode
  hw/mips/bootloader: Implement nanoMIPS SW opcode
  hw/mips/bootloader: Implement nanoMIPS SW opcode
  hw/mips/malta: Use bootloader generator API for nanoMIPS CPUs

 hw/mips/bootloader.c         | 140 +++++++++++++++++++++++------
 hw/mips/malta.c              | 167 ++++++++++-------------------------
 include/hw/mips/bootloader.h |  10 +--
 3 files changed, 162 insertions(+), 155 deletions(-)

-- 
2.38.1