targets/openrisc: Improve exception vectoring.

[Qemu-devel] [PATCH 0/2] targets/openrisc: Improve exception vectoring.

Tim 'mithro' Ansell posted 2 patches 7 years ago

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git fetch https://github.com/patchew-project/qemu tags/patchew/20170418061551.196582-1-mithro@mithis.com

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target/openrisc/cpu.c        | 2 ++
target/openrisc/cpu.h        | 7 +++++++
target/openrisc/interrupt.c  | 9 ++++++++-
target/openrisc/sys_helper.c | 7 +++++++
4 files changed, 24 insertions(+), 1 deletion(-)

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[Qemu-devel] [PATCH 0/2] targets/openrisc: Improve exception vectoring.

Posted by Tim 'mithro' Ansell 7 years ago

Hi,

This patch series improves the exception vectoring on the OpenRISC platform by
adding support for both the EVBAR register and EPH bit.

This is my first patch to upstream QEMU, so please do point of if I have done
anything silly.

Tim 'mithro' Ansell (2):
  target/openrisc: Implement EVBAR register
  target/openrisc: Implement EPH bit

 target/openrisc/cpu.c        | 2 ++
 target/openrisc/cpu.h        | 7 +++++++
 target/openrisc/interrupt.c  | 9 ++++++++-
 target/openrisc/sys_helper.c | 7 +++++++
 4 files changed, 24 insertions(+), 1 deletion(-)

-- 
2.12.1