From nobody Sat May 4 05:05:13 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; dkim=fail spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 149249633462099.59121933932045; Mon, 17 Apr 2017 23:18:54 -0700 (PDT) Received: from localhost ([::1]:40243 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1d0MTV-0004tD-4R for importer@patchew.org; Tue, 18 Apr 2017 02:18:53 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:56709) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1d0MSS-0004Jd-Nc for qemu-devel@nongnu.org; Tue, 18 Apr 2017 02:17:49 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1d0MSP-0004tZ-Ix for qemu-devel@nongnu.org; Tue, 18 Apr 2017 02:17:48 -0400 Received: from mail-pg0-x22a.google.com ([2607:f8b0:400e:c05::22a]:36624) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1d0MSP-0004tF-Cv for qemu-devel@nongnu.org; Tue, 18 Apr 2017 02:17:45 -0400 Received: by mail-pg0-x22a.google.com with SMTP id g2so82567833pge.3 for ; Mon, 17 Apr 2017 23:17:45 -0700 (PDT) Received: from tansell-z840-l.syd.corp.google.com ([100.64.125.243]) by smtp.gmail.com with ESMTPSA id e131sm15538458pfg.10.2017.04.17.23.17.41 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 17 Apr 2017 23:17:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mithis.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=F9WS16p1k9y+MQRMKMhNX6vOuSFlg16TGM2Fr9cPfi4=; b=Sszvg9qHOF2z/D4g950B/UxsQyqovVEStVQkdiogyNdsCGRSzhOholqoZMyVm5CExY pUkoKUO5afST9Gl7GeTwr2eqXQmV4X7cOgfHgjQa0WJNqn9JKaXO4zMWWOUa3Jt3GfpP l4WpW31KAIHHtX5YnnKWmK4diugJnkIUkviSc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=F9WS16p1k9y+MQRMKMhNX6vOuSFlg16TGM2Fr9cPfi4=; b=m8yGQCSNg9f8xW2soejnAyJ6bcsQbSnkALOHL6ScuMmWmdm7GKVkDiA8aYavYNqJ8e YeTDWbbOn3d75GbqQtbuXOEZpeehkbEkBUlGsymizyiF7ekNOvjQddq7rp7T0JbXfT8s fGqxg4Xisxmi7Zzel98bLtduIILrWs3/5b+8NJmEE8T9R10ielOTFgIua9/1cDwZk91J mZHHE2D0gTzhA/IEu+TPbcyG3/dI2ATfd9duElwwYQvNufVpYvsbMScdWIc4AeUNRsR2 DXKM4g2A65CKfOcivmpiLg2TOXTFZWSob67zoRA+IQTo8ukxBKDtFgRGGikw18FDh2hm 2D+Q== X-Gm-Message-State: AN3rC/6cw5NrcOqF726pkv4//XuGIrdxI7rcqE02JmKeepHIi94JJSgu oiOcnbOcuPMbvR6p1ygPTQ== X-Received: by 10.98.92.1 with SMTP id q1mr16023643pfb.209.1492496264172; Mon, 17 Apr 2017 23:17:44 -0700 (PDT) From: Tim 'mithro' Ansell To: qemu-devel@nongnu.org Date: Tue, 18 Apr 2017 16:15:50 +1000 Message-Id: <20170418061551.196582-2-mithro@mithis.com> X-Mailer: git-send-email 2.12.2.762.g0e3151a226-goog In-Reply-To: <20170418061551.196582-1-mithro@mithis.com> References: <20170418061551.196582-1-mithro@mithis.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2607:f8b0:400e:c05::22a Subject: [Qemu-devel] [PATCH 1/2] target/openrisc: Implement EVBAR register X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: shorne@gmail.com, Jia Liu , Tim 'mithro' Ansell Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Exception Vector Base Address Register (EVBAR) - This optional register can be used to apply an offset to the exception vector addresses. The significant bits (31-12) of the vector offset address for each exception depend on the setting of the Supervision Register (SR)'s EPH bit and the Exception Vector Base Address Register (EVBAR). Its presence is indicated by the EVBARP bit in the CPU Configuration Register (CPUCFGR). Signed-off-by: Tim 'mithro' Ansell Reviewed-by: Stafford Horne --- target/openrisc/cpu.c | 2 ++ target/openrisc/cpu.h | 7 +++++++ target/openrisc/interrupt.c | 6 +++++- target/openrisc/sys_helper.c | 7 +++++++ 4 files changed, 21 insertions(+), 1 deletion(-) diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index 7fd2b9a216..1524ed981a 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -134,6 +134,7 @@ static void or1200_initfn(Object *obj) =20 set_feature(cpu, OPENRISC_FEATURE_OB32S); set_feature(cpu, OPENRISC_FEATURE_OF32S); + set_feature(cpu, OPENRISC_FEATURE_EVBAR); } =20 static void openrisc_any_initfn(Object *obj) @@ -141,6 +142,7 @@ static void openrisc_any_initfn(Object *obj) OpenRISCCPU *cpu =3D OPENRISC_CPU(obj); =20 set_feature(cpu, OPENRISC_FEATURE_OB32S); + set_feature(cpu, OPENRISC_FEATURE_EVBAR); } =20 typedef struct OpenRISCCPUInfo { diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index 418a0e6960..1958b72718 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -111,6 +111,11 @@ enum { CPUCFGR_OF32S =3D (1 << 7), CPUCFGR_OF64S =3D (1 << 8), CPUCFGR_OV64S =3D (1 << 9), + /* CPUCFGR_ND =3D (1 << 10), */ + /* CPUCFGR_AVRP =3D (1 << 11), */ + CPUCFGR_EVBARP =3D (1 << 12), + /* CPUCFGR_ISRP =3D (1 << 13), */ + /* CPUCFGR_AECSRP =3D (1 << 14), */ }; =20 /* DMMU configure register */ @@ -200,6 +205,7 @@ enum { OPENRISC_FEATURE_OF32S =3D (1 << 7), OPENRISC_FEATURE_OF64S =3D (1 << 8), OPENRISC_FEATURE_OV64S =3D (1 << 9), + OPENRISC_FEATURE_EVBAR =3D (1 << 12), }; =20 /* Tick Timer Mode Register */ @@ -289,6 +295,7 @@ typedef struct CPUOpenRISCState { uint32_t dmmucfgr; /* DMMU configure register */ uint32_t immucfgr; /* IMMU configure register */ uint32_t esr; /* Exception supervisor register */ + uint32_t evbar; /* Exception vector base address register */ uint32_t fpcsr; /* Float register */ float_status fp_status; =20 diff --git a/target/openrisc/interrupt.c b/target/openrisc/interrupt.c index a2eec6fb32..78f0ba9421 100644 --- a/target/openrisc/interrupt.c +++ b/target/openrisc/interrupt.c @@ -65,7 +65,11 @@ void openrisc_cpu_do_interrupt(CPUState *cs) env->lock_addr =3D -1; =20 if (cs->exception_index > 0 && cs->exception_index < EXCP_NR) { - env->pc =3D (cs->exception_index << 8); + hwaddr vect_pc =3D cs->exception_index << 8; + if (env->cpucfgr & CPUCFGR_EVBARP) { + vect_pc |=3D env->evbar; + } + env->pc =3D vect_pc; } else { cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index); } diff --git a/target/openrisc/sys_helper.c b/target/openrisc/sys_helper.c index 60c3193656..6ba816249b 100644 --- a/target/openrisc/sys_helper.c +++ b/target/openrisc/sys_helper.c @@ -39,6 +39,10 @@ void HELPER(mtspr)(CPUOpenRISCState *env, env->vr =3D rb; break; =20 + case TO_SPR(0, 11): /* EVBAR */ + env->evbar =3D rb; + break; + case TO_SPR(0, 16): /* NPC */ cpu_restore_state(cs, GETPC()); /* ??? Mirror or1ksim in not trashing delayed branch state @@ -206,6 +210,9 @@ target_ulong HELPER(mfspr)(CPUOpenRISCState *env, case TO_SPR(0, 4): /* IMMUCFGR */ return env->immucfgr; =20 + case TO_SPR(0, 11): /* EVBAR */ + return env->evbar; + case TO_SPR(0, 16): /* NPC (equals PC) */ cpu_restore_state(cs, GETPC()); return env->pc; --=20 2.12.1 From nobody Sat May 4 05:05:13 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; dkim=fail spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1492496398786657.5944756885206; Mon, 17 Apr 2017 23:19:58 -0700 (PDT) Received: from localhost ([::1]:40245 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1d0MUW-0005P3-Kz for importer@patchew.org; Tue, 18 Apr 2017 02:19:56 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:56737) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1d0MSd-0004Pd-NY for qemu-devel@nongnu.org; Tue, 18 Apr 2017 02:18:00 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1d0MSa-0004w8-Hy for qemu-devel@nongnu.org; Tue, 18 Apr 2017 02:17:59 -0400 Received: from mail-pf0-x22a.google.com ([2607:f8b0:400e:c00::22a]:34239) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1d0MSa-0004w0-C2 for qemu-devel@nongnu.org; Tue, 18 Apr 2017 02:17:56 -0400 Received: by mail-pf0-x22a.google.com with SMTP id c198so76057926pfc.1 for ; Mon, 17 Apr 2017 23:17:56 -0700 (PDT) Received: from tansell-z840-l.syd.corp.google.com ([100.64.125.243]) by smtp.gmail.com with ESMTPSA id e131sm15538458pfg.10.2017.04.17.23.17.52 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 17 Apr 2017 23:17:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mithis.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=UtDn17RrcAV5iBZ4y2PAsx8choiULHG/iv3YsNIcmoI=; b=lj5gRJacRnk92zgL1tGX7bsJ0pno4ICo4+/7W6bDl4t5/3jS/XNcNcKKguK0c+L9uY KV5WL3zkhlUpSWzjbFlOj6xOB87K5ujAj3IP1//xZ2HihSidzJ6IenGH0iE6X+3vJmRP 6PQxtdTr6bZfKerJmgQxJ9JP759fxhThnAD8g= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=UtDn17RrcAV5iBZ4y2PAsx8choiULHG/iv3YsNIcmoI=; b=GSEqpHkOc6gOTBGJZ4kGbaoY8rViCn45wt0MEclo2b6taIzUK031t/9YwyzaWVdZeg e8vacqZi47LWvONoWJFUitM2dLOwW7gtXYLjpzBLpfe/m0mgQqCeDO0i8BQvjwRdT99o rdZl6UmWWgJ8afhaR7IC6bDOBrTEyoCJ1V5ugTArPrKVIRd+xm6cQtQlJO9SyTfXNxPU 9uZFwOhlYt4WSR4n+pWSxP9MVayYwJjgtfLWso6SSqe37ncij/pPWLg4Agm1rIhDu8Ec kdWgw7lgR4xnSQ8Rvwz3VWBVz/OBd8s3IDjB0NMLufAkjedPBte2Beg6JJiy8qyWa3Tl I2ZQ== X-Gm-Message-State: AN3rC/73ThVdWNVJ1K2I4kRoYgHWQAN9/i1VK+IiZohIjiZ34D+JIfv5 8QSKVJglWeyccrbV8MyTRA== X-Received: by 10.98.155.206 with SMTP id e75mr16441489pfk.24.1492496275336; Mon, 17 Apr 2017 23:17:55 -0700 (PDT) From: Tim 'mithro' Ansell To: qemu-devel@nongnu.org Date: Tue, 18 Apr 2017 16:15:51 +1000 Message-Id: <20170418061551.196582-3-mithro@mithis.com> X-Mailer: git-send-email 2.12.2.762.g0e3151a226-goog In-Reply-To: <20170418061551.196582-1-mithro@mithis.com> References: <20170418061551.196582-1-mithro@mithis.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::22a Subject: [Qemu-devel] [PATCH 2/2] target/openrisc: Implement EPH bit X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: shorne@gmail.com, Jia Liu , Tim 'mithro' Ansell Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Exception Prefix High (EPH) control bit of the Supervision Register (SR). The significant bits (31-12) of the vector offset address for each exception depend on the setting of the Supervision Register (SR)'s EPH bit and the Exception Vector Base Address Register (EVBAR). If SR[EPH] is set, the vector offset is logically ORed with the offset 0xF0000000. This means if EPH is; * 0 - Exceptions vectors start at EVBAR * 1 - Exception vectors start at EVBAR | 0xF0000000 Signed-off-by: Tim 'mithro' Ansell Acked-by: Stafford Horne --- target/openrisc/interrupt.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/target/openrisc/interrupt.c b/target/openrisc/interrupt.c index 78f0ba9421..2c91fab380 100644 --- a/target/openrisc/interrupt.c +++ b/target/openrisc/interrupt.c @@ -69,6 +69,9 @@ void openrisc_cpu_do_interrupt(CPUState *cs) if (env->cpucfgr & CPUCFGR_EVBARP) { vect_pc |=3D env->evbar; } + if (env->sr & SR_EPH) { + vect_pc |=3D 0xf0000000; + } env->pc =3D vect_pc; } else { cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index); --=20 2.12.1