[v2] target-arm: Check undefined opcodes for SWP in A32 decoder

[Qemu-devel] [PATCH v2] target-arm: Check undefined opcodes for SWP in A32 decoder

Onur Sahin posted 1 patch 6 years ago

Diff against v1
Download mbox

Patches applied successfully (tree, apply log)
git fetch https://github.com/patchew-project/qemu tags/patchew/1521841386-27498-1-git-send-email-onursahin08@gmail.com

Test checkpatch passed

Test docker-build@min-glib passed

Test docker-mingw@fedora passed

Test docker-quick@centos6 failed

Test s390x passed

target/arm/translate.c | 9 +++++++--
1 file changed, 7 insertions(+), 2 deletions(-)

Expand all Fold all

[Qemu-devel] [PATCH v2] target-arm: Check undefined opcodes for SWP in A32 decoder

Posted by Onur Sahin 6 years ago

Thanks for the feedback Peter. Removing the redundant check on bit
23 and adding checks for the "should be" bits as well (bits [11:8]).

The following patch should make sure we are not treating
architecturally Undefined instructions as a SWP, by verifying
the opcodes as per section A8.8.229 of ARMv7-A specification.

Best,
Onur

Signed-off-by: Onur Sahin <onursahin08@gmail.com>
---
 target/arm/translate.c | 9 +++++++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/target/arm/translate.c b/target/arm/translate.c
index ba6ab7d..1fb0b8f 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -9227,11 +9227,14 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
                             }
                         }
                         tcg_temp_free_i32(addr);
-                    } else {
+                    } else if ((insn & 0x00300f00) == 0) {
+                        /* 0bcccc_0001_0x00_xxxx_xxxx_0000_1001_xxxx
+                        *  - SWP, SWPB
+                        */
+
                         TCGv taddr;
                         TCGMemOp opc = s->be_data;
 
-                        /* SWP instruction */
                         rm = (insn) & 0xf;
 
                         if (insn & (1 << 22)) {
@@ -9249,6 +9252,8 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
                                                 get_mem_index(s), opc);
                         tcg_temp_free(taddr);
                         store_reg(s, rd, tmp);
+                    } else {
+                        goto illegal_op;
                     }
                 }
             } else {
-- 
1.8.3.1

Re: [Qemu-devel] [PATCH v2] target-arm: Check undefined opcodes for SWP in A32 decoder

Posted by Peter Maydell 6 years ago

On 23 March 2018 at 21:43, Onur Sahin <onursahin08@gmail.com> wrote:
> Thanks for the feedback Peter. Removing the redundant check on bit
> 23 and adding checks for the "should be" bits as well (bits [11:8]).
>
> The following patch should make sure we are not treating
> architecturally Undefined instructions as a SWP, by verifying
> the opcodes as per section A8.8.229 of ARMv7-A specification.
>
> Best,
> Onur
>
> Signed-off-by: Onur Sahin <onursahin08@gmail.com>
> ---

Thanks; I've applied this patch to target-arm.next for 2.12,
with some minor tweaks to the commit message.

-- PMM