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X-Received-From: 2607:f8b0:400d:c09::242 Subject: [Qemu-devel] [PATCH v2] target-arm: Check undefined opcodes for SWP in A32 decoder X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, Onur Sahin Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Thanks for the feedback Peter. Removing the redundant check on bit 23 and adding checks for the "should be" bits as well (bits [11:8]). The following patch should make sure we are not treating architecturally Undefined instructions as a SWP, by verifying the opcodes as per section A8.8.229 of ARMv7-A specification. Best, Onur Signed-off-by: Onur Sahin --- target/arm/translate.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index ba6ab7d..1fb0b8f 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -9227,11 +9227,14 @@ static void disas_arm_insn(DisasContext *s, unsigne= d int insn) } } tcg_temp_free_i32(addr); - } else { + } else if ((insn & 0x00300f00) =3D=3D 0) { + /* 0bcccc_0001_0x00_xxxx_xxxx_0000_1001_xxxx + * - SWP, SWPB + */ + TCGv taddr; TCGMemOp opc =3D s->be_data; =20 - /* SWP instruction */ rm =3D (insn) & 0xf; =20 if (insn & (1 << 22)) { @@ -9249,6 +9252,8 @@ static void disas_arm_insn(DisasContext *s, unsigned = int insn) get_mem_index(s), opc); tcg_temp_free(taddr); store_reg(s, rd, tmp); + } else { + goto illegal_op; } } } else { --=20 1.8.3.1