MAINTAINERS | 11 + Makefile.objs | 1 + arch_init.c | 2 + configure | 11 + cpus.c | 6 + default-configs/riscv32-linux-user.mak | 1 + default-configs/riscv32-softmmu.mak | 4 + default-configs/riscv64-linux-user.mak | 1 + default-configs/riscv64-softmmu.mak | 4 + disas.c | 2 + disas/Makefile.objs | 1 + disas/riscv.c | 3054 ++++++++++++++++++++++++++++++++ fpu/softfloat-specialize.h | 7 +- hw/riscv/Makefile.objs | 12 + hw/riscv/riscv_elf.c | 244 +++ hw/riscv/riscv_hart.c | 95 + hw/riscv/riscv_htif.c | 373 ++++ hw/riscv/sifive_clint.c | 312 ++++ hw/riscv/sifive_e300.c | 232 +++ hw/riscv/sifive_plic.c | 554 ++++++ hw/riscv/sifive_prci.c | 107 ++ hw/riscv/sifive_u500.c | 338 ++++ hw/riscv/sifive_uart.c | 182 ++ hw/riscv/spike_v1_09.c | 207 +++ hw/riscv/spike_v1_10.c | 281 +++ hw/riscv/virt.c | 364 ++++ include/disas/bfd.h | 2 + include/elf.h | 2 + include/hw/riscv/riscv_elf.h | 69 + include/hw/riscv/riscv_hart.h | 45 + include/hw/riscv/riscv_htif.h | 62 + include/hw/riscv/sifive_clint.h | 56 + include/hw/riscv/sifive_e300.h | 79 + include/hw/riscv/sifive_plic.h | 91 + include/hw/riscv/sifive_prci.h | 43 + include/hw/riscv/sifive_u500.h | 69 + include/hw/riscv/sifive_uart.h | 76 + include/hw/riscv/spike.h | 51 + include/hw/riscv/virt.h | 73 + include/sysemu/arch_init.h | 1 + linux-user/elfload.c | 22 + linux-user/main.c | 114 ++ linux-user/riscv/syscall_nr.h | 275 +++ linux-user/riscv/target_cpu.h | 18 + linux-user/riscv/target_signal.h | 23 + linux-user/riscv/target_structs.h | 46 + linux-user/riscv/target_syscall.h | 56 + linux-user/riscv/termbits.h | 220 +++ linux-user/signal.c | 203 ++- linux-user/syscall.c | 2 + linux-user/syscall_defs.h | 13 +- qapi-schema.json | 14 +- scripts/qemu-binfmt-conf.sh | 13 +- target/riscv/Makefile.objs | 2 + target/riscv/cpu.c | 391 ++++ target/riscv/cpu.h | 271 +++ target/riscv/cpu_bits.h | 417 +++++ target/riscv/cpu_user.h | 26 + target/riscv/fpu_helper.c | 591 ++++++ target/riscv/gdbstub.c | 59 + target/riscv/helper.c | 499 ++++++ target/riscv/helper.h | 78 + target/riscv/instmap.h | 377 ++++ target/riscv/op_helper.c | 682 +++++++ target/riscv/pmp.c | 386 ++++ target/riscv/pmp.h | 70 + target/riscv/trace-events | 1 + target/riscv/translate.c | 1982 +++++++++++++++++++++ target/riscv/user_atomic.c | 291 +++ 69 files changed, 14256 insertions(+), 11 deletions(-) create mode 100644 default-configs/riscv32-linux-user.mak create mode 100644 default-configs/riscv32-softmmu.mak create mode 100644 default-configs/riscv64-linux-user.mak create mode 100644 default-configs/riscv64-softmmu.mak create mode 100644 disas/riscv.c create mode 100644 hw/riscv/Makefile.objs create mode 100644 hw/riscv/riscv_elf.c create mode 100644 hw/riscv/riscv_hart.c create mode 100644 hw/riscv/riscv_htif.c create mode 100644 hw/riscv/sifive_clint.c create mode 100644 hw/riscv/sifive_e300.c create mode 100644 hw/riscv/sifive_plic.c create mode 100644 hw/riscv/sifive_prci.c create mode 100644 hw/riscv/sifive_u500.c create mode 100644 hw/riscv/sifive_uart.c create mode 100644 hw/riscv/spike_v1_09.c create mode 100644 hw/riscv/spike_v1_10.c create mode 100644 hw/riscv/virt.c create mode 100644 include/hw/riscv/riscv_elf.h create mode 100644 include/hw/riscv/riscv_hart.h create mode 100644 include/hw/riscv/riscv_htif.h create mode 100644 include/hw/riscv/sifive_clint.h create mode 100644 include/hw/riscv/sifive_e300.h create mode 100644 include/hw/riscv/sifive_plic.h create mode 100644 include/hw/riscv/sifive_prci.h create mode 100644 include/hw/riscv/sifive_u500.h create mode 100644 include/hw/riscv/sifive_uart.h create mode 100644 include/hw/riscv/spike.h create mode 100644 include/hw/riscv/virt.h create mode 100644 linux-user/riscv/syscall_nr.h create mode 100644 linux-user/riscv/target_cpu.h create mode 100644 linux-user/riscv/target_signal.h create mode 100644 linux-user/riscv/target_structs.h create mode 100644 linux-user/riscv/target_syscall.h create mode 100644 linux-user/riscv/termbits.h create mode 100644 target/riscv/Makefile.objs create mode 100644 target/riscv/cpu.c create mode 100644 target/riscv/cpu.h create mode 100644 target/riscv/cpu_bits.h create mode 100644 target/riscv/cpu_user.h create mode 100644 target/riscv/fpu_helper.c create mode 100644 target/riscv/gdbstub.c create mode 100644 target/riscv/helper.c create mode 100644 target/riscv/helper.h create mode 100644 target/riscv/instmap.h create mode 100644 target/riscv/op_helper.c create mode 100644 target/riscv/pmp.c create mode 100644 target/riscv/pmp.h create mode 100644 target/riscv/trace-events create mode 100644 target/riscv/translate.c create mode 100644 target/riscv/user_atomic.c
QEMU RISC-V Emulation Support (RV64GC, RV32GC) This patch series has major clean ups to target/riscv. There may be some feedback that has been missed however the changelog is growing quite large so we have decided to respin the patch series. No new features have been added however a number of bugs have been fixed. The git tree for this v3 patch series (squashed and rebased): - https://github.com/riscv/riscv-qemu/tree/qemu-upstream-v3 The git tree for the v2 patch series with full review commit history: - https://github.com/riscv/riscv-qemu/tree/qemu-upstream-v2 The git tree for the v1 patch series with full review commit history: - https://github.com/riscv/riscv-qemu/tree/qemu-upstream-v1 We're adding Palmer Dabbelt as a maintainer so that we have at least two full-time RISC-V developers available to work on the port. *** Known Issues *** - Disassembler has some checkpatch warnings for the sake of code brevity - scripts/qemu-binfmt-conf.sh has checkpatch warnings due to line length - PMP (Physical Memory Protection) is as-of-yet unused and needs testing *** Changelog *** v3 - Fix indentation in PMP and HTIF debug macros - Fix disassembler checkpatch open brace '{' on next line errors - NOTE: the other checkpatch issues have been reviewed previously v2 - Remove redundant NULL terminators from disassembler register arrays - Change disassembler register name arrays to const - Refine disassembler internal function names - Update dates in disassembler copyright message - Remove #ifdef CONFIG_USER_ONLY version of cpu_has_work - Use ULL suffix on 64-bit constants - Move riscv_cpu_mmu_index from cpu.h to helper.c - Move riscv_cpu_hw_interrupts_pending from cpu.h to helper.c - Remove redundant TARGET_HAS_ICE from cpu.h - Use qemu_irq instead of void* for irq definition in cpu.h - Remove duplicate typedef from struct CPURISCVState - Remove redundant g_strdup from cpu_register - Remove redundant tlb_flush from riscv_cpu_reset - Remove redundant mode calculation from get_physical_address - Remove redundant debug mode printf and dcsr comment - Remove redundant clearing of MSB for bare physical addresses - Use g_assert_not_reached for invalid mode in get_physical_address - Use g_assert_not_reached for unreachable checks in get_physical_address - Use g_assert_not_reached for unreachable type in raise_mmu_exception - Return exception instead of aborting for misaligned fetches - Move exception defines from cpu.h to cpu_bits.h - Remove redundant breakpoint control definitions from cpu_bits.h - Implement riscv_cpu_unassigned_access exception handling - Log and raise exceptions for unimplemented CSRs - Match Spike HTIF exit behavior - don’t print TEST-PASSED - Make frm,fflags,fcsr writes trap when mstatus.FS is clear - Use g_assert_not_reached for unreachable invalid mode - Make hret,uret,dret generate illegal instructions - Move riscv_cpu_dump_state and int/fpr regnames to cpu.c - Lift interrupt flag and mask into constants in cpu_bits.h - Change trap debugging to use qemu_log_mask LOG_TRACE - Change CSR debugging to use qemu_log_mask LOG_TRACE - Change PMP debugging to use qemu_log_mask LOG_TRACE - Remove commented code from pmp.c - Change CpuInfoRISCV qapi schema docs to Since 2.12 - Change RV feature macro to use target_ulong cast - Remove riscv_feature and instead use misa extension flags - Make riscv_flush_icache_syscall a no-op - Undo checkpatch whitespace fixes in unrelated linux-user code - Remove redudant constants and tidy up cpu_bits.h - Make helper_fence_i a no-op - Move include "exec/cpu-all" to end of cpu.h - Rename set_privilege to riscv_set_mode - Move redundant forward declaration for cpu_riscv_translate_address - Remove TCGV_UNUSED from riscv_translate_init - Add comment to pmp.c stating the code is untested and currently unused - Use ctz to simplify decoding of PMP NAPOT address ranges - Change pmp_is_in_range to use than equal for end addresses - Fix off by one error in pmp_update_rule - Rearrange PMP_DEBUG so that formatting is compile-time checked - Rearrange trap debugging so that formatting is compile-time checked - Rearrange PLIC debugging so that formatting is compile-time checked - Use qemu_log/qemu_log_mask for HTIF logging and debugging - Move exception and interrupt names into cpu.c - Add Palmer Dabbelt as a RISC-V Maintainer - Rebase against current qemu master branch v1 - initial version based on forward port from riscv-qemu repository *** Background *** "RISC-V is an open, free ISA enabling a new era of processor innovation through open standard collaboration. Born in academia and research, RISC-V ISA delivers a new level of free, extensible software and hardware freedom on architecture, paving the way for the next 50 years of computing design and innovation." The QEMU RISC-V port has been developed and maintained out-of-tree for several years by Sagar Karandikar and Bastian Koppelmann. The RISC-V Privileged specification has evolved substantially over this period but has recently been solidifying. The RISC-V Base ISA has been frozon for some time and the Privileged ISA, GCC toolchain and Linux ABI are now quite stable. I have recently joined Sagar and Bastian as a RISC-V QEMU Maintainer and hope to support upstreaming the port. There are multiple vendors taping out, preparing to ship, or shipping silicon that implements the RISC-V Privileged ISA Version 1.10. There are also several RISC-V Soft-IP cores implementing Privileged ISA Version 1.10 that run on FPGA such as SiFive's Freedom U500 Platform and the U54‑MC RISC-V Core IP, among many more implementations from a variety of vendors. See https://riscv.org/ for more details. RISC-V support was upstreamed in binutils 2.28 and GCC 7.1 in the first half of 2016. RISC-V support is now available in LLVM top-of-tree and the RISC-V Linux port was accepted into Linux 4.15-rc1 late last year and will be available in the upcoming Linux 4.15 release. RISC-V GLIBC patches are currently under review and it is hoped that RISC-V support will be added in the GLIBC 2.27 release. We believe it is timely to submit the RISC-V QEMU port for upstream review with the goal of incorporating RISC-V support into the upcoming QEMU 2.12 release. The RISC-V QEMU port is still under active development, mostly with respect to device emulation, the addition of Hypervisor support as specified in the RISC-V Draft Privileged ISA Version 1.11, and Vector support once the first draft is finalized later this year. We believe now is the appropriate time for RISC-V QEMU development to be carried out in the main QEMU repository as the code will benefit from more rigorous review. The RISC-V QEMU port currently supports all the ISA extensions that have been finalized and frozen in the Base ISA. Blog post about recent additions to RISC-V QEMU: https://goo.gl/fJ4zgk The RISC-V QEMU wiki: https://github.com/riscv/riscv-qemu/wiki Instructions for building a busybox+dropbear root image, BBL (Berkeley Boot Loader) and linux kernel image for use with the RISC-V QEMU 'virt' machine: https://github.com/michaeljclark/busybear-linux *** Overview *** The RISC-V QEMU port implements the following specifications: - RISC-V Instruction Set Manual Volume I: User-Level ISA Version 2.2 - RISC-V Instruction Set Manual Volume II: Privileged ISA Version 1.9.1 - RISC-V Instruction Set Manual Volume II: Privileged ISA Version 1.10 The RISC-V QEMU port supports the following instruction set extensions: - RV32GC with Supervisor-mode and User-mode (RV32IMAFDCSU) - RV64GC with Supervisor-mode and User-mode (RV64IMAFDCSU) The RISC-V QEMU port adds the following targets to QEMU: - riscv32-softmmu - riscv64-softmmu - riscv32-linux-user - riscv64-linux-user The RISC-V QEMU port supports the following hardware: - HTIF Console (Host Target Interface) - SiFive CLINT (Core Local Interruptor) for Timer interrupts and IPIs - SiFive PLIC (Platform Level Interrupt Controller) - SiFive UART, PRCI, AON, PWM, QSPI support is partially implemented - VirtIO MMIO (GPEX PCI support will be added in a future patch) - Generic 16550A UART emulation using 'hw/char/serial.c' - Experimental SMP support (PLIC and CLINT) on the 'virt' machine The RISC-V QEMU full system emulator supports 5 machines: - 'spike_v1.9'; CLINT, PLIC, HTIF console, config-string, Priv v1.9.1 - 'spike_v1.10'; CLINT, PLIC, HTIF console, device-tree, Priv v1.10 - 'virt'; CLINT, PLIC, 16550A UART, VirtIO, device-tree, Priv v1.10 - 'sifive_e300'; CLINT, PLIC, SiFive UART, HiFive1 compat, Priv v1.10 - 'sifive_u500'; CLINT, PLIC, SiFive UART, device-tree, Priv v1.10 This is a list of RISC-V QEMU Port Contributors: - Alex Suykov - Antony Pavlov - Bastian Koppelmann - Bruce Hoult - Chih-Min Chao - Daire McNamara - David Abdurachmanov - Ivan Griffin - Kito Cheng - Michael Clark - Palmer Dabbelt - Sagar Karandikar - Stefan O'Rear Notes: - contributor email addresses available off-list on request. - checkpatch has been run on all 21 patches. - checkpatch exceptions are noted in 2 patches that have errors. - tested linux on 'spike_v1.9', 'spike_v1.10' and 'virt' machines - passes "make check" on full build for all targets This patch series includes the following patches: Michael Clark (21): RISC-V Maintainers RISC-V ELF Machine Definition RISC-V CPU Core Definition RISC-V Disassembler RISC-V CPU Helpers RISC-V FPU Support RISC-V GDB Stub RISC-V TCG Code Generation RISC-V Physical Memory Protection RISC-V Linux User Emulation RISC-V HTIF Console RISC-V HART Array SiFive RISC-V CLINT Block SiFive RISC-V PLIC Block RISC-V Spike Machines RISC-V VirtIO Machine SiFive RISC-V UART Device SiFive RISC-V PRCI Block SiFive Freedom E300 RISC-V Machine SiFive Freedom U500 RISC-V Machine RISC-V Build Infrastructure MAINTAINERS | 11 + Makefile.objs | 1 + arch_init.c | 2 + configure | 11 + cpus.c | 6 + default-configs/riscv32-linux-user.mak | 1 + default-configs/riscv32-softmmu.mak | 4 + default-configs/riscv64-linux-user.mak | 1 + default-configs/riscv64-softmmu.mak | 4 + disas.c | 2 + disas/Makefile.objs | 1 + disas/riscv.c | 3054 ++++++++++++++++++++++++++++++++ fpu/softfloat-specialize.h | 7 +- hw/riscv/Makefile.objs | 12 + hw/riscv/riscv_elf.c | 244 +++ hw/riscv/riscv_hart.c | 95 + hw/riscv/riscv_htif.c | 373 ++++ hw/riscv/sifive_clint.c | 312 ++++ hw/riscv/sifive_e300.c | 232 +++ hw/riscv/sifive_plic.c | 554 ++++++ hw/riscv/sifive_prci.c | 107 ++ hw/riscv/sifive_u500.c | 338 ++++ hw/riscv/sifive_uart.c | 182 ++ hw/riscv/spike_v1_09.c | 207 +++ hw/riscv/spike_v1_10.c | 281 +++ hw/riscv/virt.c | 364 ++++ include/disas/bfd.h | 2 + include/elf.h | 2 + include/hw/riscv/riscv_elf.h | 69 + include/hw/riscv/riscv_hart.h | 45 + include/hw/riscv/riscv_htif.h | 62 + include/hw/riscv/sifive_clint.h | 56 + include/hw/riscv/sifive_e300.h | 79 + include/hw/riscv/sifive_plic.h | 91 + include/hw/riscv/sifive_prci.h | 43 + include/hw/riscv/sifive_u500.h | 69 + include/hw/riscv/sifive_uart.h | 76 + include/hw/riscv/spike.h | 51 + include/hw/riscv/virt.h | 73 + include/sysemu/arch_init.h | 1 + linux-user/elfload.c | 22 + linux-user/main.c | 114 ++ linux-user/riscv/syscall_nr.h | 275 +++ linux-user/riscv/target_cpu.h | 18 + linux-user/riscv/target_signal.h | 23 + linux-user/riscv/target_structs.h | 46 + linux-user/riscv/target_syscall.h | 56 + linux-user/riscv/termbits.h | 220 +++ linux-user/signal.c | 203 ++- linux-user/syscall.c | 2 + linux-user/syscall_defs.h | 13 +- qapi-schema.json | 14 +- scripts/qemu-binfmt-conf.sh | 13 +- target/riscv/Makefile.objs | 2 + target/riscv/cpu.c | 391 ++++ target/riscv/cpu.h | 271 +++ target/riscv/cpu_bits.h | 417 +++++ target/riscv/cpu_user.h | 26 + target/riscv/fpu_helper.c | 591 ++++++ target/riscv/gdbstub.c | 59 + target/riscv/helper.c | 499 ++++++ target/riscv/helper.h | 78 + target/riscv/instmap.h | 377 ++++ target/riscv/op_helper.c | 682 +++++++ target/riscv/pmp.c | 386 ++++ target/riscv/pmp.h | 70 + target/riscv/trace-events | 1 + target/riscv/translate.c | 1982 +++++++++++++++++++++ target/riscv/user_atomic.c | 291 +++ 69 files changed, 14256 insertions(+), 11 deletions(-) create mode 100644 default-configs/riscv32-linux-user.mak create mode 100644 default-configs/riscv32-softmmu.mak create mode 100644 default-configs/riscv64-linux-user.mak create mode 100644 default-configs/riscv64-softmmu.mak create mode 100644 disas/riscv.c create mode 100644 hw/riscv/Makefile.objs create mode 100644 hw/riscv/riscv_elf.c create mode 100644 hw/riscv/riscv_hart.c create mode 100644 hw/riscv/riscv_htif.c create mode 100644 hw/riscv/sifive_clint.c create mode 100644 hw/riscv/sifive_e300.c create mode 100644 hw/riscv/sifive_plic.c create mode 100644 hw/riscv/sifive_prci.c create mode 100644 hw/riscv/sifive_u500.c create mode 100644 hw/riscv/sifive_uart.c create mode 100644 hw/riscv/spike_v1_09.c create mode 100644 hw/riscv/spike_v1_10.c create mode 100644 hw/riscv/virt.c create mode 100644 include/hw/riscv/riscv_elf.h create mode 100644 include/hw/riscv/riscv_hart.h create mode 100644 include/hw/riscv/riscv_htif.h create mode 100644 include/hw/riscv/sifive_clint.h create mode 100644 include/hw/riscv/sifive_e300.h create mode 100644 include/hw/riscv/sifive_plic.h create mode 100644 include/hw/riscv/sifive_prci.h create mode 100644 include/hw/riscv/sifive_u500.h create mode 100644 include/hw/riscv/sifive_uart.h create mode 100644 include/hw/riscv/spike.h create mode 100644 include/hw/riscv/virt.h create mode 100644 linux-user/riscv/syscall_nr.h create mode 100644 linux-user/riscv/target_cpu.h create mode 100644 linux-user/riscv/target_signal.h create mode 100644 linux-user/riscv/target_structs.h create mode 100644 linux-user/riscv/target_syscall.h create mode 100644 linux-user/riscv/termbits.h create mode 100644 target/riscv/Makefile.objs create mode 100644 target/riscv/cpu.c create mode 100644 target/riscv/cpu.h create mode 100644 target/riscv/cpu_bits.h create mode 100644 target/riscv/cpu_user.h create mode 100644 target/riscv/fpu_helper.c create mode 100644 target/riscv/gdbstub.c create mode 100644 target/riscv/helper.c create mode 100644 target/riscv/helper.h create mode 100644 target/riscv/instmap.h create mode 100644 target/riscv/op_helper.c create mode 100644 target/riscv/pmp.c create mode 100644 target/riscv/pmp.h create mode 100644 target/riscv/trace-events create mode 100644 target/riscv/translate.c create mode 100644 target/riscv/user_atomic.c -- 2.7.0
Hi, This series seems to have some coding style problems. See output below for more information: Type: series Message-id: 1515637324-96034-1-git-send-email-mjc@sifive.com Subject: [Qemu-devel] [PATCH v3 00/21] RISC-V QEMU Port Submission v3 === TEST SCRIPT BEGIN === #!/bin/bash BASE=base n=1 total=$(git log --oneline $BASE.. | wc -l) failed=0 git config --local diff.renamelimit 0 git config --local diff.renames True commits="$(git log --format=%H --reverse $BASE..)" for c in $commits; do echo "Checking PATCH $n/$total: $(git log -n 1 --format=%s $c)..." if ! git show $c --format=email | ./scripts/checkpatch.pl --mailback -; then failed=1 echo fi n=$((n+1)) done exit $failed === TEST SCRIPT END === Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384 Switched to a new branch 'test' 7f192f5ceb RISC-V Build Infrastructure 91f292f2cc SiFive Freedom U500 RISC-V Machine a80f42638c SiFive Freedom E300 RISC-V Machine c2519d2f95 SiFive RISC-V PRCI Block d22164e263 SiFive RISC-V UART Device 319d67278f RISC-V VirtIO Machine 0d1f8ea1fd RISC-V Spike Machines 5d048d84c6 SiFive RISC-V PLIC Block 87dfc5ca6a SiFive RISC-V CLINT Block ac1e42ddb2 RISC-V HART Array 63b446e985 RISC-V HTIF Console 1397d2776b RISC-V Linux User Emulation d2512fa8ad RISC-V Physical Memory Protection 675d33bbe3 RISC-V TCG Code Generation a5ea9ea97f RISC-V GDB Stub a170177cab RISC-V FPU Support 61678e3f7e RISC-V CPU Helpers 64b8c82021 RISC-V Disassembler 3b561b5019 RISC-V CPU Core Definition 3cb33c620c RISC-V ELF Machine Definition 806fcf588f RISC-V Maintainers === OUTPUT BEGIN === Checking PATCH 1/21: RISC-V Maintainers... Checking PATCH 2/21: RISC-V ELF Machine Definition... Checking PATCH 3/21: RISC-V CPU Core Definition... Checking PATCH 4/21: RISC-V Disassembler... WARNING: line over 80 characters #653: FILE: disas/riscv.c:603: +static const rvc_constraint rvcc_jalr[] = { rvc_rd_eq_ra, rvc_imm_eq_zero, rvc_end }; ERROR: line over 90 characters #654: FILE: disas/riscv.c:604: +static const rvc_constraint rvcc_nop[] = { rvc_rd_eq_x0, rvc_rs1_eq_x0, rvc_imm_eq_zero, rvc_end }; WARNING: line over 80 characters #684: FILE: disas/riscv.c:634: +static const rvc_constraint rvcc_ret[] = { rvc_rd_eq_x0, rvc_rs1_eq_ra, rvc_end }; WARNING: line over 80 characters #685: FILE: disas/riscv.c:635: +static const rvc_constraint rvcc_jr[] = { rvc_rd_eq_x0, rvc_imm_eq_zero, rvc_end }; WARNING: line over 80 characters #686: FILE: disas/riscv.c:636: +static const rvc_constraint rvcc_rdcycle[] = { rvc_rs1_eq_x0, rvc_csr_eq_0xc00, rvc_end }; WARNING: line over 80 characters #687: FILE: disas/riscv.c:637: +static const rvc_constraint rvcc_rdtime[] = { rvc_rs1_eq_x0, rvc_csr_eq_0xc01, rvc_end }; ERROR: line over 90 characters #688: FILE: disas/riscv.c:638: +static const rvc_constraint rvcc_rdinstret[] = { rvc_rs1_eq_x0, rvc_csr_eq_0xc02, rvc_end }; ERROR: line over 90 characters #689: FILE: disas/riscv.c:639: +static const rvc_constraint rvcc_rdcycleh[] = { rvc_rs1_eq_x0, rvc_csr_eq_0xc80, rvc_end }; WARNING: line over 80 characters #690: FILE: disas/riscv.c:640: +static const rvc_constraint rvcc_rdtimeh[] = { rvc_rs1_eq_x0, rvc_csr_eq_0xc81, rvc_end }; ERROR: line over 90 characters #691: FILE: disas/riscv.c:641: +static const rvc_constraint rvcc_rdinstreth[] = { rvc_rs1_eq_x0, rvc_csr_eq_0xc80, rvc_end }; WARNING: line over 80 characters #692: FILE: disas/riscv.c:642: +static const rvc_constraint rvcc_frcsr[] = { rvc_rs1_eq_x0, rvc_csr_eq_0x003, rvc_end }; WARNING: line over 80 characters #693: FILE: disas/riscv.c:643: +static const rvc_constraint rvcc_frrm[] = { rvc_rs1_eq_x0, rvc_csr_eq_0x002, rvc_end }; WARNING: line over 80 characters #694: FILE: disas/riscv.c:644: +static const rvc_constraint rvcc_frflags[] = { rvc_rs1_eq_x0, rvc_csr_eq_0x001, rvc_end }; ERROR: line over 90 characters #1093: FILE: disas/riscv.c:1043: + { "c.addi4spn", rv_codec_ciw_4spn, rv_fmt_rd_rs1_imm, NULL, rv_op_addi, rv_op_addi, rv_op_addi }, WARNING: line over 80 characters #1094: FILE: disas/riscv.c:1044: + { "c.fld", rv_codec_cl_ld, rv_fmt_frd_offset_rs1, NULL, rv_op_fld, rv_op_fld, 0 }, WARNING: line over 80 characters #1095: FILE: disas/riscv.c:1045: + { "c.lw", rv_codec_cl_lw, rv_fmt_rd_offset_rs1, NULL, rv_op_lw, rv_op_lw, rv_op_lw }, WARNING: line over 80 characters #1097: FILE: disas/riscv.c:1047: + { "c.fsd", rv_codec_cs_sd, rv_fmt_frs2_offset_rs1, NULL, rv_op_fsd, rv_op_fsd, 0 }, WARNING: line over 80 characters #1098: FILE: disas/riscv.c:1048: + { "c.sw", rv_codec_cs_sw, rv_fmt_rs2_offset_rs1, NULL, rv_op_sw, rv_op_sw, rv_op_sw }, WARNING: line over 80 characters #1100: FILE: disas/riscv.c:1050: + { "c.nop", rv_codec_ci_none, rv_fmt_none, NULL, rv_op_addi, rv_op_addi, rv_op_addi }, ERROR: line over 90 characters #1101: FILE: disas/riscv.c:1051: + { "c.addi", rv_codec_ci, rv_fmt_rd_rs1_imm, NULL, rv_op_addi, rv_op_addi, rv_op_addi }, ERROR: line over 90 characters #1103: FILE: disas/riscv.c:1053: + { "c.li", rv_codec_ci_li, rv_fmt_rd_rs1_imm, NULL, rv_op_addi, rv_op_addi, rv_op_addi }, ERROR: line over 90 characters #1104: FILE: disas/riscv.c:1054: + { "c.addi16sp", rv_codec_ci_16sp, rv_fmt_rd_rs1_imm, NULL, rv_op_addi, rv_op_addi, rv_op_addi }, WARNING: line over 80 characters #1105: FILE: disas/riscv.c:1055: + { "c.lui", rv_codec_ci_lui, rv_fmt_rd_imm, NULL, rv_op_lui, rv_op_lui, rv_op_lui }, ERROR: line over 90 characters #1106: FILE: disas/riscv.c:1056: + { "c.srli", rv_codec_cb_sh6, rv_fmt_rd_rs1_imm, NULL, rv_op_srli, rv_op_srli, rv_op_srli }, ERROR: line over 90 characters #1107: FILE: disas/riscv.c:1057: + { "c.srai", rv_codec_cb_sh6, rv_fmt_rd_rs1_imm, NULL, rv_op_srai, rv_op_srai, rv_op_srai }, ERROR: line over 90 characters #1108: FILE: disas/riscv.c:1058: + { "c.andi", rv_codec_cb_imm, rv_fmt_rd_rs1_imm, NULL, rv_op_andi, rv_op_andi, rv_op_andi }, WARNING: line over 80 characters #1109: FILE: disas/riscv.c:1059: + { "c.sub", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_sub, rv_op_sub, rv_op_sub }, WARNING: line over 80 characters #1110: FILE: disas/riscv.c:1060: + { "c.xor", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_xor, rv_op_xor, rv_op_xor }, WARNING: line over 80 characters #1111: FILE: disas/riscv.c:1061: + { "c.or", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_or, rv_op_or, rv_op_or }, WARNING: line over 80 characters #1112: FILE: disas/riscv.c:1062: + { "c.and", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_and, rv_op_and, rv_op_and }, ERROR: line over 90 characters #1113: FILE: disas/riscv.c:1063: + { "c.subw", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_subw, rv_op_subw, rv_op_subw }, ERROR: line over 90 characters #1114: FILE: disas/riscv.c:1064: + { "c.addw", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_addw, rv_op_addw, rv_op_addw }, WARNING: line over 80 characters #1115: FILE: disas/riscv.c:1065: + { "c.j", rv_codec_cj, rv_fmt_rd_offset, NULL, rv_op_jal, rv_op_jal, rv_op_jal }, ERROR: line over 90 characters #1116: FILE: disas/riscv.c:1066: + { "c.beqz", rv_codec_cb, rv_fmt_rs1_rs2_offset, NULL, rv_op_beq, rv_op_beq, rv_op_beq }, ERROR: line over 90 characters #1117: FILE: disas/riscv.c:1067: + { "c.bnez", rv_codec_cb, rv_fmt_rs1_rs2_offset, NULL, rv_op_bne, rv_op_bne, rv_op_bne }, ERROR: line over 90 characters #1118: FILE: disas/riscv.c:1068: + { "c.slli", rv_codec_ci_sh6, rv_fmt_rd_rs1_imm, NULL, rv_op_slli, rv_op_slli, rv_op_slli }, ERROR: line over 90 characters #1119: FILE: disas/riscv.c:1069: + { "c.fldsp", rv_codec_ci_ldsp, rv_fmt_frd_offset_rs1, NULL, rv_op_fld, rv_op_fld, rv_op_fld }, ERROR: line over 90 characters #1120: FILE: disas/riscv.c:1070: + { "c.lwsp", rv_codec_ci_lwsp, rv_fmt_rd_offset_rs1, NULL, rv_op_lw, rv_op_lw, rv_op_lw }, WARNING: line over 80 characters #1121: FILE: disas/riscv.c:1071: + { "c.flwsp", rv_codec_ci_lwsp, rv_fmt_frd_offset_rs1, NULL, rv_op_flw, 0, 0 }, ERROR: line over 90 characters #1122: FILE: disas/riscv.c:1072: + { "c.jr", rv_codec_cr_jr, rv_fmt_rd_rs1_offset, NULL, rv_op_jalr, rv_op_jalr, rv_op_jalr }, ERROR: line over 90 characters #1123: FILE: disas/riscv.c:1073: + { "c.mv", rv_codec_cr_mv, rv_fmt_rd_rs1_rs2, NULL, rv_op_addi, rv_op_addi, rv_op_addi }, ERROR: line over 90 characters #1124: FILE: disas/riscv.c:1074: + { "c.ebreak", rv_codec_ci_none, rv_fmt_none, NULL, rv_op_ebreak, rv_op_ebreak, rv_op_ebreak }, ERROR: line over 90 characters #1125: FILE: disas/riscv.c:1075: + { "c.jalr", rv_codec_cr_jalr, rv_fmt_rd_rs1_offset, NULL, rv_op_jalr, rv_op_jalr, rv_op_jalr }, WARNING: line over 80 characters #1126: FILE: disas/riscv.c:1076: + { "c.add", rv_codec_cr, rv_fmt_rd_rs1_rs2, NULL, rv_op_add, rv_op_add, rv_op_add }, ERROR: line over 90 characters #1127: FILE: disas/riscv.c:1077: + { "c.fsdsp", rv_codec_css_sdsp, rv_fmt_frs2_offset_rs1, NULL, rv_op_fsd, rv_op_fsd, rv_op_fsd }, ERROR: line over 90 characters #1128: FILE: disas/riscv.c:1078: + { "c.swsp", rv_codec_css_swsp, rv_fmt_rs2_offset_rs1, NULL, rv_op_sw, rv_op_sw, rv_op_sw }, WARNING: line over 80 characters #1129: FILE: disas/riscv.c:1079: + { "c.fswsp", rv_codec_css_swsp, rv_fmt_frs2_offset_rs1, NULL, rv_op_fsw, 0, 0 }, WARNING: line over 80 characters #1130: FILE: disas/riscv.c:1080: + { "c.ld", rv_codec_cl_ld, rv_fmt_rd_offset_rs1, NULL, 0, rv_op_ld, rv_op_ld }, WARNING: line over 80 characters #1131: FILE: disas/riscv.c:1081: + { "c.sd", rv_codec_cs_sd, rv_fmt_rs2_offset_rs1, NULL, 0, rv_op_sd, rv_op_sd }, WARNING: line over 80 characters #1132: FILE: disas/riscv.c:1082: + { "c.addiw", rv_codec_ci, rv_fmt_rd_rs1_imm, NULL, 0, rv_op_addiw, rv_op_addiw }, WARNING: line over 80 characters #1133: FILE: disas/riscv.c:1083: + { "c.ldsp", rv_codec_ci_ldsp, rv_fmt_rd_offset_rs1, NULL, 0, rv_op_ld, rv_op_ld }, WARNING: line over 80 characters #1134: FILE: disas/riscv.c:1084: + { "c.sdsp", rv_codec_css_sdsp, rv_fmt_rs2_offset_rs1, NULL, 0, rv_op_sd, rv_op_sd }, WARNING: line over 80 characters #1138: FILE: disas/riscv.c:1088: + { "c.sqsp", rv_codec_css_sqsp, rv_fmt_rs2_offset_rs1, NULL, 0, 0, rv_op_sq }, ERROR: trailing statements should be on next line #1403: FILE: disas/riscv.c:1353: + case 0: op = rv_op_c_addi4spn; break; ERROR: trailing statements should be on next line #1411: FILE: disas/riscv.c:1361: + case 2: op = rv_op_c_lw; break; ERROR: trailing statements should be on next line #1426: FILE: disas/riscv.c:1376: + case 6: op = rv_op_c_sw; break; ERROR: trailing statements should be on next line #1440: FILE: disas/riscv.c:1390: + case 0: op = rv_op_c_nop; break; ERROR: trailing statements should be on next line #1441: FILE: disas/riscv.c:1391: + default: op = rv_op_c_addi; break; ERROR: trailing statements should be on next line #1451: FILE: disas/riscv.c:1401: + case 2: op = rv_op_c_li; break; ERROR: trailing statements should be on next line #1454: FILE: disas/riscv.c:1404: + case 2: op = rv_op_c_addi16sp; break; ERROR: trailing statements should be on next line #1455: FILE: disas/riscv.c:1405: + default: op = rv_op_c_lui; break; ERROR: trailing statements should be on next line #1466: FILE: disas/riscv.c:1416: + case 2: op = rv_op_c_andi; break; ERROR: trailing statements should be on next line #1469: FILE: disas/riscv.c:1419: + case 0: op = rv_op_c_sub; break; ERROR: trailing statements should be on next line #1470: FILE: disas/riscv.c:1420: + case 1: op = rv_op_c_xor; break; ERROR: trailing statements should be on next line #1471: FILE: disas/riscv.c:1421: + case 2: op = rv_op_c_or; break; ERROR: trailing statements should be on next line #1472: FILE: disas/riscv.c:1422: + case 3: op = rv_op_c_and; break; ERROR: trailing statements should be on next line #1473: FILE: disas/riscv.c:1423: + case 4: op = rv_op_c_subw; break; ERROR: trailing statements should be on next line #1474: FILE: disas/riscv.c:1424: + case 5: op = rv_op_c_addw; break; ERROR: trailing statements should be on next line #1479: FILE: disas/riscv.c:1429: + case 5: op = rv_op_c_j; break; ERROR: trailing statements should be on next line #1480: FILE: disas/riscv.c:1430: + case 6: op = rv_op_c_beqz; break; ERROR: trailing statements should be on next line #1481: FILE: disas/riscv.c:1431: + case 7: op = rv_op_c_bnez; break; ERROR: trailing statements should be on next line #1496: FILE: disas/riscv.c:1446: + case 2: op = rv_op_c_lwsp; break; ERROR: trailing statements should be on next line #1508: FILE: disas/riscv.c:1458: + case 0: op = rv_op_c_jr; break; ERROR: trailing statements should be on next line #1509: FILE: disas/riscv.c:1459: + default: op = rv_op_c_mv; break; ERROR: trailing statements should be on next line #1516: FILE: disas/riscv.c:1466: + case 0: op = rv_op_c_ebreak; break; ERROR: trailing statements should be on next line #1517: FILE: disas/riscv.c:1467: + default: op = rv_op_c_jalr; break; ERROR: trailing statements should be on next line #1520: FILE: disas/riscv.c:1470: + default: op = rv_op_c_add; break; ERROR: trailing statements should be on next line #1531: FILE: disas/riscv.c:1481: + case 6: op = rv_op_c_swsp; break; ERROR: trailing statements should be on next line #1545: FILE: disas/riscv.c:1495: + case 0: op = rv_op_lb; break; ERROR: trailing statements should be on next line #1546: FILE: disas/riscv.c:1496: + case 1: op = rv_op_lh; break; ERROR: trailing statements should be on next line #1547: FILE: disas/riscv.c:1497: + case 2: op = rv_op_lw; break; ERROR: trailing statements should be on next line #1548: FILE: disas/riscv.c:1498: + case 3: op = rv_op_ld; break; ERROR: trailing statements should be on next line #1549: FILE: disas/riscv.c:1499: + case 4: op = rv_op_lbu; break; ERROR: trailing statements should be on next line #1550: FILE: disas/riscv.c:1500: + case 5: op = rv_op_lhu; break; ERROR: trailing statements should be on next line #1551: FILE: disas/riscv.c:1501: + case 6: op = rv_op_lwu; break; ERROR: trailing statements should be on next line #1552: FILE: disas/riscv.c:1502: + case 7: op = rv_op_ldu; break; ERROR: trailing statements should be on next line #1557: FILE: disas/riscv.c:1507: + case 2: op = rv_op_flw; break; ERROR: trailing statements should be on next line #1558: FILE: disas/riscv.c:1508: + case 3: op = rv_op_fld; break; ERROR: trailing statements should be on next line #1559: FILE: disas/riscv.c:1509: + case 4: op = rv_op_flq; break; ERROR: trailing statements should be on next line #1564: FILE: disas/riscv.c:1514: + case 0: op = rv_op_fence; break; ERROR: trailing statements should be on next line #1565: FILE: disas/riscv.c:1515: + case 1: op = rv_op_fence_i; break; ERROR: trailing statements should be on next line #1566: FILE: disas/riscv.c:1516: + case 2: op = rv_op_lq; break; ERROR: trailing statements should be on next line #1571: FILE: disas/riscv.c:1521: + case 0: op = rv_op_addi; break; ERROR: trailing statements should be on next line #1574: FILE: disas/riscv.c:1524: + case 0: op = rv_op_slli; break; ERROR: trailing statements should be on next line #1577: FILE: disas/riscv.c:1527: + case 2: op = rv_op_slti; break; ERROR: trailing statements should be on next line #1578: FILE: disas/riscv.c:1528: + case 3: op = rv_op_sltiu; break; ERROR: trailing statements should be on next line #1579: FILE: disas/riscv.c:1529: + case 4: op = rv_op_xori; break; ERROR: trailing statements should be on next line #1582: FILE: disas/riscv.c:1532: + case 0: op = rv_op_srli; break; ERROR: trailing statements should be on next line #1583: FILE: disas/riscv.c:1533: + case 8: op = rv_op_srai; break; ERROR: trailing statements should be on next line #1586: FILE: disas/riscv.c:1536: + case 6: op = rv_op_ori; break; ERROR: trailing statements should be on next line #1587: FILE: disas/riscv.c:1537: + case 7: op = rv_op_andi; break; ERROR: trailing statements should be on next line #1590: FILE: disas/riscv.c:1540: + case 5: op = rv_op_auipc; break; ERROR: trailing statements should be on next line #1593: FILE: disas/riscv.c:1543: + case 0: op = rv_op_addiw; break; ERROR: trailing statements should be on next line #1596: FILE: disas/riscv.c:1546: + case 0: op = rv_op_slliw; break; ERROR: trailing statements should be on next line #1601: FILE: disas/riscv.c:1551: + case 0: op = rv_op_srliw; break; ERROR: trailing statements should be on next line #1602: FILE: disas/riscv.c:1552: + case 32: op = rv_op_sraiw; break; ERROR: trailing statements should be on next line #1609: FILE: disas/riscv.c:1559: + case 0: op = rv_op_sb; break; ERROR: trailing statements should be on next line #1610: FILE: disas/riscv.c:1560: + case 1: op = rv_op_sh; break; ERROR: trailing statements should be on next line #1611: FILE: disas/riscv.c:1561: + case 2: op = rv_op_sw; break; ERROR: trailing statements should be on next line #1612: FILE: disas/riscv.c:1562: + case 3: op = rv_op_sd; break; ERROR: trailing statements should be on next line #1613: FILE: disas/riscv.c:1563: + case 4: op = rv_op_sq; break; ERROR: trailing statements should be on next line #1618: FILE: disas/riscv.c:1568: + case 2: op = rv_op_fsw; break; ERROR: trailing statements should be on next line #1619: FILE: disas/riscv.c:1569: + case 3: op = rv_op_fsd; break; ERROR: trailing statements should be on next line #1620: FILE: disas/riscv.c:1570: + case 4: op = rv_op_fsq; break; ERROR: trailing statements should be on next line #1625: FILE: disas/riscv.c:1575: + case 2: op = rv_op_amoadd_w; break; ERROR: trailing statements should be on next line #1626: FILE: disas/riscv.c:1576: + case 3: op = rv_op_amoadd_d; break; ERROR: trailing statements should be on next line #1627: FILE: disas/riscv.c:1577: + case 4: op = rv_op_amoadd_q; break; ERROR: trailing statements should be on next line #1628: FILE: disas/riscv.c:1578: + case 10: op = rv_op_amoswap_w; break; ERROR: trailing statements should be on next line #1629: FILE: disas/riscv.c:1579: + case 11: op = rv_op_amoswap_d; break; ERROR: trailing statements should be on next line #1630: FILE: disas/riscv.c:1580: + case 12: op = rv_op_amoswap_q; break; ERROR: trailing statements should be on next line #1633: FILE: disas/riscv.c:1583: + case 0: op = rv_op_lr_w; break; ERROR: trailing statements should be on next line #1638: FILE: disas/riscv.c:1588: + case 0: op = rv_op_lr_d; break; ERROR: trailing statements should be on next line #1643: FILE: disas/riscv.c:1593: + case 0: op = rv_op_lr_q; break; ERROR: trailing statements should be on next line #1646: FILE: disas/riscv.c:1596: + case 26: op = rv_op_sc_w; break; ERROR: trailing statements should be on next line #1647: FILE: disas/riscv.c:1597: + case 27: op = rv_op_sc_d; break; ERROR: trailing statements should be on next line #1648: FILE: disas/riscv.c:1598: + case 28: op = rv_op_sc_q; break; ERROR: trailing statements should be on next line #1649: FILE: disas/riscv.c:1599: + case 34: op = rv_op_amoxor_w; break; ERROR: trailing statements should be on next line #1650: FILE: disas/riscv.c:1600: + case 35: op = rv_op_amoxor_d; break; ERROR: trailing statements should be on next line #1651: FILE: disas/riscv.c:1601: + case 36: op = rv_op_amoxor_q; break; ERROR: trailing statements should be on next line #1652: FILE: disas/riscv.c:1602: + case 66: op = rv_op_amoor_w; break; ERROR: trailing statements should be on next line #1653: FILE: disas/riscv.c:1603: + case 67: op = rv_op_amoor_d; break; ERROR: trailing statements should be on next line #1654: FILE: disas/riscv.c:1604: + case 68: op = rv_op_amoor_q; break; ERROR: trailing statements should be on next line #1655: FILE: disas/riscv.c:1605: + case 98: op = rv_op_amoand_w; break; ERROR: trailing statements should be on next line #1656: FILE: disas/riscv.c:1606: + case 99: op = rv_op_amoand_d; break; ERROR: trailing statements should be on next line #1657: FILE: disas/riscv.c:1607: + case 100: op = rv_op_amoand_q; break; ERROR: trailing statements should be on next line #1658: FILE: disas/riscv.c:1608: + case 130: op = rv_op_amomin_w; break; ERROR: trailing statements should be on next line #1659: FILE: disas/riscv.c:1609: + case 131: op = rv_op_amomin_d; break; ERROR: trailing statements should be on next line #1660: FILE: disas/riscv.c:1610: + case 132: op = rv_op_amomin_q; break; ERROR: trailing statements should be on next line #1661: FILE: disas/riscv.c:1611: + case 162: op = rv_op_amomax_w; break; ERROR: trailing statements should be on next line #1662: FILE: disas/riscv.c:1612: + case 163: op = rv_op_amomax_d; break; ERROR: trailing statements should be on next line #1663: FILE: disas/riscv.c:1613: + case 164: op = rv_op_amomax_q; break; ERROR: trailing statements should be on next line #1664: FILE: disas/riscv.c:1614: + case 194: op = rv_op_amominu_w; break; ERROR: trailing statements should be on next line #1665: FILE: disas/riscv.c:1615: + case 195: op = rv_op_amominu_d; break; ERROR: trailing statements should be on next line #1666: FILE: disas/riscv.c:1616: + case 196: op = rv_op_amominu_q; break; ERROR: trailing statements should be on next line #1667: FILE: disas/riscv.c:1617: + case 226: op = rv_op_amomaxu_w; break; ERROR: trailing statements should be on next line #1668: FILE: disas/riscv.c:1618: + case 227: op = rv_op_amomaxu_d; break; ERROR: trailing statements should be on next line #1669: FILE: disas/riscv.c:1619: + case 228: op = rv_op_amomaxu_q; break; WARNING: line over 80 characters #1673: FILE: disas/riscv.c:1623: + switch (((inst >> 22) & 0b1111111000) | ((inst >> 12) & 0b0000000111)) { ERROR: trailing statements should be on next line #1674: FILE: disas/riscv.c:1624: + case 0: op = rv_op_add; break; ERROR: trailing statements should be on next line #1675: FILE: disas/riscv.c:1625: + case 1: op = rv_op_sll; break; ERROR: trailing statements should be on next line #1676: FILE: disas/riscv.c:1626: + case 2: op = rv_op_slt; break; ERROR: trailing statements should be on next line #1677: FILE: disas/riscv.c:1627: + case 3: op = rv_op_sltu; break; ERROR: trailing statements should be on next line #1678: FILE: disas/riscv.c:1628: + case 4: op = rv_op_xor; break; ERROR: trailing statements should be on next line #1679: FILE: disas/riscv.c:1629: + case 5: op = rv_op_srl; break; ERROR: trailing statements should be on next line #1680: FILE: disas/riscv.c:1630: + case 6: op = rv_op_or; break; ERROR: trailing statements should be on next line #1681: FILE: disas/riscv.c:1631: + case 7: op = rv_op_and; break; ERROR: trailing statements should be on next line #1682: FILE: disas/riscv.c:1632: + case 8: op = rv_op_mul; break; ERROR: trailing statements should be on next line #1683: FILE: disas/riscv.c:1633: + case 9: op = rv_op_mulh; break; ERROR: trailing statements should be on next line #1684: FILE: disas/riscv.c:1634: + case 10: op = rv_op_mulhsu; break; ERROR: trailing statements should be on next line #1685: FILE: disas/riscv.c:1635: + case 11: op = rv_op_mulhu; break; ERROR: trailing statements should be on next line #1686: FILE: disas/riscv.c:1636: + case 12: op = rv_op_div; break; ERROR: trailing statements should be on next line #1687: FILE: disas/riscv.c:1637: + case 13: op = rv_op_divu; break; ERROR: trailing statements should be on next line #1688: FILE: disas/riscv.c:1638: + case 14: op = rv_op_rem; break; ERROR: trailing statements should be on next line #1689: FILE: disas/riscv.c:1639: + case 15: op = rv_op_remu; break; ERROR: trailing statements should be on next line #1690: FILE: disas/riscv.c:1640: + case 256: op = rv_op_sub; break; ERROR: trailing statements should be on next line #1691: FILE: disas/riscv.c:1641: + case 261: op = rv_op_sra; break; ERROR: trailing statements should be on next line #1694: FILE: disas/riscv.c:1644: + case 13: op = rv_op_lui; break; WARNING: line over 80 characters #1696: FILE: disas/riscv.c:1646: + switch (((inst >> 22) & 0b1111111000) | ((inst >> 12) & 0b0000000111)) { ERROR: trailing statements should be on next line #1697: FILE: disas/riscv.c:1647: + case 0: op = rv_op_addw; break; ERROR: trailing statements should be on next line #1698: FILE: disas/riscv.c:1648: + case 1: op = rv_op_sllw; break; ERROR: trailing statements should be on next line #1699: FILE: disas/riscv.c:1649: + case 5: op = rv_op_srlw; break; ERROR: trailing statements should be on next line #1700: FILE: disas/riscv.c:1650: + case 8: op = rv_op_mulw; break; ERROR: trailing statements should be on next line #1701: FILE: disas/riscv.c:1651: + case 12: op = rv_op_divw; break; ERROR: trailing statements should be on next line #1702: FILE: disas/riscv.c:1652: + case 13: op = rv_op_divuw; break; ERROR: trailing statements should be on next line #1703: FILE: disas/riscv.c:1653: + case 14: op = rv_op_remw; break; ERROR: trailing statements should be on next line #1704: FILE: disas/riscv.c:1654: + case 15: op = rv_op_remuw; break; ERROR: trailing statements should be on next line #1705: FILE: disas/riscv.c:1655: + case 256: op = rv_op_subw; break; ERROR: trailing statements should be on next line #1706: FILE: disas/riscv.c:1656: + case 261: op = rv_op_sraw; break; ERROR: trailing statements should be on next line #1711: FILE: disas/riscv.c:1661: + case 0: op = rv_op_fmadd_s; break; ERROR: trailing statements should be on next line #1712: FILE: disas/riscv.c:1662: + case 1: op = rv_op_fmadd_d; break; ERROR: trailing statements should be on next line #1713: FILE: disas/riscv.c:1663: + case 3: op = rv_op_fmadd_q; break; ERROR: trailing statements should be on next line #1718: FILE: disas/riscv.c:1668: + case 0: op = rv_op_fmsub_s; break; ERROR: trailing statements should be on next line #1719: FILE: disas/riscv.c:1669: + case 1: op = rv_op_fmsub_d; break; ERROR: trailing statements should be on next line #1720: FILE: disas/riscv.c:1670: + case 3: op = rv_op_fmsub_q; break; ERROR: trailing statements should be on next line #1725: FILE: disas/riscv.c:1675: + case 0: op = rv_op_fnmsub_s; break; ERROR: trailing statements should be on next line #1726: FILE: disas/riscv.c:1676: + case 1: op = rv_op_fnmsub_d; break; ERROR: trailing statements should be on next line #1727: FILE: disas/riscv.c:1677: + case 3: op = rv_op_fnmsub_q; break; ERROR: trailing statements should be on next line #1732: FILE: disas/riscv.c:1682: + case 0: op = rv_op_fnmadd_s; break; ERROR: trailing statements should be on next line #1733: FILE: disas/riscv.c:1683: + case 1: op = rv_op_fnmadd_d; break; ERROR: trailing statements should be on next line #1734: FILE: disas/riscv.c:1684: + case 3: op = rv_op_fnmadd_q; break; ERROR: trailing statements should be on next line #1739: FILE: disas/riscv.c:1689: + case 0: op = rv_op_fadd_s; break; ERROR: trailing statements should be on next line #1740: FILE: disas/riscv.c:1690: + case 1: op = rv_op_fadd_d; break; ERROR: trailing statements should be on next line #1741: FILE: disas/riscv.c:1691: + case 3: op = rv_op_fadd_q; break; ERROR: trailing statements should be on next line #1742: FILE: disas/riscv.c:1692: + case 4: op = rv_op_fsub_s; break; ERROR: trailing statements should be on next line #1743: FILE: disas/riscv.c:1693: + case 5: op = rv_op_fsub_d; break; ERROR: trailing statements should be on next line #1744: FILE: disas/riscv.c:1694: + case 7: op = rv_op_fsub_q; break; ERROR: trailing statements should be on next line #1745: FILE: disas/riscv.c:1695: + case 8: op = rv_op_fmul_s; break; ERROR: trailing statements should be on next line #1746: FILE: disas/riscv.c:1696: + case 9: op = rv_op_fmul_d; break; ERROR: trailing statements should be on next line #1747: FILE: disas/riscv.c:1697: + case 11: op = rv_op_fmul_q; break; ERROR: trailing statements should be on next line #1748: FILE: disas/riscv.c:1698: + case 12: op = rv_op_fdiv_s; break; ERROR: trailing statements should be on next line #1749: FILE: disas/riscv.c:1699: + case 13: op = rv_op_fdiv_d; break; ERROR: trailing statements should be on next line #1750: FILE: disas/riscv.c:1700: + case 15: op = rv_op_fdiv_q; break; ERROR: trailing statements should be on next line #1753: FILE: disas/riscv.c:1703: + case 0: op = rv_op_fsgnj_s; break; ERROR: trailing statements should be on next line #1754: FILE: disas/riscv.c:1704: + case 1: op = rv_op_fsgnjn_s; break; ERROR: trailing statements should be on next line #1755: FILE: disas/riscv.c:1705: + case 2: op = rv_op_fsgnjx_s; break; ERROR: trailing statements should be on next line #1760: FILE: disas/riscv.c:1710: + case 0: op = rv_op_fsgnj_d; break; ERROR: trailing statements should be on next line #1761: FILE: disas/riscv.c:1711: + case 1: op = rv_op_fsgnjn_d; break; ERROR: trailing statements should be on next line #1762: FILE: disas/riscv.c:1712: + case 2: op = rv_op_fsgnjx_d; break; ERROR: trailing statements should be on next line #1767: FILE: disas/riscv.c:1717: + case 0: op = rv_op_fsgnj_q; break; ERROR: trailing statements should be on next line #1768: FILE: disas/riscv.c:1718: + case 1: op = rv_op_fsgnjn_q; break; ERROR: trailing statements should be on next line #1769: FILE: disas/riscv.c:1719: + case 2: op = rv_op_fsgnjx_q; break; ERROR: trailing statements should be on next line #1774: FILE: disas/riscv.c:1724: + case 0: op = rv_op_fmin_s; break; ERROR: trailing statements should be on next line #1775: FILE: disas/riscv.c:1725: + case 1: op = rv_op_fmax_s; break; ERROR: trailing statements should be on next line #1780: FILE: disas/riscv.c:1730: + case 0: op = rv_op_fmin_d; break; ERROR: trailing statements should be on next line #1781: FILE: disas/riscv.c:1731: + case 1: op = rv_op_fmax_d; break; ERROR: trailing statements should be on next line #1786: FILE: disas/riscv.c:1736: + case 0: op = rv_op_fmin_q; break; ERROR: trailing statements should be on next line #1787: FILE: disas/riscv.c:1737: + case 1: op = rv_op_fmax_q; break; ERROR: trailing statements should be on next line #1792: FILE: disas/riscv.c:1742: + case 1: op = rv_op_fcvt_s_d; break; ERROR: trailing statements should be on next line #1793: FILE: disas/riscv.c:1743: + case 3: op = rv_op_fcvt_s_q; break; ERROR: trailing statements should be on next line #1798: FILE: disas/riscv.c:1748: + case 0: op = rv_op_fcvt_d_s; break; ERROR: trailing statements should be on next line #1799: FILE: disas/riscv.c:1749: + case 3: op = rv_op_fcvt_d_q; break; ERROR: trailing statements should be on next line #1804: FILE: disas/riscv.c:1754: + case 0: op = rv_op_fcvt_q_s; break; ERROR: trailing statements should be on next line #1805: FILE: disas/riscv.c:1755: + case 1: op = rv_op_fcvt_q_d; break; ERROR: trailing statements should be on next line #1810: FILE: disas/riscv.c:1760: + case 0: op = rv_op_fsqrt_s; break; ERROR: trailing statements should be on next line #1815: FILE: disas/riscv.c:1765: + case 0: op = rv_op_fsqrt_d; break; ERROR: trailing statements should be on next line #1820: FILE: disas/riscv.c:1770: + case 0: op = rv_op_fsqrt_q; break; ERROR: trailing statements should be on next line #1825: FILE: disas/riscv.c:1775: + case 0: op = rv_op_fle_s; break; ERROR: trailing statements should be on next line #1826: FILE: disas/riscv.c:1776: + case 1: op = rv_op_flt_s; break; ERROR: trailing statements should be on next line #1827: FILE: disas/riscv.c:1777: + case 2: op = rv_op_feq_s; break; ERROR: trailing statements should be on next line #1832: FILE: disas/riscv.c:1782: + case 0: op = rv_op_fle_d; break; ERROR: trailing statements should be on next line #1833: FILE: disas/riscv.c:1783: + case 1: op = rv_op_flt_d; break; ERROR: trailing statements should be on next line #1834: FILE: disas/riscv.c:1784: + case 2: op = rv_op_feq_d; break; ERROR: trailing statements should be on next line #1839: FILE: disas/riscv.c:1789: + case 0: op = rv_op_fle_q; break; ERROR: trailing statements should be on next line #1840: FILE: disas/riscv.c:1790: + case 1: op = rv_op_flt_q; break; ERROR: trailing statements should be on next line #1841: FILE: disas/riscv.c:1791: + case 2: op = rv_op_feq_q; break; ERROR: trailing statements should be on next line #1846: FILE: disas/riscv.c:1796: + case 0: op = rv_op_fcvt_w_s; break; ERROR: trailing statements should be on next line #1847: FILE: disas/riscv.c:1797: + case 1: op = rv_op_fcvt_wu_s; break; ERROR: trailing statements should be on next line #1848: FILE: disas/riscv.c:1798: + case 2: op = rv_op_fcvt_l_s; break; ERROR: trailing statements should be on next line #1849: FILE: disas/riscv.c:1799: + case 3: op = rv_op_fcvt_lu_s; break; ERROR: trailing statements should be on next line #1854: FILE: disas/riscv.c:1804: + case 0: op = rv_op_fcvt_w_d; break; ERROR: trailing statements should be on next line #1855: FILE: disas/riscv.c:1805: + case 1: op = rv_op_fcvt_wu_d; break; ERROR: trailing statements should be on next line #1856: FILE: disas/riscv.c:1806: + case 2: op = rv_op_fcvt_l_d; break; ERROR: trailing statements should be on next line #1857: FILE: disas/riscv.c:1807: + case 3: op = rv_op_fcvt_lu_d; break; ERROR: trailing statements should be on next line #1862: FILE: disas/riscv.c:1812: + case 0: op = rv_op_fcvt_w_q; break; ERROR: trailing statements should be on next line #1863: FILE: disas/riscv.c:1813: + case 1: op = rv_op_fcvt_wu_q; break; ERROR: trailing statements should be on next line #1864: FILE: disas/riscv.c:1814: + case 2: op = rv_op_fcvt_l_q; break; ERROR: trailing statements should be on next line #1865: FILE: disas/riscv.c:1815: + case 3: op = rv_op_fcvt_lu_q; break; ERROR: trailing statements should be on next line #1870: FILE: disas/riscv.c:1820: + case 0: op = rv_op_fcvt_s_w; break; ERROR: trailing statements should be on next line #1871: FILE: disas/riscv.c:1821: + case 1: op = rv_op_fcvt_s_wu; break; ERROR: trailing statements should be on next line #1872: FILE: disas/riscv.c:1822: + case 2: op = rv_op_fcvt_s_l; break; ERROR: trailing statements should be on next line #1873: FILE: disas/riscv.c:1823: + case 3: op = rv_op_fcvt_s_lu; break; ERROR: trailing statements should be on next line #1878: FILE: disas/riscv.c:1828: + case 0: op = rv_op_fcvt_d_w; break; ERROR: trailing statements should be on next line #1879: FILE: disas/riscv.c:1829: + case 1: op = rv_op_fcvt_d_wu; break; ERROR: trailing statements should be on next line #1880: FILE: disas/riscv.c:1830: + case 2: op = rv_op_fcvt_d_l; break; ERROR: trailing statements should be on next line #1881: FILE: disas/riscv.c:1831: + case 3: op = rv_op_fcvt_d_lu; break; ERROR: trailing statements should be on next line #1886: FILE: disas/riscv.c:1836: + case 0: op = rv_op_fcvt_q_w; break; ERROR: trailing statements should be on next line #1887: FILE: disas/riscv.c:1837: + case 1: op = rv_op_fcvt_q_wu; break; ERROR: trailing statements should be on next line #1888: FILE: disas/riscv.c:1838: + case 2: op = rv_op_fcvt_q_l; break; ERROR: trailing statements should be on next line #1889: FILE: disas/riscv.c:1839: + case 3: op = rv_op_fcvt_q_lu; break; WARNING: line over 80 characters #1893: FILE: disas/riscv.c:1843: + switch (((inst >> 17) & 0b11111000) | ((inst >> 12) & 0b00000111)) { ERROR: trailing statements should be on next line #1894: FILE: disas/riscv.c:1844: + case 0: op = rv_op_fmv_x_s; break; ERROR: trailing statements should be on next line #1895: FILE: disas/riscv.c:1845: + case 1: op = rv_op_fclass_s; break; WARNING: line over 80 characters #1899: FILE: disas/riscv.c:1849: + switch (((inst >> 17) & 0b11111000) | ((inst >> 12) & 0b00000111)) { ERROR: trailing statements should be on next line #1900: FILE: disas/riscv.c:1850: + case 0: op = rv_op_fmv_x_d; break; ERROR: trailing statements should be on next line #1901: FILE: disas/riscv.c:1851: + case 1: op = rv_op_fclass_d; break; WARNING: line over 80 characters #1905: FILE: disas/riscv.c:1855: + switch (((inst >> 17) & 0b11111000) | ((inst >> 12) & 0b00000111)) { ERROR: trailing statements should be on next line #1906: FILE: disas/riscv.c:1856: + case 0: op = rv_op_fmv_x_q; break; ERROR: trailing statements should be on next line #1907: FILE: disas/riscv.c:1857: + case 1: op = rv_op_fclass_q; break; WARNING: line over 80 characters #1911: FILE: disas/riscv.c:1861: + switch (((inst >> 17) & 0b11111000) | ((inst >> 12) & 0b00000111)) { ERROR: trailing statements should be on next line #1912: FILE: disas/riscv.c:1862: + case 0: op = rv_op_fmv_s_x; break; WARNING: line over 80 characters #1916: FILE: disas/riscv.c:1866: + switch (((inst >> 17) & 0b11111000) | ((inst >> 12) & 0b00000111)) { ERROR: trailing statements should be on next line #1917: FILE: disas/riscv.c:1867: + case 0: op = rv_op_fmv_d_x; break; WARNING: line over 80 characters #1921: FILE: disas/riscv.c:1871: + switch (((inst >> 17) & 0b11111000) | ((inst >> 12) & 0b00000111)) { ERROR: trailing statements should be on next line #1922: FILE: disas/riscv.c:1872: + case 0: op = rv_op_fmv_q_x; break; ERROR: trailing statements should be on next line #1929: FILE: disas/riscv.c:1879: + case 0: op = rv_op_addid; break; ERROR: trailing statements should be on next line #1932: FILE: disas/riscv.c:1882: + case 0: op = rv_op_sllid; break; ERROR: trailing statements should be on next line #1937: FILE: disas/riscv.c:1887: + case 0: op = rv_op_srlid; break; ERROR: trailing statements should be on next line #1938: FILE: disas/riscv.c:1888: + case 16: op = rv_op_sraid; break; ERROR: trailing statements should be on next line #1945: FILE: disas/riscv.c:1895: + case 0: op = rv_op_beq; break; ERROR: trailing statements should be on next line #1946: FILE: disas/riscv.c:1896: + case 1: op = rv_op_bne; break; ERROR: trailing statements should be on next line #1947: FILE: disas/riscv.c:1897: + case 4: op = rv_op_blt; break; ERROR: trailing statements should be on next line #1948: FILE: disas/riscv.c:1898: + case 5: op = rv_op_bge; break; ERROR: trailing statements should be on next line #1949: FILE: disas/riscv.c:1899: + case 6: op = rv_op_bltu; break; ERROR: trailing statements should be on next line #1950: FILE: disas/riscv.c:1900: + case 7: op = rv_op_bgeu; break; ERROR: trailing statements should be on next line #1955: FILE: disas/riscv.c:1905: + case 0: op = rv_op_jalr; break; ERROR: trailing statements should be on next line #1958: FILE: disas/riscv.c:1908: + case 27: op = rv_op_jal; break; ERROR: line over 90 characters #1962: FILE: disas/riscv.c:1912: + switch (((inst >> 20) & 0b111111100000) | ((inst >> 7) & 0b000000011111)) { ERROR: trailing statements should be on next line #1965: FILE: disas/riscv.c:1915: + case 0: op = rv_op_ecall; break; ERROR: trailing statements should be on next line #1966: FILE: disas/riscv.c:1916: + case 32: op = rv_op_ebreak; break; ERROR: trailing statements should be on next line #1967: FILE: disas/riscv.c:1917: + case 64: op = rv_op_uret; break; ERROR: trailing statements should be on next line #1974: FILE: disas/riscv.c:1924: + case 0: op = rv_op_sret; break; ERROR: trailing statements should be on next line #1977: FILE: disas/riscv.c:1927: + case 4: op = rv_op_sfence_vm; break; ERROR: trailing statements should be on next line #1980: FILE: disas/riscv.c:1930: + case 0: op = rv_op_wfi; break; ERROR: trailing statements should be on next line #1985: FILE: disas/riscv.c:1935: + case 288: op = rv_op_sfence_vma; break; ERROR: trailing statements should be on next line #1988: FILE: disas/riscv.c:1938: + case 64: op = rv_op_hret; break; ERROR: trailing statements should be on next line #1993: FILE: disas/riscv.c:1943: + case 64: op = rv_op_mret; break; ERROR: trailing statements should be on next line #1998: FILE: disas/riscv.c:1948: + case 576: op = rv_op_dret; break; ERROR: trailing statements should be on next line #2003: FILE: disas/riscv.c:1953: + case 1: op = rv_op_csrrw; break; ERROR: trailing statements should be on next line #2004: FILE: disas/riscv.c:1954: + case 2: op = rv_op_csrrs; break; ERROR: trailing statements should be on next line #2005: FILE: disas/riscv.c:1955: + case 3: op = rv_op_csrrc; break; ERROR: trailing statements should be on next line #2006: FILE: disas/riscv.c:1956: + case 5: op = rv_op_csrrwi; break; ERROR: trailing statements should be on next line #2007: FILE: disas/riscv.c:1957: + case 6: op = rv_op_csrrsi; break; ERROR: trailing statements should be on next line #2008: FILE: disas/riscv.c:1958: + case 7: op = rv_op_csrrci; break; WARNING: line over 80 characters #2012: FILE: disas/riscv.c:1962: + switch (((inst >> 22) & 0b1111111000) | ((inst >> 12) & 0b0000000111)) { ERROR: trailing statements should be on next line #2013: FILE: disas/riscv.c:1963: + case 0: op = rv_op_addd; break; ERROR: trailing statements should be on next line #2014: FILE: disas/riscv.c:1964: + case 1: op = rv_op_slld; break; ERROR: trailing statements should be on next line #2015: FILE: disas/riscv.c:1965: + case 5: op = rv_op_srld; break; ERROR: trailing statements should be on next line #2016: FILE: disas/riscv.c:1966: + case 8: op = rv_op_muld; break; ERROR: trailing statements should be on next line #2017: FILE: disas/riscv.c:1967: + case 12: op = rv_op_divd; break; ERROR: trailing statements should be on next line #2018: FILE: disas/riscv.c:1968: + case 13: op = rv_op_divud; break; ERROR: trailing statements should be on next line #2019: FILE: disas/riscv.c:1969: + case 14: op = rv_op_remd; break; ERROR: trailing statements should be on next line #2020: FILE: disas/riscv.c:1970: + case 15: op = rv_op_remud; break; ERROR: trailing statements should be on next line #2021: FILE: disas/riscv.c:1971: + case 256: op = rv_op_subd; break; ERROR: trailing statements should be on next line #2022: FILE: disas/riscv.c:1972: + case 261: op = rv_op_srad; break; ERROR: trailing statements should be on next line #2785: FILE: disas/riscv.c:2735: + default: break; ERROR: space prohibited between function name and open parenthesis '(' #3113: FILE: include/disas/bfd.h:431: +int print_insn_riscv32 (bfd_vma, disassemble_info*); ERROR: space prohibited between function name and open parenthesis '(' #3114: FILE: include/disas/bfd.h:432: +int print_insn_riscv64 (bfd_vma, disassemble_info*); total: 279 errors, 38 warnings, 3077 lines checked Your patch has style problems, please review. If any of these errors are false positives report them to the maintainer, see CHECKPATCH in MAINTAINERS. Checking PATCH 5/21: RISC-V CPU Helpers... Checking PATCH 6/21: RISC-V FPU Support... Checking PATCH 7/21: RISC-V GDB Stub... Checking PATCH 8/21: RISC-V TCG Code Generation... ERROR: spaces required around that ':' (ctx:VxE) #647: FILE: target/riscv/translate.c:242: + CASE_OP_32_64(OPC_RISC_ADD): ^ ERROR: spaces required around that ':' (ctx:VxE) #650: FILE: target/riscv/translate.c:245: + CASE_OP_32_64(OPC_RISC_SUB): ^ ERROR: spaces required around that ':' (ctx:VxE) #704: FILE: target/riscv/translate.c:299: + CASE_OP_32_64(OPC_RISC_MUL): ^ total: 3 errors, 0 warnings, 2359 lines checked Your patch has style problems, please review. If any of these errors are false positives report them to the maintainer, see CHECKPATCH in MAINTAINERS. Checking PATCH 9/21: RISC-V Physical Memory Protection... Checking PATCH 10/21: RISC-V Linux User Emulation... Checking PATCH 11/21: RISC-V HTIF Console... Checking PATCH 12/21: RISC-V HART Array... Checking PATCH 13/21: SiFive RISC-V CLINT Block... Checking PATCH 14/21: SiFive RISC-V PLIC Block... Checking PATCH 15/21: RISC-V Spike Machines... Checking PATCH 16/21: RISC-V VirtIO Machine... Checking PATCH 17/21: SiFive RISC-V UART Device... Checking PATCH 18/21: SiFive RISC-V PRCI Block... Checking PATCH 19/21: SiFive Freedom E300 RISC-V Machine... Checking PATCH 20/21: SiFive Freedom U500 RISC-V Machine... Checking PATCH 21/21: RISC-V Build Infrastructure... WARNING: line over 80 characters #222: FILE: scripts/qemu-binfmt-conf.sh:99: +riscv32_magic='\x7fELF\x01\x01\x01\x00\x00\x00\x00\x00\x00\x00\x00\x00\x02\x00\xf3\x00' ERROR: line over 90 characters #223: FILE: scripts/qemu-binfmt-conf.sh:100: +riscv32_mask='\xff\xff\xff\xff\xff\xff\xff\x00\xff\xff\xff\xff\xff\xff\xff\xff\xfe\xff\xff\xff' WARNING: line over 80 characters #226: FILE: scripts/qemu-binfmt-conf.sh:103: +riscv64_magic='\x7fELF\x02\x01\x01\x00\x00\x00\x00\x00\x00\x00\x00\x00\x02\x00\xf3\x00' ERROR: line over 90 characters #227: FILE: scripts/qemu-binfmt-conf.sh:104: +riscv64_mask='\xff\xff\xff\xff\xff\xff\xff\x00\xff\xff\xff\xff\xff\xff\xff\xff\xfe\xff\xff\xff' total: 2 errors, 2 warnings, 151 lines checked Your patch has style problems, please review. If any of these errors are false positives report them to the maintainer, see CHECKPATCH in MAINTAINERS. === OUTPUT END === Test command exited with code: 1 --- Email generated automatically by Patchew [http://patchew.org/]. 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