Hello,

Here is a series adding support for the interrupt controller as found
on a POWER8 system. POWER9 uses a different interrupt controller
called XIVE, still to be worked on.

The initial patches are more cleanups of the XICS layer which move the
IRQ 'server' number mapping under the machine handlers.

A new PnvICPState object based on MMIOs, which is specific to PowerNV,
is introduced in XICS. These ICP objects are created for each thread
of a core and linked to the associated PowerPCCPU object.

Finally, to make use of the XICS layer, the PowerNV machine is
extended with a QOM XICSFabric interface and with a global memory
region acting as the Interrupt Management area.


To test, grab a kernel and a rootfs image here :

  https://openpower.xyz/job/openpower-op-build/distro=ubuntu,target=palmetto/lastSuccessfulBuild/artifact/images/zImage.epapr
  https://openpower.xyz/job/openpower-op-build/distro=ubuntu,target=palmetto/lastSuccessfulBuild/artifact/images/rootfs.cpio.xz

The full patchset is available here :

   https://github.com/legoater/qemu/commits/powernv-ipmi-2.9

Thanks,

C.

Changes since v4:
 - reworked a bit the order of the patches for make check-qtest-ppc64
   to pass. The machine needs to be a XICSFabric before the PnvCore
   use it.
 - allocated the ICPState object from under sPAPRCPUCore and removed
   xics_get_cpu_index_by_dt_id()
 - moved the creation of PnvICPState object before the PowerPCCPU
   object is realized to handle correctly errors.
 - removed the empty ics_get() and ics_resend() handlers. They will be
   added by the PSI HB model

Changes since v3:
 - renamed 'icp' backlink to a more generic name 'intc'
 - removed the array of ICP objects from under the PowerNV machine and
   handled the allocation of the PnvICPState object for each thread
   when the PowerPCCPU object is realized.

Changes since v2:

 - removed the ICS list from the PowerNV machine
 - changed the 'icp' backlink type to be an 'Object'

Changes since v1:

 - introduced PnvICPState to hold the ICP memory region
 - handled pir-to-cpu_index mapping under the machine icp_get handler
 - added multichip support
 - removed ics_eoi handler (came from a bug in PHB3_MSI)
 - kept PSI and OCC model for later, when this part is done.

Cédric Le Goater (9):
  spapr: move the IRQ server number mapping under the machine
  spapr: allocate the ICPState object from under sPAPRCPUCore
  ppc/xics: add a realize() handler to ICPStateClass
  ppc/pnv: add a PnvICPState object
  ppc/pnv: extend the machine with a XICSFabric interface
  ppc/pnv: extend the machine with a InterruptStatsProvider interface
  ppc/pnv: create the ICP object under PnvCore
  ppc/pnv: add a helper to calculate MMIO addresses registers
  ppc/pnv: add memory regions for the ICP registers

 hw/intc/Makefile.objs   |   1 +
 hw/intc/xics.c          |  16 ++--
 hw/intc/xics_pnv.c      | 192 ++++++++++++++++++++++++++++++++++++++++++++++++
 hw/intc/xics_spapr.c    |   5 +-
 hw/ppc/pnv.c            | 130 ++++++++++++++++++++++++++++++++
 hw/ppc/pnv_core.c       |  27 ++++++-
 hw/ppc/spapr.c          |  48 ++++--------
 hw/ppc/spapr_cpu_core.c |  18 ++++-
 include/hw/ppc/pnv.h    |  31 +++++++-
 include/hw/ppc/spapr.h  |   2 +-
 include/hw/ppc/xics.h   |  15 +++-
 11 files changed, 428 insertions(+), 57 deletions(-)
 create mode 100644 hw/intc/xics_pnv.c

-- 
2.7.4

On Mon, Apr 03, 2017 at 09:45:56AM +0200, Cédric Le Goater wrote:
> Hello,
> 
> Here is a series adding support for the interrupt controller as found
> on a POWER8 system. POWER9 uses a different interrupt controller
> called XIVE, still to be worked on.
> 
> The initial patches are more cleanups of the XICS layer which move the
> IRQ 'server' number mapping under the machine handlers.
> 
> A new PnvICPState object based on MMIOs, which is specific to PowerNV,
> is introduced in XICS. These ICP objects are created for each thread
> of a core and linked to the associated PowerPCCPU object.
> 
> Finally, to make use of the XICS layer, the PowerNV machine is
> extended with a QOM XICSFabric interface and with a global memory
> region acting as the Interrupt Management area.
> 
> 
> To test, grab a kernel and a rootfs image here :
> 
>   https://openpower.xyz/job/openpower-op-build/distro=ubuntu,target=palmetto/lastSuccessfulBuild/artifact/images/zImage.epapr
>   https://openpower.xyz/job/openpower-op-build/distro=ubuntu,target=palmetto/lastSuccessfulBuild/artifact/images/rootfs.cpio.xz
> 
> The full patchset is available here :
> 
>    https://github.com/legoater/qemu/commits/powernv-ipmi-2.9
> 
> Thanks,

I've applied the series to my ppc-for-2.10 branch.  A couple of things
to think about for follow up cleanups:

1) The spapr->nr_servers field has very little remaining use; can you
   go a bit further and remove it entirely?

2) At the moment you're creating (and realizing) the ICP objects just
before you realize the core objects.  I'm not entirely sure if
creating new objects at realize time is QOMishly correct.  Maybe do
some more enquiries to see if it is or not, and if not update.

-- 
David Gibson			| I'll have my music baroque, and my code
david AT gibson.dropbear.id.au	| minimalist, thank you.  NOT _the_ _other_
				| _way_ _around_!
http://www.ozlabs.org/~dgibson

On 04/05/2017 07:51 AM, David Gibson wrote:
> On Mon, Apr 03, 2017 at 09:45:56AM +0200, Cédric Le Goater wrote:
>> Hello,
>>
>> Here is a series adding support for the interrupt controller as found
>> on a POWER8 system. POWER9 uses a different interrupt controller
>> called XIVE, still to be worked on.
>>
>> The initial patches are more cleanups of the XICS layer which move the
>> IRQ 'server' number mapping under the machine handlers.
>>
>> A new PnvICPState object based on MMIOs, which is specific to PowerNV,
>> is introduced in XICS. These ICP objects are created for each thread
>> of a core and linked to the associated PowerPCCPU object.
>>
>> Finally, to make use of the XICS layer, the PowerNV machine is
>> extended with a QOM XICSFabric interface and with a global memory
>> region acting as the Interrupt Management area.
>>
>>
>> To test, grab a kernel and a rootfs image here :
>>
>>   https://openpower.xyz/job/openpower-op-build/distro=ubuntu,target=palmetto/lastSuccessfulBuild/artifact/images/zImage.epapr
>>   https://openpower.xyz/job/openpower-op-build/distro=ubuntu,target=palmetto/lastSuccessfulBuild/artifact/images/rootfs.cpio.xz
>>
>> The full patchset is available here :
>>
>>    https://github.com/legoater/qemu/commits/powernv-ipmi-2.9
>>
>> Thanks,
> 
> I've applied the series to my ppc-for-2.10 branch.  A couple of things
> to think about for follow up cleanups:
> 
> 1) The spapr->nr_servers field has very little remaining use; can you
>    go a bit further and remove it entirely?

yes. I have a patch for it already, reshuffling the xics_system_init
routine again to make it look a little better : 

	https://github.com/legoater/qemu/commit/94e90b4b660d521ad4806a5496dd89f351995810
 
> 2) At the moment you're creating (and realizing) the ICP objects 

yes. This is because the number of ICPState objects depends 
on 'nr_threads' which is only known at realize time.

We could also define an array of icps in the core:

	PnvICPState icps[MAX_THREADS]

initialize them in an init routine and only realize a subset 
depending on 'nr_threads'. 

This is possible because the size of TYPE_PNV_ICP and TYPE_ICP
are the same. 

But, the current method is safer I think. 

> just  before you realize the core objects. 

yes. this is to not complete the core realization if the ICP 
creation fails. Else the core would be fully realized before 
the ICP, which feels incorrect as the ICP is an attribute 
of the core now. 

> I'm not entirely sure if
> creating new objects at realize time is QOMishly correct.  Maybe do
> some more enquiries to see if it is or not, and if not update.

Yes.

Thanks,

C.