Timer interrupts are level triggered. Hence, signal end of
interrupt only after current interrupt has been cleared
after setting updated compare value.

Signed-off-by: Ashish Singhal <ashishsingha@nvidia.com>
---
 ArmPkg/Drivers/TimerDxe/TimerDxe.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/ArmPkg/Drivers/TimerDxe/TimerDxe.c b/ArmPkg/Drivers/TimerDxe/TimerDxe.c
index 0370620fae..56c9c353b3 100644
--- a/ArmPkg/Drivers/TimerDxe/TimerDxe.c
+++ b/ArmPkg/Drivers/TimerDxe/TimerDxe.c
@@ -300,10 +300,6 @@ TimerInterruptHandler (
   //
   OriginalTPL = gBS->RaiseTPL (TPL_HIGH_LEVEL);
 
-  // Signal end of interrupt early to help avoid losing subsequent ticks
-  // from long duration handlers
-  gInterrupt->EndOfInterrupt (gInterrupt, Source);
-
   // Check if the timer interrupt is active
   if ((ArmGenericTimerGetTimerCtrlReg () ) & ARM_ARCH_TIMER_ISTATUS) {
 
@@ -335,6 +331,10 @@ TimerInterruptHandler (
     ArmInstructionSynchronizationBarrier ();
   }
 
+  // Timer interrupts are level triggered. Hence, signal end of interrupt only after current
+  // interrupt has been cleared after setting updated compare value.
+  gInterrupt->EndOfInterrupt (gInterrupt, Source);
+
   gBS->RestoreTPL (OriginalTPL);
 }
 
-- 
2.17.1



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