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Mon, 11 Oct 2021 19:20:57 +0000 X-Received: from HQMAIL101.nvidia.com (172.20.187.10) by HQMAIL111.nvidia.com (172.20.187.18) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Mon, 11 Oct 2021 19:20:56 +0000 X-Received: from ashishsingha-lnx.nvidia.com (172.20.187.6) by mail.nvidia.com (172.20.187.10) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Mon, 11 Oct 2021 19:20:55 +0000 From: "Ashish Singhal via groups.io" To: , , CC: Ashish Singhal Subject: [edk2-devel] [PATCH] ArmPkg/TimerDxe: Delay End Of Interrupt Signal Date: Mon, 11 Oct 2021 13:20:50 -0600 Message-ID: <775695ba8b279068d82f2fd50486370d7eeb03c2.1633979944.git.ashishsingha@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: dc1a7a39-f030-412b-e5ab-08d98cec40d9 X-MS-TrafficTypeDiagnostic: BL0PR12MB2386: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:962; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam-Message-Info: bu0Jl4IaRtLdNnzVz9oLuAFvYNE0vkQaIQiNnTLufuTb5NewjoEtW38jnSinn45vxGVBUbt/VvSRqg2Sb90V+a/75fgsnNU9u+CuHhgnfwag9u5Eo/9cgK96mUQZDYP5DcqYP6kcqFYIoRbFj9d2xQQDgMZLzStFeOjRSUxnfICmYi/RS9s8qvsWxn95pJBQd/1LLT00BQ3saPTvJgaoDrvGaFVm1jpKZkH5ltiOqSnoIeAgxruKDuIq4P5sjxZ++nZ8IfuvK6KoAbW6npcWA5OPuO3ual7l4g0VkUoSaT0q8YsD0BrDXdEtJgJQVI8iLK6d/H7+oqEL2oqLwJ33q/j+c5WwCPAKOBBbfB3vHO6i4jgRdtBCLstR+gaddEugyxUTeEqQFvr6i/giwbb2qlS//N/sjy9zjKKfJTVzkqvn+Yj5cIfLJ7aEAEqkSv0ac7DuCd1SelEADViQvPENj9S8cegytDHHqvhzmTgsQWZdlp1EFxo//FMuTSm31i+nUU35lkFZ8hU5uMHuq+iPZ0qvsUyokL97tRzLUEuk2C24I3ti0UPdmW80fQEokzvPfeVbeVc4cvvUjv0h7Su1xd6ekd6DFL/7SK7n55K76BndsQeSrBDEJeaShjUawBOU0O9xodw+oevjIFCRP8/e3FuxmFQD2EKTaRHyyPTuLRSPIlccg/FOMx2tDAsOSW8hxl81sO0MhjucfMdh4p0CUg== X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Oct 2021 19:20:57.6748 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: dc1a7a39-f030-412b-e5ab-08d98cec40d9 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.112.35];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT022.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL0PR12MB2386 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,ashishsingha@nvidia.com X-Gm-Message-State: qdVg9levGBkxlu4UMjEt2LqIx1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1633980060; bh=wKiJJYxxn2MVP/JJdcXfYqbpuKWbdrfaYpFJpA45Eb8=; h=CC:Content-Type:Date:From:Reply-To:Subject:To; b=OoQSgHFhVGmtSTlFSzFSemthmMxW0C1243yxQhkoD2FfKFatqsNtxxRfv0FKPwbW/aq XhrhwwiBCKRV+i5hnHgGh4hxQG0zL8SBCcZUK/VAb/H0MS9xejJhzrN7BDeqVc5mxRNyY X66pIhSNm/SqxlI2pCDHUlACsVN0zTZibYk= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1633980062715100002 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Timer interrupts are level triggered. Hence, signal end of interrupt only after current interrupt has been cleared after setting updated compare value. Signed-off-by: Ashish Singhal --- ArmPkg/Drivers/TimerDxe/TimerDxe.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/ArmPkg/Drivers/TimerDxe/TimerDxe.c b/ArmPkg/Drivers/TimerDxe/T= imerDxe.c index 0370620fae..56c9c353b3 100644 --- a/ArmPkg/Drivers/TimerDxe/TimerDxe.c +++ b/ArmPkg/Drivers/TimerDxe/TimerDxe.c @@ -300,10 +300,6 @@ TimerInterruptHandler ( // OriginalTPL =3D gBS->RaiseTPL (TPL_HIGH_LEVEL); =20 - // Signal end of interrupt early to help avoid losing subsequent ticks - // from long duration handlers - gInterrupt->EndOfInterrupt (gInterrupt, Source); - // Check if the timer interrupt is active if ((ArmGenericTimerGetTimerCtrlReg () ) & ARM_ARCH_TIMER_ISTATUS) { =20 @@ -335,6 +331,10 @@ TimerInterruptHandler ( ArmInstructionSynchronizationBarrier (); } =20 + // Timer interrupts are level triggered. Hence, signal end of interrupt = only after current + // interrupt has been cleared after setting updated compare value. + gInterrupt->EndOfInterrupt (gInterrupt, Source); + gBS->RestoreTPL (OriginalTPL); } =20 --=20 2.17.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#81763): https://edk2.groups.io/g/devel/message/81763 Mute This Topic: https://groups.io/mt/86245640/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-