Implementing code to support Cache Management Operations (CMO) defined by RV spec https://github.com/riscv/riscv-CMOs

Notes:
CMO only supports block based Operations. Meaning complete cache flush/invd/clean Operations are not available. In that case we fallback on fence.i instructions.
Rely on the fact that platform init has initialized CMO and this implementation just checks if it is enabled.
In order to avoid compiler dependency injecting byte code. Code branch https://github.com/rivosinc/edk2/tree/dev_rv_cmo_v5

Test:
Ensured correct instructions are refelecting in asm
Able to boot platform with RiscVVirtQemu config
Not able to verify actual instruction in HW as Qemu ignores any actual cache operations.

Dhaval (2):
  MdePkg:Implement RISCV CMO
  OvmfPkg/RiscVVirt: Override for RV CPU Features

 MdePkg/MdePkg.dec                                                  |   7 +
 OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc                                |   2 +
 MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf |   3 +-
 MdePkg/Library/BaseLib/BaseLib.inf                                 |   2 +-
 MdePkg/Include/Register/RiscV64/RiscVEncoding.h                    |   6 +
 MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c                | 203 +++++++++++++++++---
 MdePkg/Library/BaseLib/RiscV64/FlushCache.S                        |  21 --
 MdePkg/Library/BaseLib/RiscV64/RiscVCacheMgmt.S                    |  38 ++++
 8 files changed, 236 insertions(+), 46 deletions(-)
 delete mode 100644 MdePkg/Library/BaseLib/RiscV64/FlushCache.S
 create mode 100644 MdePkg/Library/BaseLib/RiscV64/RiscVCacheMgmt.S

-- 
2.39.2



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