From nobody Fri May 17 12:54:58 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+109678+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+109678+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1697545085; cv=none; d=zohomail.com; s=zohoarc; b=jaCo5Q5COR18JGHR9YsKRKKaM0w4HrYbc5oX+za4w0AI+9H7kZLxvoCFvsXrKjoxDATRPbs4kIc0TH4J0kG+v0/beQdNi+wiGRPc6Hud6Rs75enmDRlXxXim1KMbJHGNO25F9WblJQvcVz885LC/y+TAoOW7ZAELr6FBRIs0BxA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1697545085; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=3joFV4xUXp25EaRxtJA/scvueGhzzH+oCTES2PEsWU8=; b=XFAMnv3eskHbCleDhh7141HvIPvyU1WCAW65SrJKZOgIjLzQFHj7QS8WkoiHgf5QvBAQmVt2KR1W5nN0o5V7Cdu0a/HJXSyzYwPlZPEbCZaC5/KsREFPSmYZveQlvkOxdQg7xI1QPukhsWpQG+MdQOZFmC/LUvQkx9q8pm30wog= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+109678+1787277+3901457@groups.io Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1697545085375699.0211578153541; Tue, 17 Oct 2023 05:18:05 -0700 (PDT) Return-Path: DKIM-Signature: a=rsa-sha256; bh=0WgN9oR2q6TGYpZVJp/+oA+dGe0xEMU9i/dGgRRyA4k=; c=relaxed/simple; d=groups.io; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References:MIME-Version:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Reply-To:List-Unsubscribe-Post:List-Unsubscribe:Content-Transfer-Encoding; s=20140610; t=1697545085; v=1; b=Ma0Fa+lBX6jDKVkUKtPF5jyBnCGk2SNpVSenCx0mg7MSbad6uWPuji0ieGKrIGLd1xb+Thys hrPMbxnvjS2q/Fjth3TalKy3KUFn181e4IE9MfDHKMBExmw9+F9c+RxB1lBg4RO+fMATUYCu0K2 SgE3dEkVPYLaWynHieBt6fKE= X-Received: by 127.0.0.2 with SMTP id GJMjYY1788612xi1tEYQ9kTR; Tue, 17 Oct 2023 05:18:05 -0700 X-Received: from mail-pg1-f173.google.com (mail-pg1-f173.google.com [209.85.215.173]) by mx.groups.io with SMTP id smtpd.web10.211977.1697545084126046218 for ; Tue, 17 Oct 2023 05:18:04 -0700 X-Received: by mail-pg1-f173.google.com with SMTP id 41be03b00d2f7-578b4997decso4149302a12.0 for ; Tue, 17 Oct 2023 05:18:03 -0700 (PDT) X-Gm-Message-State: 2Rv4iaEZgtcxkwm9vtBfFI99x1787277AA= X-Google-Smtp-Source: AGHT+IFGu/0ySPhRnlXBP/4Vq47+lLOKcRbImyaUJ6yOvfrBDdB1pnceJfwuakEhhWBD2cF8acG5nA== X-Received: by 2002:a05:6a21:18d:b0:159:beec:79ba with SMTP id le13-20020a056a21018d00b00159beec79bamr2128514pzb.2.1697545083167; Tue, 17 Oct 2023 05:18:03 -0700 (PDT) X-Received: from dhaval.. ([2401:4900:1c80:4a26:d125:5df7:226b:329]) by smtp.gmail.com with ESMTPSA id f7-20020a17090274c700b001c62b9a51a4sm1379511plt.239.2023.10.17.05.18.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Oct 2023 05:18:02 -0700 (PDT) From: "Dhaval Sharma" To: devel@edk2.groups.io Cc: Ard Biesheuvel , Jiewen Yao , Jordan Justen , Gerd Hoffmann , Sunil V L , Andrei Warkentin Subject: [edk2-devel] [PATCH v5 1/2] MdePkg:Implement RISCV CMO Date: Tue, 17 Oct 2023 17:47:54 +0530 Message-Id: <20231017121755.190285-2-dhaval@rivosinc.com> In-Reply-To: <20231017121755.190285-1-dhaval@rivosinc.com> References: <20231017121755.190285-1-dhaval@rivosinc.com> MIME-Version: 1.0 Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,dhaval@rivosinc.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1697545086454100005 Content-Type: text/plain; charset="utf-8" Implementing code to support Cache Management Operations (CMO) defined by RV spec https://github.com/riscv/riscv-CMOs Notes: 1. CMO only supports block based Operations. Meaning complete cache flush/invd/clean Operations are not available. In that case we fallback on fence.i instructions. 2. Rely on the fact that platform init has initialized CMO and this implementation just checks if it is enabled. 3. In order to avoid compiler dependency injecting byte code. Test: 1. Ensured correct instructions are refelecting in asm 2. Able to boot platform with RiscVVirtQemu config 3. Not able to verify actual instruction in HW as Qemu ignores any actual cache operations. Cc: Ard Biesheuvel Cc: Jiewen Yao Cc: Jordan Justen Cc: Gerd Hoffmann Cc: Sunil V L Cc: Andrei Warkentin Signed-off-by: Dhaval Sharma --- Notes: v5: - Addressed comments from v4 - Use #defines instead of numbers in cache instruction encoding - Addressed function naming issues from previous patch - Added new PCD to override RV CPU features - Removed code that relied on ENVCFG registers - Fixing typos in comments MdePkg/MdePkg.dec | 7 + MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf | 3 +- MdePkg/Library/BaseLib/BaseLib.inf | 2 +- MdePkg/Include/Register/RiscV64/RiscVEncoding.h | 6 + MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c | 203 += ++++++++++++++++--- MdePkg/Library/BaseLib/RiscV64/FlushCache.S | 21 -- MdePkg/Library/BaseLib/RiscV64/RiscVCacheMgmt.S | 38 += +++ 7 files changed, 234 insertions(+), 46 deletions(-) diff --git a/MdePkg/MdePkg.dec b/MdePkg/MdePkg.dec index ac54338089e8..2d06cf46b1ca 100644 --- a/MdePkg/MdePkg.dec +++ b/MdePkg/MdePkg.dec @@ -2399,6 +2399,13 @@ [PcdsFixedAtBuild.AARCH64, PcdsPatchableInModule.AAR= CH64] # @Prompt CPU Rng algorithm's GUID. gEfiMdePkgTokenSpaceGuid.PcdCpuRngSupportedAlgorithm|{0x00,0x00,0x00,0x0= 0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00}|VOID*|0x0000= 0037 =20 +[PcdsFixedAtBuild.RISCV64, PcdsPatchableInModule.RISCV64] + # + # Configurability to override RV CPU Features + # BIT 0 =3D CMO + # + gEfiMdePkgTokenSpaceGuid.PcdRVFeatureOverride|0x1|UINT64|0x69 + [PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamic, PcdsDynamicEx] ## This value is used to set the base address of PCI express hierarchy. # @Prompt PCI Express Base Address. diff --git a/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib= .inf b/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf index 6fd9cbe5f6c9..037a0b49800a 100644 --- a/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf +++ b/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf @@ -55,4 +55,5 @@ [Packages] [LibraryClasses] BaseLib DebugLib - +[Pcd] + gEfiMdePkgTokenSpaceGuid.PcdRVFeatureOverride diff --git a/MdePkg/Library/BaseLib/BaseLib.inf b/MdePkg/Library/BaseLib/Ba= seLib.inf index 03c7b02e828b..53389389448c 100644 --- a/MdePkg/Library/BaseLib/BaseLib.inf +++ b/MdePkg/Library/BaseLib/BaseLib.inf @@ -400,7 +400,7 @@ [Sources.RISCV64] RiscV64/RiscVCpuBreakpoint.S | GCC RiscV64/RiscVCpuPause.S | GCC RiscV64/RiscVInterrupt.S | GCC - RiscV64/FlushCache.S | GCC + RiscV64/RiscVCacheMgmt.S | GCC RiscV64/CpuScratch.S | GCC RiscV64/ReadTimer.S | GCC RiscV64/RiscVMmu.S | GCC diff --git a/MdePkg/Include/Register/RiscV64/RiscVEncoding.h b/MdePkg/Inclu= de/Register/RiscV64/RiscVEncoding.h index 2bde8db478ff..5d6dcab12f74 100644 --- a/MdePkg/Include/Register/RiscV64/RiscVEncoding.h +++ b/MdePkg/Include/Register/RiscV64/RiscVEncoding.h @@ -117,4 +117,10 @@ #define CAUSE_VIRTUAL_INST_FAULT 0x16 #define CAUSE_STORE_GUEST_PAGE_FAULT 0x17 =20 +#define CPU_FLUSH_CMO_ASM 0x0025200f + +#define CPU_CLEAN_CMO_ASM 0x0015200f + +#define CPU_INVLD_CMO_ASM 0x0005200f + #endif diff --git a/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c b/MdePkg/L= ibrary/BaseCacheMaintenanceLib/RiscVCache.c index d08fb9f193ca..bd8794e1d818 100644 --- a/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c +++ b/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c @@ -1,7 +1,8 @@ /** @file - RISC-V specific functionality for cache. + Implement Risc-V Cache Management Operations =20 Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All right= s reserved.
+ Copyright (c) 2023, Rivos Inc. All rights reserved.
=20 SPDX-License-Identifier: BSD-2-Clause-Patent **/ @@ -9,6 +10,17 @@ #include #include #include +#include + +// TODO: This will be removed once RISC-V CPU HOB is available +#define RV64_CACHE_BLOCK_SIZE 64 +#define RV_CPU_FEATURE_CMO_BITMASK 0x1 + +typedef enum { + Clean, + Flush, + Invld, +} CACHE_OP; =20 /** RISC-V invalidate instruction cache. @@ -16,7 +28,7 @@ **/ VOID EFIAPI -RiscVInvalidateInstCacheAsm ( +RiscVInvalidateInstCacheAsmFence ( VOID ); =20 @@ -26,13 +38,134 @@ RiscVInvalidateInstCacheAsm ( **/ VOID EFIAPI -RiscVInvalidateDataCacheAsm ( +RiscVInvalidateDataCacheAsmFence ( VOID ); =20 +/** + RISC-V flush cache block. Atomically perform a clean operation + followed by an invalidate operation + +**/ +VOID +EFIAPI +RiscVCpuCacheFlushAsmCbo ( + UINTN + ); + +/** +Perform a write transfer to another cache or to memory if the +data in the copy of the cache block have been modified by a store +operation + +**/ +VOID +EFIAPI +RiscVCpuCacheCleanAsmCbo ( + UINTN + ); + +/** +Deallocate the copy of the cache block + +**/ +VOID +EFIAPI +RiscVCpuCacheInvalAsmCbo ( + UINTN + ); + +/** +Verify CBOs are supported by this HW +TODO: Use RISC-V CPU HOB once available. + +**/ +UINT64 +RiscvIsCMOEnabled ( + VOID + ) +{ + // TODO: Add check for CMO from CPU HOB. + // If CMO is disabled in HW, skip Override check + // Otherwise this PCD can override settings + return (PcdGet64 (PcdRVFeatureOverride) & RV_CPU_FEATURE_CMO_BITMASK); +} + +/** + Performs required opeartion on cache lines in the cache coherency domain + of the calling CPU. If Address is not aligned on a cache line boundary, + then entire cache line containing Address is operated. If Address + Leng= th + is not aligned on a cache line boundary, then the entire cache line + containing Address + Length -1 is operated. + If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT(). + @param Address The base address of the cache lines to + invalidate. + @param Length The number of bytes to invalidate from the instruction + cache. + @param Op Type of CMO operation to be performed + @return Address. + +**/ +VOID * +EFIAPI +CacheOpCacheRange ( + IN VOID *Address, + IN UINTN Length, + IN CACHE_OP Op + ) +{ + UINTN CacheLineSize; + UINTN Start; + UINTN End; + + if (Length =3D=3D 0) { + return Address; + } + + ASSERT ((Length - 1) <=3D (MAX_ADDRESS - (UINTN)Address)); + + CacheLineSize =3D RV64_CACHE_BLOCK_SIZE; + + Start =3D (UINTN)Address; + // + // Calculate the cache line alignment + // + End =3D (Start + Length + (CacheLineSize - 1)) & ~(CacheLineSize - 1); + Start &=3D ~((UINTN)CacheLineSize - 1); + + DEBUG ( + (DEBUG_INFO, + "%a Performing Cache Management Operation %d \n", __func__, Op) + ); + + do { + switch (Op) { + case Invld: + RiscVCpuCacheInvalAsmCbo (Start); + break; + case Flush: + RiscVCpuCacheFlushAsmCbo (Start); + break; + case Clean: + RiscVCpuCacheCleanAsmCbo (Start); + break; + default: + DEBUG ((DEBUG_ERROR, "RISC-V unsupported operation\n")); + break; + } + + Start =3D Start + CacheLineSize; + } while (Start !=3D End); + + return Address; +} + /** Invalidates the entire instruction cache in cache coherency domain of the - calling CPU. + calling CPU. Risc-V does not have currently an CBO implementation which = can + invalidate entire I-cache. Hence using Fence instruction for now. P.S. F= ence + instruction may or may not implement full I-cache invd functionality on = all + implementations. =20 **/ VOID @@ -41,7 +174,7 @@ InvalidateInstructionCache ( VOID ) { - RiscVInvalidateInstCacheAsm (); + RiscVInvalidateInstCacheAsmFence (); } =20 /** @@ -76,12 +209,17 @@ InvalidateInstructionCacheRange ( IN UINTN Length ) { - DEBUG ( - (DEBUG_WARN, - "%a:RISC-V unsupported function.\n" - "Invalidating the whole instruction cache instead.\n", __func__) - ); - InvalidateInstructionCache (); + if (RiscvIsCMOEnabled () !=3D 0) { + CacheOpCacheRange (Address, Length, Invld); + } else { + DEBUG ( + (DEBUG_WARN, + "%a:RISC-V unsupported function.\n" + "Invalidating the whole instruction cache instead.\n", __func__) + ); + InvalidateInstructionCache (); + } + return Address; } =20 @@ -137,7 +275,12 @@ WriteBackInvalidateDataCacheRange ( IN UINTN Length ) { - DEBUG ((DEBUG_ERROR, "%a:RISC-V unsupported function.\n", __func__)); + if (RiscvIsCMOEnabled () !=3D 0) { + CacheOpCacheRange (Address, Length, Flush); + } else { + DEBUG ((DEBUG_ERROR, "%a:RISC-V unsupported function.\n", __func__)); + } + return Address; } =20 @@ -176,10 +319,7 @@ WriteBackDataCache ( =20 If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT(). =20 - @param Address The base address of the data cache lines to write back. = If - the CPU is in a physical addressing mode, then Address i= s a - physical address. If the CPU is in a virtual addressing - mode, then Address is a virtual address. + @param Address The base address of the data cache lines to write back. @param Length The number of bytes to write back from the data cache. =20 @return Address of cache written in main memory. @@ -192,7 +332,12 @@ WriteBackDataCacheRange ( IN UINTN Length ) { - DEBUG ((DEBUG_ERROR, "%a:RISC-V unsupported function.\n", __func__)); + if (RiscvIsCMOEnabled () !=3D 0) { + CacheOpCacheRange (Address, Length, Clean); + } else { + DEBUG ((DEBUG_ERROR, "%a:RISC-V unsupported function.\n", __func__)); + } + return Address; } =20 @@ -213,7 +358,12 @@ InvalidateDataCache ( VOID ) { - RiscVInvalidateDataCacheAsm (); + DEBUG ( + (DEBUG_WARN, + "%a:RISC-V unsupported function.\n" + "Invalidating the whole Data cache instead.\n", __func__) + ); + RiscVInvalidateDataCacheAsmFence (); } =20 /** @@ -234,10 +384,7 @@ InvalidateDataCache ( =20 If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT(). =20 - @param Address The base address of the data cache lines to invalidate. = If - the CPU is in a physical addressing mode, then Address i= s a - physical address. If the CPU is in a virtual addressing = mode, - then Address is a virtual address. + @param Address The base address of the data cache lines to invalidate. @param Length The number of bytes to invalidate from the data cache. =20 @return Address. @@ -250,6 +397,16 @@ InvalidateDataCacheRange ( IN UINTN Length ) { - DEBUG ((DEBUG_ERROR, "%a:RISC-V unsupported function.\n", __func__)); + if (RiscvIsCMOEnabled () !=3D 0) { + CacheOpCacheRange (Address, Length, Invld); + } else { + DEBUG ( + (DEBUG_WARN, + "%a:RISC-V unsupported function.\n" + "Invalidating the whole Data cache instead.\n", __func__) + ); + InvalidateDataCache (); + } + return Address; } diff --git a/MdePkg/Library/BaseLib/RiscV64/FlushCache.S b/MdePkg/Library/B= aseLib/RiscV64/FlushCache.S deleted file mode 100644 index 7c10fdd268af..000000000000 --- a/MdePkg/Library/BaseLib/RiscV64/FlushCache.S +++ /dev/null @@ -1,21 +0,0 @@ -//------------------------------------------------------------------------= ------ -// -// RISC-V cache operation. -// -// Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
-// -// SPDX-License-Identifier: BSD-2-Clause-Patent -// -//------------------------------------------------------------------------= ------ - -.align 3 -ASM_GLOBAL ASM_PFX(RiscVInvalidateInstCacheAsm) -ASM_GLOBAL ASM_PFX(RiscVInvalidateDataCacheAsm) - -ASM_PFX(RiscVInvalidateInstCacheAsm): - fence.i - ret - -ASM_PFX(RiscVInvalidateDataCacheAsm): - fence - ret diff --git a/MdePkg/Library/BaseLib/RiscV64/RiscVCacheMgmt.S b/MdePkg/Libra= ry/BaseLib/RiscV64/RiscVCacheMgmt.S new file mode 100644 index 000000000000..f9b79446b56a --- /dev/null +++ b/MdePkg/Library/BaseLib/RiscV64/RiscVCacheMgmt.S @@ -0,0 +1,38 @@ +//------------------------------------------------------------------------= ------ +// +// RISC-V cache operation. +// +// Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
+// Copyright (c) 2022, Rivos Inc. All rights reserved.
+// +// SPDX-License-Identifier: BSD-2-Clause-Patent +// +//------------------------------------------------------------------------= ------ +#include + +.align 3 +ASM_GLOBAL ASM_PFX(RiscVInvalidateInstCacheAsmFence) +ASM_GLOBAL ASM_PFX(RiscVInvalidateDataCacheAsmFence) + +ASM_PFX(RiscVInvalidateInstCacheAsmFence): + fence.i + ret + +ASM_PFX(RiscVInvalidateDataCacheAsmFence): + fence + ret + +ASM_GLOBAL ASM_PFX (RiscVCpuCacheFlushAsmCbo) +ASM_PFX (RiscVCpuCacheFlushAsmCbo): + .long CPU_FLUSH_CMO_ASM + ret + +ASM_GLOBAL ASM_PFX (RiscVCpuCacheCleanAsmCbo) +ASM_PFX (RiscVCpuCacheCleanAsmCbo): + .long CPU_CLEAN_CMO_ASM + ret + +ASM_GLOBAL ASM_PFX (RiscVCpuCacheInvalAsmCbo) +ASM_PFX (RiscVCpuCacheInvalAsmCbo): + .long CPU_INVLD_CMO_ASM + ret --=20 2.39.2 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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([2401:4900:1c80:4a26:d125:5df7:226b:329]) by smtp.gmail.com with ESMTPSA id f7-20020a17090274c700b001c62b9a51a4sm1379511plt.239.2023.10.17.05.18.03 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Oct 2023 05:18:04 -0700 (PDT) From: "Dhaval Sharma" To: devel@edk2.groups.io Subject: [edk2-devel] [PATCH v5 2/2] OvmfPkg/RiscVVirt: Override for RV CPU Features Date: Tue, 17 Oct 2023 17:47:55 +0530 Message-Id: <20231017121755.190285-3-dhaval@rivosinc.com> In-Reply-To: <20231017121755.190285-1-dhaval@rivosinc.com> References: <20231017121755.190285-1-dhaval@rivosinc.com> MIME-Version: 1.0 Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,dhaval@rivosinc.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1697545088415100011 Content-Type: text/plain; charset="utf-8" This PCD provides a way for platform to override any HW features that are default enabled by previous stages of FW (like OpenSBI). For the case where previous/prev stage has disabled the feature, this override is not useful and its usage should be avoided. Ard Biesheuvel Jiewen Yao Jordan Justen Gerd Hoffmann Sunil V L Andrei Warkentin Signed-off-by: Dhaval Sharma --- OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc | 2 ++ 1 file changed, 2 insertions(+) diff --git a/OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc b/OvmfPkg/RiscVVirt/RiscVV= irt.dsc.inc index fe320525153f..8b5e010316ba 100644 --- a/OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc +++ b/OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc @@ -203,6 +203,8 @@ [PcdsFeatureFlag] gEfiMdeModulePkgTokenSpaceGuid.PcdInstallAcpiSdtProtocol|TRUE =20 [PcdsFixedAtBuild.common] + gEfiMdePkgTokenSpaceGuid.PcdRVFeatureOverride|0 + gEfiMdePkgTokenSpaceGuid.PcdMaximumUnicodeStringLength|1000000 gEfiMdePkgTokenSpaceGuid.PcdMaximumAsciiStringLength|1000000 gEfiMdePkgTokenSpaceGuid.PcdMaximumLinkedListLength|0 --=20 2.39.2 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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