REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4468
Take a step towards enabling a generic approach to manage memory
permissions in PEI, by wiring up the existing IA32 page table creation
logic in CpuMpPei for X64 as well. This will enable future work to expose
a PPI that is available throughout PEI to manage memory permissions in a
generic manner across architectures.
The DxeIpl that implements this logic today will be made redundant by
this, and we should be able to retire it once the replacement pieces are
all in place.
Cc: Ray Ni <ray.ni@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Gerd Hoffmann <kraxel@redhat.com>
Cc: Taylor Beebe <t@taylorbeebe.com>
Cc: Oliver Smith-Denny <osd@smith-denny.com>
Cc: Dandan Bi <dandan.bi@intel.com>
Cc: Dun Tan <dun.tan@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: "Kinney, Michael D" <michael.d.kinney@intel.com>
Cc: Michael Kubacki <mikuback@linux.microsoft.com>
Cc: Eric Dong <eric.dong@intel.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
Cc: Kun Qin <kuqin12@gmail.com>
Ard Biesheuvel (2):
UefiCpuPkg/CpuMpPei: Print correct buffer size used for page table
UefiCpuPkg/CpuMpPei X64: Reallocate page tables in permanent DRAM
UefiCpuPkg/CpuMpPei/CpuMpPei.inf | 2 +
UefiCpuPkg/CpuMpPei/CpuPaging.c | 187 ++++++++++++++++----
2 files changed, 151 insertions(+), 38 deletions(-)
--
2.39.2
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