From nobody Fri May 17 03:00:42 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+105942+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+105942+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=kernel.org ARC-Seal: i=1; a=rsa-sha256; t=1686245020; cv=none; d=zohomail.com; s=zohoarc; b=JUk/MP59kLP8azo0rlZBlqk4rbpz3DyAyrt5XCf1Bt4F5sC7+3Um/+4cwJYm2NFKqVd3foCc5PboO6YZ0gza0wrjifjF9pGwxIyf9t3WmoMKgMEfcPL5+XJpoD2DKYthyB/HLYyG+1qnsbjd2vFhYQAsDEDmCd/Q6F1+AgqMrag= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1686245020; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=j4En9xbfCF62eN7OGE26DqR8RSGtWf4mxA4rUwmhkjU=; b=YFretCIdGhVJK/+9MAA/n6dcHKtW02dUUUTTPNzxaFWu6GROfe6QXlX+7rrAcaMUanSPmILhgtA0C2gjkhN70Zxe9t6kIHw48yzGsoZX13br4XxKuJkfSkCKtpUSUbkO5qN0eUkHcXbESuMHZhn/rnYZXSJaNsJmo3piSFVGGFc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+105942+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1686245020211426.29467509684594; Thu, 8 Jun 2023 10:23:40 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id KxicYY1788612xunK2Mi4YuY; Thu, 08 Jun 2023 10:23:39 -0700 X-Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by mx.groups.io with SMTP id smtpd.web10.127.1686245019028191765 for ; Thu, 08 Jun 2023 10:23:39 -0700 X-Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 9528160DBD; Thu, 8 Jun 2023 17:23:38 +0000 (UTC) X-Received: by smtp.kernel.org (Postfix) with ESMTPSA id 10B26C433EF; Thu, 8 Jun 2023 17:23:34 +0000 (UTC) From: "Ard Biesheuvel" To: devel@edk2.groups.io Cc: Ard Biesheuvel , Ray Ni , Jiewen Yao , Gerd Hoffmann , Taylor Beebe , Oliver Smith-Denny , Dandan Bi , Dun Tan , Liming Gao , "Kinney, Michael D" , Michael Kubacki , Eric Dong , Rahul Kumar , Kun Qin Subject: [edk2-devel] [PATCH 1/2] UefiCpuPkg/CpuMpPei: Print correct buffer size used for page table Date: Thu, 8 Jun 2023 19:23:22 +0200 Message-Id: <20230608172323.9096-2-ardb@kernel.org> In-Reply-To: <20230608172323.9096-1-ardb@kernel.org> References: <20230608172323.9096-1-ardb@kernel.org> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,ardb@kernel.org X-Gm-Message-State: sM6y3zLR00tLyXy3STvcPdu4x1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1686245019; bh=NN6lFfMdM3p5BX0vSxkuhmFQ4CehJILTGQV60cL61t8=; h=Cc:Date:From:Reply-To:Subject:To; b=SntpQ+hzWwLY4gInWBPJKaoPBHNq3NntBZadO+H0FXHw0b8P5dN9OGh7JPY6vcRQKjV hbvvcJuNqYfwnJsr1dIetjWAJTruYvI5NByD3LoCRTq7VOdSclHkzZozOBWDgran4sd2z gwmGWQvUc5tvxfbkyqtLtvuRctWpsy3Vt5E= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1686245020759100005 Content-Type: text/plain; charset="utf-8" The DEBUG print that outputs the base and size of the page table allocation always prints 0x0 for the size, given that BufferSize will be updated by PageTableMap () and contain the unused allocation on return. So move the DEBUG print right after the allocation. Signed-off-by: Ard Biesheuvel Reviewed-by: Michael Kubacki --- UefiCpuPkg/CpuMpPei/CpuPaging.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/UefiCpuPkg/CpuMpPei/CpuPaging.c b/UefiCpuPkg/CpuMpPei/CpuPagin= g.c index b7ddb0005b6fbcac..175e47ccd737a0c1 100644 --- a/UefiCpuPkg/CpuMpPei/CpuPaging.c +++ b/UefiCpuPkg/CpuMpPei/CpuPaging.c @@ -396,6 +396,13 @@ EnablePaePageTable ( return EFI_OUT_OF_RESOURCES; } =20 + DEBUG (( + DEBUG_INFO, + "EnablePaePageTable: Created PageTable =3D 0x%x, BufferSize =3D %x\n", + PageTable, + BufferSize + )); + Status =3D PageTableMap (&PageTable, PagingPae, Buffer, &BufferSize, 0, = SIZE_4GB, &MapAttribute, &MapMask, NULL); ASSERT_EFI_ERROR (Status); if (EFI_ERROR (Status) || (PageTable =3D=3D 0)) { @@ -417,13 +424,6 @@ EnablePaePageTable ( // AsmWriteCr0 (AsmReadCr0 () | BIT31); =20 - DEBUG (( - DEBUG_INFO, - "EnablePaePageTable: Created PageTable =3D 0x%x, BufferSize =3D %x\n", - PageTable, - BufferSize - )); - return Status; } =20 --=20 2.39.2 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#105942): https://edk2.groups.io/g/devel/message/105942 Mute This Topic: https://groups.io/mt/99411874/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Fri May 17 03:00:42 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+105943+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+105943+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=kernel.org ARC-Seal: i=1; a=rsa-sha256; t=1686245023; cv=none; d=zohomail.com; s=zohoarc; b=NIJJU4/BMjmwt43uVWZQ5KpTq6o4LB8cH7XMZ/qDxe3cUH9FGPMMGssFMgZ2Y0stVrAnCq0fZG1SlJ+K5BDjeBtowauwYrTAMMQuaj9n65V1qt8SkxhRxj6OFwCg/TFspSEveAG0Cxv/Y/ozL8KTpy2/Alcsk/+JSwS2ylLsaHg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1686245023; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=dYr2ekeq2B2aoiBYq7E26pmdenbDJ1QWGnFS2sdsamU=; b=lGj6nxOWy4rkZ68ytvhGk69PdhFZFMTpfiNHAtIsQ1a0pldigkualcckm2BItVBkzYM4ASBCv10PXGhmWDxQzX5uOqUrSP7Y7LKSwOBwugqojgmZXyd0OTC0osLlMJwmk1+IryTrXDddgNI2kAvx4gh9L5GwG2f4cqbGdshE7u4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+105943+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1686245023544835.6656360514365; Thu, 8 Jun 2023 10:23:43 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id pN7hYY1788612xGT4jRY3z3c; Thu, 08 Jun 2023 10:23:43 -0700 X-Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by mx.groups.io with SMTP id smtpd.web11.115.1686245022561638053 for ; Thu, 08 Jun 2023 10:23:42 -0700 X-Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 0EC3964FBB; Thu, 8 Jun 2023 17:23:42 +0000 (UTC) X-Received: by smtp.kernel.org (Postfix) with ESMTPSA id 77525C4339C; Thu, 8 Jun 2023 17:23:38 +0000 (UTC) From: "Ard Biesheuvel" To: devel@edk2.groups.io Cc: Ard Biesheuvel , Ray Ni , Jiewen Yao , Gerd Hoffmann , Taylor Beebe , Oliver Smith-Denny , Dandan Bi , Dun Tan , Liming Gao , "Kinney, Michael D" , Michael Kubacki , Eric Dong , Rahul Kumar , Kun Qin Subject: [edk2-devel] [PATCH 2/2] UefiCpuPkg/CpuMpPei X64: Reallocate page tables in permanent DRAM Date: Thu, 8 Jun 2023 19:23:23 +0200 Message-Id: <20230608172323.9096-3-ardb@kernel.org> In-Reply-To: <20230608172323.9096-1-ardb@kernel.org> References: <20230608172323.9096-1-ardb@kernel.org> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,ardb@kernel.org X-Gm-Message-State: K6cR3U2b4QyVkPELh3y3Xxp7x1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1686245023; bh=g25aDUhQTr7e6UhsfALtAbwDT6DXwD366H+8jKBSjFc=; h=Cc:Date:From:Reply-To:Subject:To; b=kOBxM49ISJ3Xwkudb1bI4iRZZPxJiVxcMNedLUiKOa/Aoj+2kQvqE0akcveN5R8pCYM C2grhZ/4I5WhGNdexFlRvxsriSS8GKX8LgA51YI6BXN1WYPPGE1thDPzOMsqh2fQ7hYlX +7d8MMzi+NbZNfcyU/TKy/ykhX929hwxVX4= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1686245024403100001 Content-Type: text/plain; charset="utf-8" Currently, we rely on the logic in DXE IPL to create new page tables from scratch when executing in X64 mode, which means that we run with the initial page tables all throughout PEI, and never enable protections such as the CPU stack guard, even though the logic is already in place for IA32. So let's enable the existing logic for X64 as well. This will permit us to apply stricter memory permissions to code and data allocations, as well as the stack, when executing in PEI. It also makes the DxeIpl logic redundant, and should allow us to make the PcdDxeIplBuildPageTables feature PCD limited to IA32 DxeIpl loading the x64 DXE core. When running in long mode, use the same logic that DxeIpl uses to determine the size of the address space, whether or not to use 1 GB leaf entries and whether or not to use 5 level paging. Note that in long mode, PEI is entered with paging enabled, and given that switching between 4 and 5 levels of paging is not currently supported without dropping out of 64-bit mode temporarily, all we can do is carry on without changing the number of levels. Signed-off-by: Ard Biesheuvel --- UefiCpuPkg/CpuMpPei/CpuMpPei.inf | 2 + UefiCpuPkg/CpuMpPei/CpuPaging.c | 163 ++++++++++++++++---- 2 files changed, 139 insertions(+), 26 deletions(-) diff --git a/UefiCpuPkg/CpuMpPei/CpuMpPei.inf b/UefiCpuPkg/CpuMpPei/CpuMpPe= i.inf index 865be5627e8551ee..77eecaa0ea035b38 100644 --- a/UefiCpuPkg/CpuMpPei/CpuMpPei.inf +++ b/UefiCpuPkg/CpuMpPei/CpuMpPei.inf @@ -65,6 +65,8 @@ [Ppis] [Pcd] gEfiMdeModulePkgTokenSpaceGuid.PcdPteMemoryEncryptionAddressOrMask ##= CONSUMES gEfiMdeModulePkgTokenSpaceGuid.PcdCpuStackGuard ##= CONSUMES + gEfiMdeModulePkgTokenSpaceGuid.PcdUse1GPageTable ##= SOMETIMES_CONSUMES + gEfiMdeModulePkgTokenSpaceGuid.PcdUse5LevelPageTable ##= SOMETIMES_CONSUMES gUefiCpuPkgTokenSpaceGuid.PcdCpuStackSwitchExceptionList ##= SOMETIMES_CONSUMES gUefiCpuPkgTokenSpaceGuid.PcdCpuKnownGoodStackSize ##= SOMETIMES_CONSUMES gUefiCpuPkgTokenSpaceGuid.PcdCpuApStackSize ##= SOMETIMES_CONSUMES diff --git a/UefiCpuPkg/CpuMpPei/CpuPaging.c b/UefiCpuPkg/CpuMpPei/CpuPagin= g.c index 175e47ccd737a0c1..2a901e44253434c2 100644 --- a/UefiCpuPkg/CpuMpPei/CpuPaging.c +++ b/UefiCpuPkg/CpuMpPei/CpuPaging.c @@ -302,7 +302,7 @@ ConvertMemoryPageAttributes ( return RETURN_INVALID_PARAMETER; } =20 - MaximumAddress =3D (EFI_PHYSICAL_ADDRESS)MAX_UINT32; + MaximumAddress =3D (EFI_PHYSICAL_ADDRESS)MAX_ADDRESS; if ((BaseAddress > MaximumAddress) || (Length > MaximumAddress) || (BaseAddress > MaximumAddress - (Length - 1))) @@ -350,16 +350,91 @@ ConvertMemoryPageAttributes ( return RETURN_SUCCESS; } =20 +/* + * Get physical address bits supported. + * + * @return The number of supported physical address bits. + */ +STATIC +UINT8 +GetPhysicalAddressBits ( + VOID + ) +{ + EFI_HOB_CPU *Hob; + UINT32 RegEax; + + Hob =3D GetFirstHob (EFI_HOB_TYPE_CPU); + if (Hob !=3D NULL) { + return Hob->SizeOfMemorySpace; + } + + AsmCpuid (0x80000000, &RegEax, NULL, NULL, NULL); + if (RegEax >=3D 0x80000008) { + AsmCpuid (0x80000008, &RegEax, NULL, NULL, NULL); + return (UINT8)RegEax; + } + + return 36; +} + +/* + * Determine and return the paging mode to be used in long mode, based on = PCD + * configuration and CPU support for 1G leaf descriptors and 5 level pagin= g. + * + * @return The paging mode + */ +STATIC +PAGING_MODE +GetPagingMode ( + VOID + ) +{ + BOOLEAN Page5LevelSupport; + BOOLEAN Page1GSupport; + UINT32 RegEax; + UINT32 RegEdx; + IA32_CR4 Cr4; + + Cr4.UintN =3D AsmReadCr4 (); + Page5LevelSupport =3D (Cr4.Bits.LA57 !=3D 0); + ASSERT (PcdGetBool (PcdUse5LevelPageTable) =3D=3D Page5LevelSupport); + + Page1GSupport =3D FALSE; + if (PcdGetBool (PcdUse1GPageTable)) { + AsmCpuid (0x80000000, &RegEax, NULL, NULL, NULL); + if (RegEax >=3D 0x80000001) { + AsmCpuid (0x80000001, NULL, NULL, NULL, &RegEdx); + if ((RegEdx & BIT26) !=3D 0) { + Page1GSupport =3D TRUE; + } + } + } + + if (Page5LevelSupport && Page1GSupport) { + return Paging5Level1GB; + } else if (Page5LevelSupport) { + return Paging5Level; + } else if (Page1GSupport) { + return Paging4Level1GB; + } else { + return Paging4Level; + } +} + /** - Enable PAE Page Table. + Enable Page Table. =20 - @retval EFI_SUCCESS The PAE Page Table was enabled successfu= lly. - @retval EFI_OUT_OF_RESOURCES The PAE Page Table could not be enabled = due to lack of available memory. + @param LongMode Whether the execution mode is 64 bit + + @retval EFI_SUCCESS The Page Table was enabled successfully. + @retval EFI_OUT_OF_RESOURCES The Page Table could not be enabled due = to lack of available memory. =20 **/ +STATIC EFI_STATUS -EnablePaePageTable ( - VOID +EnablePageTable ( + IN BOOLEAN LongMode ) { EFI_STATUS Status; @@ -369,6 +444,8 @@ EnablePaePageTable ( UINTN BufferSize; IA32_MAP_ATTRIBUTE MapAttribute; IA32_MAP_ATTRIBUTE MapMask; + PAGING_MODE PagingMode; + UINT64 Length; =20 PageTable =3D 0; Buffer =3D NULL; @@ -378,10 +455,28 @@ EnablePaePageTable ( MapAttribute.Bits.Present =3D 1; MapAttribute.Bits.ReadWrite =3D 1; =20 - // - // 1:1 map 4GB in 32bit mode - // - Status =3D PageTableMap (&PageTable, PagingPae, 0, &BufferSize, 0, SIZE_= 4GB, &MapAttribute, &MapMask, NULL); + if (!LongMode) { + // + // 1:1 map 4GB in 32bit mode + // + PagingMode =3D PagingPae; + Length =3D SIZE_4GB; + } else { + PagingMode =3D GetPagingMode (); + Length =3D LShiftU64 (1, GetPhysicalAddressBits ()); + } + + Status =3D PageTableMap ( + &PageTable, + PagingMode, + 0, + &BufferSize, + 0, + Length, + &MapAttribute, + &MapMask, + NULL + ); ASSERT (Status =3D=3D EFI_BUFFER_TOO_SMALL); if (Status !=3D EFI_BUFFER_TOO_SMALL) { return Status; @@ -398,12 +493,23 @@ EnablePaePageTable ( =20 DEBUG (( DEBUG_INFO, - "EnablePaePageTable: Created PageTable =3D 0x%x, BufferSize =3D %x\n", + "%a: Created PageTable =3D 0x%x, BufferSize =3D %x\n", + __func__, PageTable, BufferSize )); =20 - Status =3D PageTableMap (&PageTable, PagingPae, Buffer, &BufferSize, 0, = SIZE_4GB, &MapAttribute, &MapMask, NULL); + Status =3D PageTableMap ( + &PageTable, + PagingMode, + Buffer, + &BufferSize, + 0, + Length, + &MapAttribute, + &MapMask, + NULL + ); ASSERT_EFI_ERROR (Status); if (EFI_ERROR (Status) || (PageTable =3D=3D 0)) { return EFI_OUT_OF_RESOURCES; @@ -414,15 +520,17 @@ EnablePaePageTable ( // AsmWriteCr3 (PageTable); =20 - // - // Enable CR4.PAE - // - AsmWriteCr4 (AsmReadCr4 () | BIT5); + if (!LongMode) { + // + // Enable CR4.PAE + // + AsmWriteCr4 (AsmReadCr4 () | BIT5); =20 - // - // Enable CR0.PG - // - AsmWriteCr0 (AsmReadCr0 () | BIT31); + // + // Enable CR0.PG + // + AsmWriteCr0 (AsmReadCr0 () | BIT31); + } =20 return Status; } @@ -557,6 +665,9 @@ MemoryDiscoveredPpiNotifyCallback ( EDKII_MIGRATED_FV_INFO *MigratedFvInfo; EFI_PEI_HOB_POINTERS Hob; IA32_CR0 Cr0; + BOOLEAN LongMode; + + LongMode =3D (sizeof (UINTN) =3D=3D sizeof (UINT64)); =20 // // Paging must be setup first. Otherwise the exception TSS setup during = MP @@ -565,7 +676,7 @@ MemoryDiscoveredPpiNotifyCallback ( // InitStackGuard =3D FALSE; Hob.Raw =3D NULL; - if (IsIa32PaeSupported ()) { + if (LongMode || IsIa32PaeSupported ()) { Hob.Raw =3D GetFirstGuidHob (&gEdkiiMigratedFvInfoGuid); InitStackGuard =3D PcdGetBool (PcdCpuStackGuard); } @@ -575,12 +686,12 @@ MemoryDiscoveredPpiNotifyCallback ( // is to enable paging if it is not enabled (only in 32bit mode). // Cr0.UintN =3D AsmReadCr0 (); - if ((Cr0.Bits.PG =3D=3D 0) && (InitStackGuard || (Hob.Raw !=3D NULL))) { - ASSERT (sizeof (UINTN) =3D=3D sizeof (UINT32)); - - Status =3D EnablePaePageTable (); + if (LongMode || + ((Cr0.Bits.PG =3D=3D 0) && (InitStackGuard || (Hob.Raw !=3D NULL)))) + { + Status =3D EnablePageTable (LongMode); if (EFI_ERROR (Status)) { - DEBUG ((DEBUG_ERROR, "MemoryDiscoveredPpiNotifyCallback: Failed to e= nable PAE page table: %r.\n", Status)); + DEBUG ((DEBUG_ERROR, "%a: Failed to enable page table: %r.\n", __fun= c__, Status)); CpuDeadLoop (); } } --=20 2.39.2 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#105943): https://edk2.groups.io/g/devel/message/105943 Mute This Topic: https://groups.io/mt/99411875/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-