Below serial patches are to support the SMM Relocated SmBase handling.
To achieve, new hob interface is procuded, and will be consumed by SMM
CPU driver & SmmCpuFeaturesLib to do SmBase initialization:

The Smm Base HOB is used to store the relocated SmBase in
array for each Processors. If gSmmBaseHobGuid produced,
indicate SmBase for each Processors have been relocated.
The SmBase address in hob can be guaranteed the SMRAM state
save areas for all processors do not overlap.

SMM CPU driver will retrieve the SMBASE addresses from SMM Base Hob
and installs the SMI handler at [SMBASE+8000h] for each processor
instead of relocating SMM Base addresses from SMRAM again.

With SMM Base Hob, SMM CPU driver does not need the RSM instruction
to reload the SMBASE register with the new allocated value in SMBASE
field each time it exits SMM. SMBASE Register for each processors
have already been programmed in parallel since the same default
SMBASE Address(0x30000) is not used, thus the CPUs over-writing
each other's SMM Save State Area will not happen. This way will save
boot time on multi-core system.

Beside, If gSmmBaseHobGuid found, no need to do the relocation in
SmmCpuFeaturesInitializeProcessor().

Jiaxin Wu (4):
  UefiCpuPkg/SmmBaseHob.h: Add SMM Base HOB Data
  UefiCpuPkg/PiSmmCpuDxeSmm: Consume SMM Base Hob for SmBase info
  UefiCpuPkg/SmmCpuFeaturesLib: Skip to configure SMBASE
  OvmfPkg/SmmCpuFeaturesLib: Skip to configure SMBASE

 .../Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c  |  39 ++++--
 .../SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf        |   4 +
 UefiCpuPkg/Include/Guid/SmmBaseHob.h               |  51 +++++++
 .../Library/SmmCpuFeaturesLib/CpuFeaturesLib.h     |   2 +
 .../SmmCpuFeaturesLib/IntelSmmCpuFeaturesLib.c     |  25 +++-
 .../SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf        |   4 +
 .../SmmCpuFeaturesLib/SmmCpuFeaturesLibStm.inf     |   1 +
 UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.c      |   1 -
 .../StandaloneMmCpuFeaturesLib.inf                 |   4 +
 UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c                  |  40 +++++-
 UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c              |  25 +++-
 UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c         | 155 ++++++++++++++++-----
 UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h         |  21 ++-
 UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf       |   1 +
 UefiCpuPkg/UefiCpuPkg.dec                          |   3 +
 15 files changed, 318 insertions(+), 58 deletions(-)
 create mode 100644 UefiCpuPkg/Include/Guid/SmmBaseHob.h

-- 
2.16.2.windows.1



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On Fri, Jan 13, 2023 at 03:17:34PM +0800, Wu, Jiaxin wrote:
> Below serial patches are to support the SMM Relocated SmBase handling.
> To achieve, new hob interface is procuded, and will be consumed by SMM
> CPU driver & SmmCpuFeaturesLib to do SmBase initialization:

The series breaks s3 suspend in ovmf.

take care,
  Gerd



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Hi Gerd,

I made some fix for the s3 flow with patch set v2, and now pass the CI check, you can review directly on PR https://github.com/tianocore/edk2/pull/3884

Thanks,
Jiaxin

> -----Original Message-----
> From: Gerd Hoffmann <kraxel@redhat.com>
> Sent: Friday, January 13, 2023 8:45 PM
> To: devel@edk2.groups.io; Wu, Jiaxin <jiaxin.wu@intel.com>
> Subject: Re: [edk2-devel] [PATCH v1 0/4] Support SMM Relocated SmBase
> handling
> 
> On Fri, Jan 13, 2023 at 03:17:34PM +0800, Wu, Jiaxin wrote:
> > Below serial patches are to support the SMM Relocated SmBase handling.
> > To achieve, new hob interface is procuded, and will be consumed by SMM
> > CPU driver & SmmCpuFeaturesLib to do SmBase initialization:
> 
> The series breaks s3 suspend in ovmf.
> 
> take care,
>   Gerd



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Gerd, 

Could you share me the steps to build OVMF & run the test? I did the OVMF related test almost 5 year ago, I forgot how to enable the OVFM in windows☹. 

Thanks,
Jiaxin 


> -----Original Message-----
> From: Gerd Hoffmann <kraxel@redhat.com>
> Sent: Friday, January 13, 2023 8:45 PM
> To: devel@edk2.groups.io; Wu, Jiaxin <jiaxin.wu@intel.com>
> Subject: Re: [edk2-devel] [PATCH v1 0/4] Support SMM Relocated SmBase
> handling
> 
> On Fri, Jan 13, 2023 at 03:17:34PM +0800, Wu, Jiaxin wrote:
> > Below serial patches are to support the SMM Relocated SmBase handling.
> > To achieve, new hob interface is procuded, and will be consumed by SMM
> > CPU driver & SmmCpuFeaturesLib to do SmBase initialization:
> 
> The series breaks s3 suspend in ovmf.
> 
> take care,
>   Gerd



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On Fri, Jan 13, 2023 at 03:17:34PM +0800, Wu, Jiaxin wrote:
> Below serial patches are to support the SMM Relocated SmBase handling.
> To achieve, new hob interface is procuded, and will be consumed by SMM
> CPU driver & SmmCpuFeaturesLib to do SmBase initialization:

Who produces that HOB?  I see only consumers in this patch series.

The patch series doesn't even pass BaseTools/Scripts/PatchCheck.py,
it will surely not pass CI.

> With SMM Base Hob, SMM CPU driver does not need the RSM instruction
> to reload the SMBASE register with the new allocated value in SMBASE
> field each time it exits SMM. SMBASE Register for each processors
> have already been programmed in parallel since the same default
> SMBASE Address(0x30000) is not used, thus the CPUs over-writing
> each other's SMM Save State Area will not happen.

Care to explain how this works?  SMBASE setup has to happen somewhere
(probably in the HOB producer), how does that work without using the
default smbase address?

take care,
  Gerd



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For simple, this change will keep compatibility with the lack of the HOB. When the HOB doesn't exist, PiSmmCpuDxeSmm driver will keep the original logic to program the new SMBASE in driver itself.


> -----Original Message-----
> From: Wu, Jiaxin
> Sent: Friday, January 13, 2023 6:19 PM
> To: Gerd Hoffmann <kraxel@redhat.com>; devel@edk2.groups.io
> Subject: RE: [edk2-devel] [PATCH v1 0/4] Support SMM Relocated SmBase
> handling
> 
> Thanks Comments Gerd, I will resolve the CI check issue (I have noticed that
> in https://github.com/tianocore/edk2/pull/3884) & refine the usage
> description in next version.
> 
> Anyway, Ray also helped explain the usage as below, I will integrate it in the
> hob definition .h file, help below can help understand the design.:
> 
> The default SMBASE for the x86 processor is 0x30000. When SMI happens,
> CPU runs the
> SMI handler at SMBASE+0x8000. Also, the SMM save state area is within
> SMBASE+0x10000.
> 
> One of the SMM initialization from CPU perspective is to program the new
> SMBASE (in TSEG range)
> for each CPU thread. When the SMBASE update happens in a PEI module,
> the PEI module shall
> produce the SMM_BASE_HOB in HOB database which tells the
> PiSmmCpuDxeSmm driver which runs
> at a later phase about the new SMBASE for each CPU thread.
> PiSmmCpuDxeSmm driver installs
> the SMI handler at the SMM_BASE_HOB.SmBase[Index]+0x8000 for CPU
> thread Index.
> When the HOB doesn't exist, PiSmmCpuDxeSmm driver shall program the
> new SMBASE itself.
> 
> I also explain the in the patch 2 for PiSmmCpuDxeSmm changes:
> 
> SMM CPU driver will retrieve the SMBASE addresses from SMM Base Hob
> and installs the SMI handler at [SMBASE+8000h] for each processor
> instead of relocating SMM Base addresses from SMRAM again.
> 
> With SMM Base Hob, SMM CPU driver does not need the RSM instruction
> to reload the SMBASE register with the new allocated value in SMBASE
> field each time it exits SMM. SMBASE Register for each processors
> have already been programmed in parallel since the same default
> SMBASE Address(0x30000) is not used, thus the CPUs over-writing
> each other's SMM Save State Area will not happen. This way will save
> boot time on multi-core system
> 
> 
> thanks,
> Jiaxin
> 
> 
> > -----Original Message-----
> > From: Gerd Hoffmann <kraxel@redhat.com>
> > Sent: Friday, January 13, 2023 5:50 PM
> > To: devel@edk2.groups.io; Wu, Jiaxin <jiaxin.wu@intel.com>
> > Subject: Re: [edk2-devel] [PATCH v1 0/4] Support SMM Relocated SmBase
> > handling
> >
> > On Fri, Jan 13, 2023 at 03:17:34PM +0800, Wu, Jiaxin wrote:
> > > Below serial patches are to support the SMM Relocated SmBase handling.
> > > To achieve, new hob interface is procuded, and will be consumed by
> SMM
> > > CPU driver & SmmCpuFeaturesLib to do SmBase initialization:
> >
> > Who produces that HOB?  I see only consumers in this patch series.
> >
> > The patch series doesn't even pass BaseTools/Scripts/PatchCheck.py,
> > it will surely not pass CI.
> >
> > > With SMM Base Hob, SMM CPU driver does not need the RSM instruction
> > > to reload the SMBASE register with the new allocated value in SMBASE
> > > field each time it exits SMM. SMBASE Register for each processors
> > > have already been programmed in parallel since the same default
> > > SMBASE Address(0x30000) is not used, thus the CPUs over-writing
> > > each other's SMM Save State Area will not happen.
> >
> > Care to explain how this works?  SMBASE setup has to happen somewhere
> > (probably in the HOB producer), how does that work without using the
> > default smbase address?
> >
> > take care,
> >   Gerd



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Thanks Comments Gerd, I will resolve the CI check issue (I have noticed that in https://github.com/tianocore/edk2/pull/3884) & refine the usage description in next version.

Anyway, Ray also helped explain the usage as below, I will integrate it in the hob definition .h file, help below can help understand the design.:

The default SMBASE for the x86 processor is 0x30000. When SMI happens, CPU runs the
SMI handler at SMBASE+0x8000. Also, the SMM save state area is within SMBASE+0x10000.

One of the SMM initialization from CPU perspective is to program the new SMBASE (in TSEG range)
for each CPU thread. When the SMBASE update happens in a PEI module, the PEI module shall
produce the SMM_BASE_HOB in HOB database which tells the PiSmmCpuDxeSmm driver which runs
at a later phase about the new SMBASE for each CPU thread. PiSmmCpuDxeSmm driver installs
the SMI handler at the SMM_BASE_HOB.SmBase[Index]+0x8000 for CPU thread Index.
When the HOB doesn't exist, PiSmmCpuDxeSmm driver shall program the new SMBASE itself.

I also explain the in the patch 2 for PiSmmCpuDxeSmm changes:

SMM CPU driver will retrieve the SMBASE addresses from SMM Base Hob
and installs the SMI handler at [SMBASE+8000h] for each processor
instead of relocating SMM Base addresses from SMRAM again.

With SMM Base Hob, SMM CPU driver does not need the RSM instruction
to reload the SMBASE register with the new allocated value in SMBASE
field each time it exits SMM. SMBASE Register for each processors
have already been programmed in parallel since the same default
SMBASE Address(0x30000) is not used, thus the CPUs over-writing
each other's SMM Save State Area will not happen. This way will save
boot time on multi-core system

  
thanks,
Jiaxin 


> -----Original Message-----
> From: Gerd Hoffmann <kraxel@redhat.com>
> Sent: Friday, January 13, 2023 5:50 PM
> To: devel@edk2.groups.io; Wu, Jiaxin <jiaxin.wu@intel.com>
> Subject: Re: [edk2-devel] [PATCH v1 0/4] Support SMM Relocated SmBase
> handling
> 
> On Fri, Jan 13, 2023 at 03:17:34PM +0800, Wu, Jiaxin wrote:
> > Below serial patches are to support the SMM Relocated SmBase handling.
> > To achieve, new hob interface is procuded, and will be consumed by SMM
> > CPU driver & SmmCpuFeaturesLib to do SmBase initialization:
> 
> Who produces that HOB?  I see only consumers in this patch series.
> 
> The patch series doesn't even pass BaseTools/Scripts/PatchCheck.py,
> it will surely not pass CI.
> 
> > With SMM Base Hob, SMM CPU driver does not need the RSM instruction
> > to reload the SMBASE register with the new allocated value in SMBASE
> > field each time it exits SMM. SMBASE Register for each processors
> > have already been programmed in parallel since the same default
> > SMBASE Address(0x30000) is not used, thus the CPUs over-writing
> > each other's SMM Save State Area will not happen.
> 
> Care to explain how this works?  SMBASE setup has to happen somewhere
> (probably in the HOB producer), how does that work without using the
> default smbase address?
> 
> take care,
>   Gerd



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On Fri, Jan 13, 2023 at 10:18:59AM +0000, Wu, Jiaxin wrote:
> Thanks Comments Gerd, I will resolve the CI check issue (I have noticed that in https://github.com/tianocore/edk2/pull/3884) & refine the usage description in next version.
> 
> Anyway, Ray also helped explain the usage as below, I will integrate it in the hob definition .h file, help below can help understand the design.:
> 
> The default SMBASE for the x86 processor is 0x30000. When SMI happens, CPU runs the
> SMI handler at SMBASE+0x8000. Also, the SMM save state area is within SMBASE+0x10000.
> 
> One of the SMM initialization from CPU perspective is to program the new SMBASE (in TSEG range)
> for each CPU thread. When the SMBASE update happens in a PEI module, the PEI module shall
> produce the SMM_BASE_HOB in HOB database which tells the PiSmmCpuDxeSmm driver which runs
> at a later phase about the new SMBASE for each CPU thread.

There are no PEI module changes in this patch series.

So where does the HOB come from?

And what are the reasons for setting SMBASE in a PEI module instead
of PiSmmCpuDxeSmm?

take care,
  Gerd



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> 
> There are no PEI module changes in this patch series.
> 
> So where does the HOB come from?
> 

Who use, who produce. Here, just provide the interface capability.   

> And what are the reasons for setting SMBASE in a PEI module instead
> of PiSmmCpuDxeSmm?
> 

Do the smbase relocated ahead of SMM cpu driver can bring the benefit as I explain in the patch 2:

PiSmmCpuDxeSmm will retrieve the SMBASE addresses from SMM Base Hob
and installs the SMI handler at [SMBASE+8000h] for each processor
instead of relocating SMM Base addresses from SMRAM again.

With SMM Base Hob, PiSmmCpuDxeSmm does not need the RSM
instruction to reload the SMBASE register with the new allocated
SMBASE each time when it exits SMM. SMBASE Register for each
processors have already been programmed and all SMBASE address
have recorded in SMM Base Hob. So the same default SMBASE Address
(0x30000) will not be used, thus the CPUs over-writing
each other's SMM Save State Area will not happen. This way makes
the first SMI init can be executed in parallel and save boot
time on multi-core system.


> take care,
>   Gerd



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On Fri, Jan 13, 2023 at 12:47:54PM +0000, Wu, Jiaxin wrote:
> > 
> > There are no PEI module changes in this patch series.
> > 
> > So where does the HOB come from?
> 
> Who use, who produce. Here, just provide the interface capability.   

Well, yes.  This series adds the interface (i.e. the HOB guid
and struct).  It also updates some modules which consume that
new interface.

It does *not* add a producer of that new interface.

> > And what are the reasons for setting SMBASE in a PEI module instead
> > of PiSmmCpuDxeSmm?
> 
> Do the smbase relocated ahead of SMM cpu driver can bring the benefit
> as I explain in the patch 2:

> PiSmmCpuDxeSmm will retrieve the SMBASE addresses from SMM Base Hob
> and installs the SMI handler at [SMBASE+8000h] for each processor
> instead of relocating SMM Base addresses from SMRAM again.

That doesn't answer my question.

Sure, if you do the SMM Base relocation somewhere else PiSmmCpuDxeSmm
shouldn't do it again.

It is not clear why you do the SMM Base relocation somewhere else.
The code for that is also not present in this patch series.

take care,
  Gerd



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