From nobody Tue May 21 11:57:49 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+98447+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+98447+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1673594267; cv=none; d=zohomail.com; s=zohoarc; b=W88I91wkzos6lChymbjF4VWulTK7j7iKnARxoUZzoqG7tPqXRLkIWobhewwfUKZN9K5jOfJ6+oDdxRMT5hLf9YwXn6vXySVh6deMIx9gBFzXO/Kxs2toIsL75MfX/gRu9lhuEXWxMuBI5aZpgz1CkkaumVOqn2+vJAtg/iGhFYw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1673594267; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To; bh=MoPz/FI/aNt9ohjL6aCpbGvrw9sNIFNeDh1HGmQWTyM=; b=mOqDBNYDrYXYzAIPqKfUQJxDMZFfthtVS6q9Md6go6QaGH1+wM7SG/kABmN8ADA4MVVvFc+N1qRC07ejfL4ObYYpeb4ILK6pFQwQ1O1+QqUi8qdAJUipy8m/9o7vd2fJYzjnpX76QFBuR54C4Ptv/6oOi627GluzoCXIEKpQLI8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+98447+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1673594267293205.86651221418083; Thu, 12 Jan 2023 23:17:47 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id yxkuYY1788612xDM3gQdkyn4; Thu, 12 Jan 2023 23:17:46 -0800 X-Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by mx.groups.io with SMTP id smtpd.web11.80768.1673594263982383415 for ; Thu, 12 Jan 2023 23:17:46 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10588"; a="410169722" X-IronPort-AV: E=Sophos;i="5.97,213,1669104000"; d="scan'208";a="410169722" X-Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Jan 2023 23:17:46 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10588"; a="688646177" X-IronPort-AV: E=Sophos;i="5.97,213,1669104000"; d="scan'208";a="688646177" X-Received: from sh1gapp1009.ccr.corp.intel.com ([10.239.189.79]) by orsmga008.jf.intel.com with ESMTP; 12 Jan 2023 23:17:43 -0800 From: "Wu, Jiaxin" To: devel@edk2.groups.io Cc: Eric Dong , Ray Ni , Zeng Star , Laszlo Ersek , Gerd Hoffmann , Rahul Kumar Subject: [edk2-devel] [PATCH v1 1/4] UefiCpuPkg/SmmBaseHob.h: Add SMM Base HOB Data Date: Fri, 13 Jan 2023 15:17:35 +0800 Message-Id: <20230113071738.15868-2-jiaxin.wu@intel.com> In-Reply-To: <20230113071738.15868-1-jiaxin.wu@intel.com> References: <20230113071738.15868-1-jiaxin.wu@intel.com> Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,jiaxin.wu@intel.com X-Gm-Message-State: vXjgPgPRIi7BuILMg7NmAQEdx1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1673594266; bh=nZ+UqsNISaE5+uXztjhNltkPO9HUVcObkoqxb4ZXGWM=; h=Cc:Date:From:Reply-To:Subject:To; b=macgnWMp9xi4y8f3WkwGmUufWzPodeL4tkHf3pS+QScrwdkdb+gEFhWmOSxV8QACLDw QnAAzgsoqSscvu/PvH9YvvCnSi22Ls1BX+gYzwP5B29mB367e+r1lMNSotzYSOfZaRe7u ZgDv3IKVoRYJGEl0+iBYvo22I5IFzKerjBI= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1673594268241100010 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The Smm Base HOB is used to store the relocated SmBase in array for each Processors. If gSmmBaseHobGuid produced, indicate SmBase for each Processors have been relocated. The SmBase address in hob can be guaranteed the SMRAM state save areas for all processors do not overlap. Cc: Eric Dong Cc: Ray Ni Cc: Zeng Star Cc: Laszlo Ersek Cc: Gerd Hoffmann Cc: Rahul Kumar Signed-off-by: Jiaxin Wu --- UefiCpuPkg/Include/Guid/SmmBaseHob.h | 51 ++++++++++++++++++++++++++++++++= ++++ UefiCpuPkg/UefiCpuPkg.dec | 3 +++ 2 files changed, 54 insertions(+) create mode 100644 UefiCpuPkg/Include/Guid/SmmBaseHob.h diff --git a/UefiCpuPkg/Include/Guid/SmmBaseHob.h b/UefiCpuPkg/Include/Guid= /SmmBaseHob.h new file mode 100644 index 0000000000..090b22a274 --- /dev/null +++ b/UefiCpuPkg/Include/Guid/SmmBaseHob.h @@ -0,0 +1,51 @@ +/** @file + The Smm Base HOB is used to store the information of: + * The relocated SmBase in array for each Processors. + + If gSmmBaseHobGuid produced, indicate SmBase for each Processors + have been relocated and SmBase in HOB can be guaranteed the SMRAM + state save areas for all processors do not overlap. SMM CPU driver + should retrieve the SMBASE addresses from this HOB and installs the + SMI handler at [SMBASE+8000h] for each processor instead of relocating + SMM Base addresses from SMRAM again. + + With SMM Base Hob, SMM CPU driver doesn't need the RSM instruction + to reload the SMBASE register with the new allocated value in SMBASE + field each time it exits SMM. SMBASE Register for each processors + have already been programmed in parallel since the same default + SMBASE Address (0x30000) is not used, thus the CPUs over-writing + each other's SMM Save State Area will not happen. This way will save + boot time on multi-core system. + + Copyright (c) 2023, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef SMM_BASE_HOB_H_ +#define SMM_BASE_HOB_H_ + +#include +#include + +#define SMM_BASE_HOB_DATA_GUID \ + { \ + 0xc2217ba7, 0x03bb, 0x4f63, {0xa6, 0x47, 0x7c, 0x25, 0xc5, 0xfc, 0x9d,= 0x73} \ + } + +#pragma pack(1) +typedef struct { + /// + /// Describes the Number of all max supported processors. + /// + UINT64 NumberOfProcessors; + /// + /// Pointer to SmBase address for each Processors. + /// + UINT64 SmBase[]; +} SMM_BASE_HOB_DATA; +#pragma pack() + +extern EFI_GUID gSmmBaseHobGuid; + +#endif diff --git a/UefiCpuPkg/UefiCpuPkg.dec b/UefiCpuPkg/UefiCpuPkg.dec index cff239d528..2afd08cdd2 100644 --- a/UefiCpuPkg/UefiCpuPkg.dec +++ b/UefiCpuPkg/UefiCpuPkg.dec @@ -76,10 +76,13 @@ gEdkiiCpuFeaturesInitDoneGuid =3D { 0xc77c3a41, 0x61ab, 0x4143, { 0x98,= 0x3e, 0x33, 0x39, 0x28, 0x6, 0x28, 0xe5 }} =20 ## Include/Guid/MicrocodePatchHob.h gEdkiiMicrocodePatchHobGuid =3D { 0xd178f11d, 0x8716, 0x418e, { 0xa1,= 0x31, 0x96, 0x7d, 0x2a, 0xc4, 0x28, 0x43 }} =20 + ## Include/Guid/SmmBaseHob.h + gSmmBaseHobGuid =3D { 0xc2217ba7, 0x03bb, 0x4f63, {0xa6, 0x47, 0x7c= , 0x25, 0xc5, 0xfc, 0x9d, 0x73 }} + [Protocols] ## Include/Protocol/SmmCpuService.h gEfiSmmCpuServiceProtocolGuid =3D { 0x1d202cab, 0xc8ab, 0x4d5c, { 0x94= , 0xf7, 0x3c, 0xfc, 0xc0, 0xd3, 0xd3, 0x35 }} gEdkiiSmmCpuRendezvousProtocolGuid =3D { 0xaa00d50b, 0x4911, 0x428f, { 0= xb9, 0x1a, 0xa5, 0x9d, 0xdb, 0x13, 0xe2, 0x4c }} =20 --=20 2.16.2.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#98447): https://edk2.groups.io/g/devel/message/98447 Mute This Topic: https://groups.io/mt/96241701/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Tue May 21 11:57:49 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+98448+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+98448+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1673594269; cv=none; d=zohomail.com; s=zohoarc; b=jzq1ZCctQgJsSQohiiioytZ0WNkZO3od9bi8f/WJjFRHORoW2j3HqWrUzKf1hUCx/brRAupDG1bnaVhpsnJsVYT+/oCvw3/TJwshHmxsgQVn0ieCfs3Nqmj+Iy5F19yWvNtJEdjw2BD+yzR9DyNRsPI9Cq9jg5XD63ri/vDdVUY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1673594269; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To; bh=G5dua569G7u1s7bWTBQswT/FAp6WC+tgbG09n+vs6m0=; b=OHpWohPAcMoGakKYEKSI86bgY8Oojt9XR61K3zKEpOsMBUx6sqnvEBkPkc5ukAQqcI8dgHgO3e3GuVmvPsgOkTdrIjg6Dnh/+UsaL0o55clVZn22fmi+YtHkcPuN5Bi5/uUZxp9kBrcpElfpOozNGKyPUS39n9m7kjS+nsw4+dY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+98448+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 167359426917589.5727941895858; Thu, 12 Jan 2023 23:17:49 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id gSRcYY1788612xnWVtwGKOel; Thu, 12 Jan 2023 23:17:48 -0800 X-Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by mx.groups.io with SMTP id smtpd.web11.80768.1673594263982383415 for ; Thu, 12 Jan 2023 23:17:48 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10588"; a="410169748" X-IronPort-AV: E=Sophos;i="5.97,213,1669104000"; d="scan'208";a="410169748" X-Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Jan 2023 23:17:47 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10588"; a="688646193" X-IronPort-AV: E=Sophos;i="5.97,213,1669104000"; d="scan'208";a="688646193" X-Received: from sh1gapp1009.ccr.corp.intel.com ([10.239.189.79]) by orsmga008.jf.intel.com with ESMTP; 12 Jan 2023 23:17:45 -0800 From: "Wu, Jiaxin" To: devel@edk2.groups.io Cc: Eric Dong , Ray Ni , Zeng Star , Laszlo Ersek , Gerd Hoffmann , Rahul Kumar Subject: [edk2-devel] [PATCH v1 2/4] UefiCpuPkg/PiSmmCpuDxeSmm: Consume SMM Base Hob for SmBase info Date: Fri, 13 Jan 2023 15:17:36 +0800 Message-Id: <20230113071738.15868-3-jiaxin.wu@intel.com> In-Reply-To: <20230113071738.15868-1-jiaxin.wu@intel.com> References: <20230113071738.15868-1-jiaxin.wu@intel.com> Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,jiaxin.wu@intel.com X-Gm-Message-State: xVU3fVoOBGpBO1C94k9NujQix1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1673594268; bh=/uG4v8oOl+hr3KVLWfLnyxQFWsPFXISEoOHdGjq5kXg=; h=Cc:Date:From:Reply-To:Subject:To; b=vhfMGrltlxGNNaLqrrtkxAXmByldtoPpzx5L0MSgSkN1nEcvmFwQBA2DZAGc2OTCjwE 9x8CAUtaFe5JmVzfBjsjkDq9e8d4nv5uOuGXvPC+lLP33wlyxbJnW+Rk+GaRp+dt8RzIF yef2ePr4VAVyx1O578yvfv4xBeRVC17FQtE= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1673594270214100014 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" SMM CPU driver will retrieve the SMBASE addresses from SMM Base Hob and installs the SMI handler at [SMBASE+8000h] for each processor instead of relocating SMM Base addresses from SMRAM again. With SMM Base Hob, SMM CPU driver does not need the RSM instruction to reload the SMBASE register with the new allocated value in SMBASE field each time it exits SMM. SMBASE Register for each processors have already been programmed in parallel since the same default SMBASE Address(0x30000) is not used, thus the CPUs over-writing each other's SMM Save State Area will not happen. This way will save boot time on multi-core system. Mainly changes as below: *Combine 2 SMIs (gcSmmInitTemplate & gcSmiHandlerTemplate) into one (gcSmiHandlerTemplate), the new SMI handler needs to run to 2 paths: one to SmmCpuFeaturesInitializeProcessor(), the other to SMM Core Entry Point. *Issue SMI IPI (All Excluding Self SMM IPI + BSP SMM IPI) for SMM init before normal SMI sources happen. *Call SmmCpuFeaturesInitializeProcessor() in parallel. Cc: Eric Dong Cc: Ray Ni Cc: Zeng Star Cc: Laszlo Ersek Cc: Gerd Hoffmann Cc: Rahul Kumar Signed-off-by: Jiaxin Wu --- UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c | 40 ++++++- UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c | 25 ++++- UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c | 155 ++++++++++++++++++++---= ---- UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h | 21 +++- UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf | 1 + 5 files changed, 197 insertions(+), 45 deletions(-) diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c b/UefiCpuPkg/PiSmmCpuDxeSmm/= CpuS3.c index fb4a44eab6..f7479fc74d 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c @@ -765,10 +765,11 @@ SmmRestoreCpu ( SMM_S3_RESUME_STATE *SmmS3ResumeState; IA32_DESCRIPTOR Ia32Idtr; IA32_DESCRIPTOR X64Idtr; IA32_IDT_GATE_DESCRIPTOR IdtEntryTable[EXCEPTION_VECTOR_NUMBER]; EFI_STATUS Status; + UINTN Index; =20 DEBUG ((DEBUG_INFO, "SmmRestoreCpu()\n")); =20 mSmmS3Flag =3D TRUE; =20 @@ -822,13 +823,48 @@ SmmRestoreCpu ( // InitializeCpuBeforeRebase (); } =20 // - // Restore SMBASE for BSP and all APs + // Retrive the allocated SmmBase from gSmmBaseHobGuid. If found, + // means the SmBase relocation has been done. + // + if (GetFirstGuidHob (&gSmmBaseHobGuid) !=3D NULL) { + mSmBaseRelocationDone =3D TRUE; + } else { + mSmBaseRelocationDone =3D FALSE; + } + + // + // Check whether Smm Relocation is done or not. + // If not, will do the SmmBases Relocation here!!! // - SmmRelocateBases (); + if (!mSmBaseRelocationDone) { + // + // Restore SMBASE for BSP and all APs + // + SmmRelocateBases (); + } else { + mSmmInitialized =3D (BOOLEAN *)AllocateZeroPool (sizeof (BOOLEAN) * mM= axNumberOfCpus); + ASSERT (mSmmInitialized !=3D NULL); + + mBspApicId =3D GetApicId (); + + // + // Issue SMI IPI (All Excluding Self SMM IPI + BSP SMM IPI) for SMM in= it + // + SendSmiIpi (mBspApicId); + SendSmiIpiAllExcludingSelf (); + + // + // Wait for all processors to finish its 1st SMI + // + for (Index =3D 0; Index < mNumberOfCpus; Index++) { + while (mSmmInitialized[Index] =3D=3D FALSE) { + } + } + } =20 // // Skip initialization if mAcpiCpuData is not valid // if (mAcpiCpuData.NumberOfCpus > 0) { diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c b/UefiCpuPkg/PiSmmCpuDxe= Smm/MpService.c index a0967eb69c..b4339eef48 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c @@ -1728,10 +1728,29 @@ SmiRendezvous ( // when using on-demand paging for above 4G memory. // Cr2 =3D 0; SaveCr2 (&Cr2); =20 + if (mSmBaseRelocationDone && !mSmmInitialized[CpuIndex]) { + // + // Perform SmmInitHandler for CpuIndex + // + SmmInitHandler (); + + // + // Restore Cr2 + // + RestoreCr2 (Cr2); + + // + // Mark the first SMI init for CpuIndex has been done so as to avoid t= he reentry. + // + mSmmInitialized[CpuIndex] =3D TRUE; + + return; + } + // // Call the user register Startup function first. // if (mSmmMpSyncData->StartupProcedure !=3D NULL) { mSmmMpSyncData->StartupProcedure (mSmmMpSyncData->StartupProcArgs); @@ -1882,13 +1901,13 @@ Exit: // RestoreCr2 (Cr2); } =20 /** - Initialize PackageBsp Info. Processor specified by mPackageFirstThreadIn= dex[PackageIndex] - will do the package-scope register programming. Set default CpuIndex to = (UINT32)-1, which - means not specified yet. + Initialize mPackageFirstThreadIndex Info. Processor specified by mPackag= eFirstThreadIndex[PackageIndex] + will do the package-scope register programming. Set default CpuIndex to = (UINT32)-1, which means not + specified yet. =20 **/ VOID InitPackageFirstThreadIndexInfo ( VOID diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c b/UefiCpuPkg/PiSmmC= puDxeSmm/PiSmmCpuDxeSmm.c index 655175a2c6..aa1700ba58 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c @@ -83,10 +83,14 @@ EDKII_SMM_MEMORY_ATTRIBUTE_PROTOCOL mSmmMemoryAttribut= e =3D { EdkiiSmmClearMemoryAttributes }; =20 EFI_CPU_INTERRUPT_HANDLER mExternalVectorTable[EXCEPTION_VECTOR_NUMBER]; =20 +BOOLEAN mSmBaseRelocationDone =3D FALSE; +BOOLEAN *mSmmInitialized =3D NULL; +UINT32 mBspApicId =3D 0; + // // SMM stack information // UINTN mSmmStackArrayBase; UINTN mSmmStackArrayEnd; @@ -341,29 +345,38 @@ VOID EFIAPI SmmInitHandler ( VOID ) { - UINT32 ApicId; - UINTN Index; + UINT32 ApicId; + UINTN Index; + BOOLEAN IsMonarch; + + IsMonarch =3D FALSE; =20 // // Update SMM IDT entries' code segment and load IDT // AsmWriteIdtr (&gcSmiIdtr); ApicId =3D GetApicId (); =20 ASSERT (mNumberOfCpus <=3D mMaxNumberOfCpus); =20 + if (!mSmBaseRelocationDone) { + IsMonarch =3D mIsBsp; + } else if (mBspApicId =3D=3D ApicId) { + IsMonarch =3D TRUE; + } + for (Index =3D 0; Index < mNumberOfCpus; Index++) { if (ApicId =3D=3D (UINT32)gSmmCpuPrivate->ProcessorInfo[Index].Process= orId) { // // Initialize SMM specific features on the currently executing CPU // SmmCpuFeaturesInitializeProcessor ( Index, - mIsBsp, + IsMonarch, gSmmCpuPrivate->ProcessorInfo, &mCpuHotPlugData ); =20 if (!mSmmS3Flag) { @@ -371,23 +384,25 @@ SmmInitHandler ( // Check XD and BTS features on each processor on normal boot // CheckFeatureSupported (); } =20 - if (mIsBsp) { + if (!mSmBaseRelocationDone) { + if (mIsBsp) { + // + // BSP rebase is already done above. + // Initialize private data during S3 resume + // + InitializeMpSyncData (); + } + // - // BSP rebase is already done above. - // Initialize private data during S3 resume + // Hook return after RSM to set SMM re-based flag // - InitializeMpSyncData (); + SemaphoreHook (Index, &mRebased[Index]); } =20 - // - // Hook return after RSM to set SMM re-based flag - // - SemaphoreHook (Index, &mRebased[Index]); - return; } } =20 ASSERT (FALSE); @@ -561,10 +576,15 @@ PiCpuSmmEntry ( UINT32 RegEcx; UINT32 RegEdx; UINTN FamilyId; UINTN ModelId; UINT32 Cr3; + EFI_HOB_GUID_TYPE *GuidHob; + SMM_BASE_HOB_DATA *SmmBaseHobData; + + GuidHob =3D NULL; + SmmBaseHobData =3D NULL; =20 // // Initialize address fixup // PiSmmCpuSmmInitFixupAddress (); @@ -789,30 +809,52 @@ PiCpuSmmEntry ( // context must be reduced. // ASSERT (TileSize <=3D (SMRAM_SAVE_STATE_MAP_OFFSET + sizeof (SMRAM_SAVE_= STATE_MAP) - SMM_HANDLER_OFFSET)); =20 // - // Allocate buffer for all of the tiles. + // Check whether the Required TileSize is enough. // - // Intel(R) 64 and IA-32 Architectures Software Developer's Manual - // Volume 3C, Section 34.11 SMBASE Relocation - // For Pentium and Intel486 processors, the SMBASE values must be - // aligned on a 32-KByte boundary or the processor will enter shutdown - // state during the execution of a RSM instruction. + if (TileSize > SIZE_8KB) { + DEBUG ((DEBUG_ERROR, "The Range of Smbase in SMRAM is not enough -- Re= quired TileSize =3D 0x%08x, Actual TileSize =3D 0x%08x\n", TileSize, SIZE_8= KB)); + ASSERT (TileSize <=3D SIZE_8KB); + return RETURN_BUFFER_TOO_SMALL; + } + // - // Intel486 processors: FamilyId is 4 - // Pentium processors : FamilyId is 5 + // Retrive the allocated SmmBase from gSmmBaseHobGuid. If found, + // means the SmBase relocation has been done. // - BufferPages =3D EFI_SIZE_TO_PAGES (SIZE_32KB + TileSize * (mMaxNumberOfC= pus - 1)); - if ((FamilyId =3D=3D 4) || (FamilyId =3D=3D 5)) { - Buffer =3D AllocateAlignedCodePages (BufferPages, SIZE_32KB); + GuidHob =3D GetFirstGuidHob (&gSmmBaseHobGuid); + if (GuidHob !=3D NULL) { + SmmBaseHobData =3D GET_GUID_HOB_DATA (GuidHob); + + ASSERT (SmmBaseHobData->NumberOfProcessors =3D=3D mMaxNumberOfCpus); + mSmBaseRelocationDone =3D TRUE; } else { - Buffer =3D AllocateAlignedCodePages (BufferPages, SIZE_4KB); - } + DEBUG ((DEBUG_INFO, "PiCpuSmmEntry: gSmmBaseHobGuid not found!\n")); + // + // Allocate buffer for all of the tiles. + // + // Intel(R) 64 and IA-32 Architectures Software Developer's Manual + // Volume 3C, Section 34.11 SMBASE Relocation + // For Pentium and Intel486 processors, the SMBASE values must be + // aligned on a 32-KByte boundary or the processor will enter shutdo= wn + // state during the execution of a RSM instruction. + // + // Intel486 processors: FamilyId is 4 + // Pentium processors : FamilyId is 5 + // + BufferPages =3D EFI_SIZE_TO_PAGES (SIZE_32KB + TileSize * (mMaxNumberO= fCpus - 1)); + if ((FamilyId =3D=3D 4) || (FamilyId =3D=3D 5)) { + Buffer =3D AllocateAlignedCodePages (BufferPages, SIZE_32KB); + } else { + Buffer =3D AllocateAlignedCodePages (BufferPages, SIZE_4KB); + } =20 - ASSERT (Buffer !=3D NULL); - DEBUG ((DEBUG_INFO, "SMRAM SaveState Buffer (0x%08x, 0x%08x)\n", Buffer,= EFI_PAGES_TO_SIZE (BufferPages))); + ASSERT (Buffer !=3D NULL); + DEBUG ((DEBUG_INFO, "New Allcoated SMRAM SaveState Buffer (0x%08x, 0x%= 08x)\n", Buffer, EFI_PAGES_TO_SIZE (BufferPages))); + } =20 // // Allocate buffer for pointers to array in SMM_CPU_PRIVATE_DATA. // gSmmCpuPrivate->ProcessorInfo =3D (EFI_PROCESSOR_INFORMATION *)AllocateP= ool (sizeof (EFI_PROCESSOR_INFORMATION) * mMaxNumberOfCpus); @@ -843,11 +885,12 @@ PiCpuSmmEntry ( // Retrieve APIC ID of each enabled processor from the MP Services proto= col. // Also compute the SMBASE address, CPU Save State address, and CPU Save= state // size for each CPU in the platform // for (Index =3D 0; Index < mMaxNumberOfCpus; Index++) { - mCpuHotPlugData.SmBase[Index] =3D (UINTN)Buffer + Index * Ti= leSize - SMM_HANDLER_OFFSET; + mCpuHotPlugData.SmBase[Index] =3D mSmBaseRelocationDone ? (UINTN)SmmBa= seHobData->SmBase[Index] : (UINTN)Buffer + Index * TileSize - SMM_HANDLER_O= FFSET; + gSmmCpuPrivate->CpuSaveStateSize[Index] =3D sizeof (SMRAM_SAVE_STATE_M= AP); gSmmCpuPrivate->CpuSaveState[Index] =3D (VOID *)(mCpuHotPlugData.S= mBase[Index] + SMRAM_SAVE_STATE_MAP_OFFSET); gSmmCpuPrivate->Operation[Index] =3D SmmCpuNone; =20 if (Index < mNumberOfCpus) { @@ -956,21 +999,27 @@ PiCpuSmmEntry ( // Initialize IDT // InitializeSmmIdt (); =20 // - // Relocate SMM Base addresses to the ones allocated from SMRAM + // Check whether Smm Relocation is done or not. + // If not, will do the SmmBases Relocation here!!! // - mRebased =3D (BOOLEAN *)AllocateZeroPool (sizeof (BOOLEAN) * mMaxNumberO= fCpus); - ASSERT (mRebased !=3D NULL); - SmmRelocateBases (); + if (!mSmBaseRelocationDone) { + // + // Relocate SMM Base addresses to the ones allocated from SMRAM + // + mRebased =3D (BOOLEAN *)AllocateZeroPool (sizeof (BOOLEAN) * mMaxNumbe= rOfCpus); + ASSERT (mRebased !=3D NULL); + SmmRelocateBases (); =20 - // - // Call hook for BSP to perform extra actions in normal mode after all - // SMM base addresses have been relocated on all CPUs - // - SmmCpuFeaturesSmmRelocationComplete (); + // + // Call hook for BSP to perform extra actions in normal mode after all + // SMM base addresses have been relocated on all CPUs + // + SmmCpuFeaturesSmmRelocationComplete (); + } =20 DEBUG ((DEBUG_INFO, "mXdSupported - 0x%x\n", mXdSupported)); =20 // // SMM Time initialization @@ -997,10 +1046,42 @@ PiCpuSmmEntry ( ); } } } =20 + // + // For relocated SMBASE, some MSRs & CSRs are still required to be confi= gured in SMM Mode for SMM Initialization. + // Those MSRs & CSRs must be configured before normal SMI sources happen. + // So, here is to issue SMI IPI (All Excluding Self SMM IPI + BSP SMM I= PI) for SMM init + // + if (mSmBaseRelocationDone) { + mSmmInitialized =3D (BOOLEAN *)AllocateZeroPool (sizeof (BOOLEAN) * mM= axNumberOfCpus); + ASSERT (mSmmInitialized !=3D NULL); + + mBspApicId =3D GetApicId (); + + // + // Issue SMI IPI (All Excluding Self SMM IPI + BSP SMM IPI) for SMM in= it + // + SendSmiIpi (mBspApicId); + SendSmiIpiAllExcludingSelf (); + + // + // Wait for all processors to finish its 1st SMI + // + for (Index =3D 0; Index < mNumberOfCpus; Index++) { + while (mSmmInitialized[Index] =3D=3D FALSE) { + } + } + + // + // Call hook for BSP to perform extra actions in normal mode after all + // SMM base addresses have been relocated on all CPUs + // + SmmCpuFeaturesSmmRelocationComplete (); + } + // // Fill in SMM Reserved Regions // gSmmCpuPrivate->SmmReservedSmramRegion[0].SmramReservedStart =3D 0; gSmmCpuPrivate->SmmReservedSmramRegion[0].SmramReservedSize =3D 0; diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h b/UefiCpuPkg/PiSmmC= puDxeSmm/PiSmmCpuDxeSmm.h index 5f0a38e400..da6804c58b 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h @@ -23,10 +23,11 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include =20 #include #include #include +#include =20 #include #include #include #include @@ -346,10 +347,20 @@ SmmWriteSaveState ( IN EFI_SMM_SAVE_STATE_REGISTER Register, IN UINTN CpuIndex, IN CONST VOID *Buffer ); =20 +/** + C function for SMI handler. To change all processor's SMMBase Register. + +**/ +VOID +EFIAPI +SmmInitHandler ( + VOID + ); + /** Read a CPU Save State register on the target processor. =20 This function abstracts the differences that whether the CPU Save State re= gister is in the IA32 CPU Save State Map or X64 CPU Save State Map. @@ -400,10 +411,14 @@ WriteSaveStateRegister ( IN EFI_SMM_SAVE_STATE_REGISTER Register, IN UINTN Width, IN CONST VOID *Buffer ); =20 +extern BOOLEAN mSmBaseRelocationDone; +extern BOOLEAN *mSmmInitialized; +extern UINT32 mBspApicId; + extern CONST UINT8 gcSmmInitTemplate[]; extern CONST UINT16 gcSmmInitSize; X86_ASSEMBLY_PATCH_LABEL gPatchSmmCr0; extern UINT32 mSmmCr0; X86_ASSEMBLY_PATCH_LABEL gPatchSmmCr3; @@ -1486,13 +1501,13 @@ RegisterStartupProcedure ( IN EFI_AP_PROCEDURE Procedure, IN OUT VOID *ProcedureArguments OPTIONAL ); =20 /** - Initialize PackageBsp Info. Processor specified by mPackageFirstThreadIn= dex[PackageIndex] - will do the package-scope register programming. Set default CpuIndex to = (UINT32)-1, which - means not specified yet. + Initialize mPackageFirstThreadIndex Info. Processor specified by mPackag= eFirstThreadIndex[PackageIndex] + will do the package-scope register programming. Set default CpuIndex to = (UINT32)-1, which means not + specified yet. =20 **/ VOID InitPackageFirstThreadIndexInfo ( VOID diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf b/UefiCpuPkg/PiSm= mCpuDxeSmm/PiSmmCpuDxeSmm.inf index b4b327f60c..6dbed17b96 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf @@ -112,10 +112,11 @@ =20 [Guids] gEfiAcpiVariableGuid ## SOMETIMES_CONSUMES ## HOB # = it is used for S3 boot. gEdkiiPiSmmMemoryAttributesTableGuid ## CONSUMES ## SystemTable gEfiMemoryAttributesTableGuid ## CONSUMES ## SystemTable + gSmmBaseHobGuid ## CONSUMES =20 [FeaturePcd] gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmDebug ## CONS= UMES gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmBlockStartupThisAp ## CONS= UMES gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmEnableBspElection ## CONS= UMES --=20 2.16.2.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#98448): https://edk2.groups.io/g/devel/message/98448 Mute This Topic: https://groups.io/mt/96241702/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Tue May 21 11:57:49 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+98449+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+98449+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1673594271; cv=none; d=zohomail.com; s=zohoarc; b=VMXJSMPkxFqyaz+8LX1TKyk5JP4Qb9Yat/S5Vb1nmzJ3H8mUrmTdgl0TH50oA9Kz7Fwwz6rP1piJFiHbr/QrRsTBXQV0Zvofn1lkWtOWpyCMEyI8Xccldwl4ueWsrZShCbms92I5+6P9sms6t5ro3CKWPChiDS4t+VhcR0evWrE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1673594271; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To; bh=2KgjLFIxMw+5iFMu15agUy3cLTpeALiCo6VRDCNvlWQ=; b=bHpqo4Q5GiMTQEe8pfrCo9UBPHORYx39+AD5tCZwGjXOCwMXvWqwc7RkYfak01pA7gpYfCGzNCrwTVYTHluI3SjVWBjsnowoVa8R3KOYKz8/SLqAl4/1ZNHSZOzudzX6bjm0lvfp8YD+fLrL7JsTcinoE76RGkx+2ZDhMGgYhwU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+98449+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1673594271506585.8725357882216; Thu, 12 Jan 2023 23:17:51 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id sLzzYY1788612xXF2MSIdSAK; Thu, 12 Jan 2023 23:17:51 -0800 X-Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by mx.groups.io with SMTP id smtpd.web11.80768.1673594263982383415 for ; Thu, 12 Jan 2023 23:17:50 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10588"; a="410169766" X-IronPort-AV: E=Sophos;i="5.97,213,1669104000"; d="scan'208";a="410169766" X-Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Jan 2023 23:17:50 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10588"; a="688646202" X-IronPort-AV: E=Sophos;i="5.97,213,1669104000"; d="scan'208";a="688646202" X-Received: from sh1gapp1009.ccr.corp.intel.com ([10.239.189.79]) by orsmga008.jf.intel.com with ESMTP; 12 Jan 2023 23:17:47 -0800 From: "Wu, Jiaxin" To: devel@edk2.groups.io Cc: Eric Dong , Ray Ni , Zeng Star , Laszlo Ersek , Gerd Hoffmann , Rahul Kumar Subject: [edk2-devel] [PATCH v1 3/4] UefiCpuPkg/SmmCpuFeaturesLib: Skip to configure SMBASE Date: Fri, 13 Jan 2023 15:17:37 +0800 Message-Id: <20230113071738.15868-4-jiaxin.wu@intel.com> In-Reply-To: <20230113071738.15868-1-jiaxin.wu@intel.com> References: <20230113071738.15868-1-jiaxin.wu@intel.com> Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,jiaxin.wu@intel.com X-Gm-Message-State: fWaNNofahgTYs2PzwaP77aE7x1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1673594271; bh=uD1pdtFxBtMoJ85Z6OQftVzIcQixaySSP2JvMSlriMw=; h=Cc:Date:From:Reply-To:Subject:To; b=TMYT7TfDR9SQweIH1+YrPfNkqvhgA1u4W526rvGOHbcvq7JDIdSb0lihyPHhY2ZyKuL Lnu4Fy/AAyHaqSTUOJEiIjGEPCrdSRN37oBdrp1FLBmkdpCt+Hm4TvhlRN4esLyaXCG5P AnMWs8IT0gDWZBPcpf1sIYlCcNI58auEv2A= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1673594272216100018 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This patch is to aviod configure SMBASE if SmBase relocation has been done. If gSmmBaseHobGuid found, means SmBase info has been relocated and recorded in the SmBase array. No need to do the relocation in SmmCpuFeaturesInitializeProcessor(). Cc: Eric Dong Cc: Ray Ni Cc: Zeng Star Cc: Laszlo Ersek Cc: Gerd Hoffmann Cc: Rahul Kumar Signed-off-by: Jiaxin Wu --- .../Library/SmmCpuFeaturesLib/CpuFeaturesLib.h | 2 ++ .../SmmCpuFeaturesLib/IntelSmmCpuFeaturesLib.c | 25 ++++++++++++++++++= +--- .../SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf | 4 ++++ .../SmmCpuFeaturesLib/SmmCpuFeaturesLibStm.inf | 1 + UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.c | 1 - .../StandaloneMmCpuFeaturesLib.inf | 4 ++++ 6 files changed, 33 insertions(+), 4 deletions(-) diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/CpuFeaturesLib.h b/UefiCp= uPkg/Library/SmmCpuFeaturesLib/CpuFeaturesLib.h index fd3e902547..c2e4fbe96b 100644 --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/CpuFeaturesLib.h +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/CpuFeaturesLib.h @@ -7,15 +7,17 @@ **/ =20 #ifndef CPU_FEATURES_LIB_H_ #define CPU_FEATURES_LIB_H_ =20 +#include #include #include #include #include #include +#include =20 /** Performs library initialization. =20 This initialization function contains common functionality shared betwen= all diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/IntelSmmCpuFeaturesLib.c = b/UefiCpuPkg/Library/SmmCpuFeaturesLib/IntelSmmCpuFeaturesLib.c index d5eaaa7a99..c82bf9ad37 100644 --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/IntelSmmCpuFeaturesLib.c +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/IntelSmmCpuFeaturesLib.c @@ -36,10 +36,16 @@ SPDX-License-Identifier: BSD-2-Clause-Patent // Set default value to assume IA-32 Architectural MSRs are used // UINT32 mSmrrPhysBaseMsr =3D SMM_FEATURES_LIB_IA32_SMRR_PHYSBASE; UINT32 mSmrrPhysMaskMsr =3D SMM_FEATURES_LIB_IA32_SMRR_PHYSMASK; =20 +// +// Indicate SmBase for each Processors has been relocated or not. If TRUE, +// means no need to do the relocation in SmmCpuFeaturesInitializeProcessor= (). +// +BOOLEAN mSmBaseRelocated; + // // Set default value to assume MTRRs need to be configured on each SMI // BOOLEAN mNeedConfigureMtrrs =3D TRUE; =20 @@ -142,10 +148,18 @@ CpuFeaturesLibInitialization ( // // Allocate array for state of SMRR enable on all CPUs // mSmrrEnabled =3D (BOOLEAN *)AllocatePool (sizeof (BOOLEAN) * GetCpuMaxLo= gicalProcessorNumber ()); ASSERT (mSmrrEnabled !=3D NULL); + + // + // If gSmmBaseHobGuid found, means SmBase info has been relocated and re= corded + // in the SmBase array. + // + if (GetFirstGuidHob (&gSmmBaseHobGuid) !=3D NULL) { + mSmBaseRelocated =3D TRUE; + } } =20 /** Called during the very first SMI into System Management Mode to initiali= ze CPU features, including SMBASE, for the currently executing CPU. Since = this @@ -185,14 +199,19 @@ SmmCpuFeaturesInitializeProcessor ( UINT32 RegEdx; UINTN FamilyId; UINTN ModelId; =20 // - // Configure SMBASE. + // No need to configure SMBASE if SmBase relocation has been done. // - CpuState =3D (SMRAM_SAVE_STATE_MAP *)(UINTN)(SMM_DEFAULT_SMB= ASE + SMRAM_SAVE_STATE_MAP_OFFSET); - CpuState->x86.SMBASE =3D (UINT32)CpuHotPlugData->SmBase[CpuIndex]; + if (!mSmBaseRelocated) { + // + // Configure SMBASE. + // + CpuState =3D (SMRAM_SAVE_STATE_MAP *)(UINTN)(SMM_DEFAULT_S= MBASE + SMRAM_SAVE_STATE_MAP_OFFSET); + CpuState->x86.SMBASE =3D (UINT32)CpuHotPlugData->SmBase[CpuIndex]; + } =20 // // Intel(R) 64 and IA-32 Architectures Software Developer's Manual // Volume 3C, Section 35.2 MSRs in the Intel(R) Core(TM) 2 Processor Fam= ily // diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf b/U= efiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf index 9ac7dde78f..280a4b8b39 100644 --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf @@ -31,10 +31,14 @@ [LibraryClasses] BaseLib PcdLib MemoryAllocationLib DebugLib + HobLib + +[Guids] + gSmmBaseHobGuid ## CONSUMES =20 [Pcd] gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber ## SOME= TIMES_CONSUMES =20 [FeaturePcd] diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLibStm.inf = b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLibStm.inf index 86d367e0a0..4bb045244b 100644 --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLibStm.inf +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLibStm.inf @@ -62,10 +62,11 @@ =20 [Guids] gMsegSmramGuid ## SOMETIMES_CONSUMES ## HOB gEfiAcpi20TableGuid ## SOMETIMES_CONSUMES ## System= Table gEfiAcpi10TableGuid ## SOMETIMES_CONSUMES ## System= Table + gSmmBaseHobGuid ## CONSUMES =20 [Pcd] gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber ## SOME= TIMES_CONSUMES gUefiCpuPkgTokenSpaceGuid.PcdCpuMsegSize ## SOME= TIMES_CONSUMES gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStmExceptionStackSize ## SOME= TIMES_CONSUMES diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.c b/UefiCpuPkg/Lib= rary/SmmCpuFeaturesLib/SmmStm.c index 3cf162ada0..455fe83991 100644 --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.c +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.c @@ -6,11 +6,10 @@ =20 **/ =20 #include #include -#include #include #include #include #include #include diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/StandaloneMmCpuFeaturesLi= b.inf b/UefiCpuPkg/Library/SmmCpuFeaturesLib/StandaloneMmCpuFeaturesLib.inf index b1f60a5505..63259e44e7 100644 --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/StandaloneMmCpuFeaturesLib.inf +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/StandaloneMmCpuFeaturesLib.inf @@ -32,10 +32,14 @@ [LibraryClasses] BaseLib DebugLib MemoryAllocationLib PcdLib + HobLib + +[Guids] + gSmmBaseHobGuid ## CONSUMES =20 [FixedPcd] gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber ## SOME= TIMES_CONSUMES =20 [FeaturePcd] --=20 2.16.2.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#98449): https://edk2.groups.io/g/devel/message/98449 Mute This Topic: https://groups.io/mt/96241703/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Tue May 21 11:57:49 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+98450+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+98450+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1673594273; cv=none; d=zohomail.com; s=zohoarc; b=mHvPeye33WqnaDK6rzD+qkE0myXSqxv5kyUB0OOBVvWsGIBTwElYPNcI3VuFp0QrkfRvm4lbTCr2kfv/M2rcVueAE4wA0Ni02/Xg7jTpT57z3kNIKYkmkJD5P3RQnExbGQtU/J5yz64LwZlSBxQLoDaKkphdhdqGZyqFiMc7N7s= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1673594273; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To; bh=RWqv2UDjZ4f318yVDtNU1XGZ6o3BU4HuPw8z0xEumfE=; b=mjcx7OV/ZzxynrelwEO2vxYJ3+dZoTklulJDuiBegeYtV25V6VbdS4dK0C5BSSJseZlPXQHM/JWSAeKbtCH6xfuhPTRxDBOvRWXbw0j21bMMY2ViQX/DgbSYxMs0GA4aKKNkI5ooeeskXVOVtisyoIpbiNaACRH7BA++L5zqLoM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+98450+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1673594273448929.9713248878213; Thu, 12 Jan 2023 23:17:53 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id aZQjYY1788612xV8FXxvvTo5; Thu, 12 Jan 2023 23:17:53 -0800 X-Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by mx.groups.io with SMTP id smtpd.web11.80768.1673594263982383415 for ; Thu, 12 Jan 2023 23:17:52 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10588"; a="410169797" X-IronPort-AV: E=Sophos;i="5.97,213,1669104000"; d="scan'208";a="410169797" X-Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Jan 2023 23:17:52 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10588"; a="688646224" X-IronPort-AV: E=Sophos;i="5.97,213,1669104000"; d="scan'208";a="688646224" X-Received: from sh1gapp1009.ccr.corp.intel.com ([10.239.189.79]) by orsmga008.jf.intel.com with ESMTP; 12 Jan 2023 23:17:50 -0800 From: "Wu, Jiaxin" To: devel@edk2.groups.io Cc: Eric Dong , Ray Ni , Zeng Star , Laszlo Ersek , Gerd Hoffmann , Rahul Kumar Subject: [edk2-devel] [PATCH v1 4/4] OvmfPkg/SmmCpuFeaturesLib: Skip to configure SMBASE Date: Fri, 13 Jan 2023 15:17:38 +0800 Message-Id: <20230113071738.15868-5-jiaxin.wu@intel.com> In-Reply-To: <20230113071738.15868-1-jiaxin.wu@intel.com> References: <20230113071738.15868-1-jiaxin.wu@intel.com> Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,jiaxin.wu@intel.com X-Gm-Message-State: zAlPWkR6jtJAg4Fpf8hDfOAcx1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1673594273; bh=nMT2FfYQI7PUqZO79wzLSFMCRxSsPmq3bzn+ZDWutQ8=; h=Cc:Date:From:Reply-To:Subject:To; b=M/HjU50RQmx0IkvaK1JW5k1N8QSMrOqyGtpImNH7oButlIMoYiTqPzTd/obEn+HTHT1 MiGcS2E9/uGv3T2uW2Iir78PCZNO0iovgG5rnfskQMDayhAavzi9DDiP7zYVK+gW3/PLO CTEK9IhL6Cjdw9soU5SzAs6jJJml6GBH5fU= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1673594274194100021 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This patch is to aviod configure SMBASE if SmBase relocation has been done. If gSmmBaseHobGuid found, means SmBase info has been relocated and recorded in the SmBase array. No need to do the relocation in SmmCpuFeaturesInitializeProcessor(). Cc: Eric Dong Cc: Ray Ni Cc: Zeng Star Cc: Laszlo Ersek Cc: Gerd Hoffmann Cc: Rahul Kumar Signed-off-by: Jiaxin Wu --- .../Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c | 39 +++++++++++++++++-= ---- .../SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf | 4 +++ 2 files changed, 34 insertions(+), 9 deletions(-) diff --git a/OvmfPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c b/OvmfPk= g/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c index 6693666d04..00c84877ed 100644 --- a/OvmfPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c +++ b/OvmfPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c @@ -15,20 +15,28 @@ #include #include #include #include #include +#include #include #include #include #include +#include =20 // // EFER register LMA bit // #define LMA BIT10 =20 +// +// Indicate SmBase for each Processors has been relocated or not. If TRUE, +// means no need to do the relocation in SmmCpuFeaturesInitializeProcessor= (). +// +BOOLEAN mSmBaseRelocated; + /** The constructor function =20 @param[in] ImageHandle The firmware allocated handle for the EFI image. @param[in] SystemTable A pointer to the EFI System Table. @@ -41,10 +49,18 @@ EFIAPI SmmCpuFeaturesLibConstructor ( IN EFI_HANDLE ImageHandle, IN EFI_SYSTEM_TABLE *SystemTable ) { + // + // If gSmmBaseHobGuid found, means SmBase info has been relocated and re= corded + // in the SmBase array. + // + if (GetFirstGuidHob (&gSmmBaseHobGuid) !=3D NULL) { + mSmBaseRelocated =3D TRUE; + } + // // No need to program SMRRs on our virtual platform. // return EFI_SUCCESS; } @@ -83,20 +99,25 @@ SmmCpuFeaturesInitializeProcessor ( ) { QEMU_SMRAM_SAVE_STATE_MAP *CpuState; =20 // - // Configure SMBASE. + // No need to configure SMBASE if SmBase relocation has been done. // - CpuState =3D (QEMU_SMRAM_SAVE_STATE_MAP *)(UINTN)( - SMM_DEFAULT_SMBASE + - SMRAM_SAVE_STATE_MAP_OFF= SET - ); - if ((CpuState->x86.SMMRevId & 0xFFFF) =3D=3D 0) { - CpuState->x86.SMBASE =3D (UINT32)CpuHotPlugData->SmBase[CpuIndex]; - } else { - CpuState->x64.SMBASE =3D (UINT32)CpuHotPlugData->SmBase[CpuIndex]; + if (!mSmBaseRelocated) { + // + // Configure SMBASE. + // + CpuState =3D (QEMU_SMRAM_SAVE_STATE_MAP *)(UINTN)( + SMM_DEFAULT_SMBASE + + SMRAM_SAVE_STATE_MAP_O= FFSET + ); + if ((CpuState->x86.SMMRevId & 0xFFFF) =3D=3D 0) { + CpuState->x86.SMBASE =3D (UINT32)CpuHotPlugData->SmBase[CpuIndex]; + } else { + CpuState->x64.SMBASE =3D (UINT32)CpuHotPlugData->SmBase[CpuIndex]; + } } =20 // // No need to program SMRRs on our virtual platform. // diff --git a/OvmfPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf b/Ovmf= Pkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf index 8a426a4c10..6a281518f5 100644 --- a/OvmfPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf +++ b/OvmfPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf @@ -33,10 +33,14 @@ MemoryAllocationLib PcdLib SafeIntLib SmmServicesTableLib UefiBootServicesTableLib + HobLib + +[Guids] + gSmmBaseHobGuid ## CONSUMES =20 [Pcd] gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber gUefiOvmfPkgTokenSpaceGuid.PcdCpuHotEjectDataAddress gUefiOvmfPkgTokenSpaceGuid.PcdQ35SmramAtDefaultSmbase --=20 2.16.2.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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