.../Feature/VTd/IntelVTdDmarPei/IntelVTdDmar.c | 3 +-- .../Feature/VTd/IntelVTdDxe/DmarAcpiTable.c | 8 ++++---- .../IntelSiliconPkg/Feature/VTd/IntelVTdDxe/VtdReg.c | 3 +-- 3 files changed, 6 insertions(+), 8 deletions(-)
Refine the DRHD table print message.
Remove unused variable.
Hsd-es-id: 15012152545
Signed-off-by: Sheng Wei <w.sheng@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Rangasai V Chaganty <rangasai.v.chaganty@intel.com>
Cc: Jenny Huang <jenny.huang@intel.com>
Cc: Robert Kowalewski <robert.kowalewski@intel.com>
---
.../Feature/VTd/IntelVTdDmarPei/IntelVTdDmar.c | 3 +--
.../Feature/VTd/IntelVTdDxe/DmarAcpiTable.c | 8 ++++----
.../IntelSiliconPkg/Feature/VTd/IntelVTdDxe/VtdReg.c | 3 +--
3 files changed, 6 insertions(+), 8 deletions(-)
diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDmarPei/IntelVTdDmar.c b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDmarPei/IntelVTdDmar.c
index 24beccd26..af85a3d8e 100644
--- a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDmarPei/IntelVTdDmar.c
+++ b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDmarPei/IntelVTdDmar.c
@@ -486,7 +486,6 @@ EnableDmar (
IN UINTN RootEntryTable
)
{
- UINT32 Reg32;
UINTN VtdUnitBaseAddress;
BOOLEAN TEWasEnabled;
@@ -529,7 +528,7 @@ EnableDmar (
//
// Init DMAr Fault Event and Data registers
//
- Reg32 = MmioRead32 (VtdUnitBaseAddress + R_FEDATA_REG);
+ MmioRead32 (VtdUnitBaseAddress + R_FEDATA_REG);
//
// Write Buffer Flush before invalidation
diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/DmarAcpiTable.c b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/DmarAcpiTable.c
index 42e1b1449..a485f4d9a 100644
--- a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/DmarAcpiTable.c
+++ b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/DmarAcpiTable.c
@@ -536,14 +536,14 @@ DumpDmarDrhd (
" Flags ................................................ 0x%02x\n",
Drhd->Flags
));
- DEBUG ((DEBUG_INFO,
- " Size ................................................. 0x%02x\n",
- Drhd->Size
- ));
DEBUG ((DEBUG_INFO,
" INCLUDE_PCI_ALL .................................... 0x%02x\n",
Drhd->Flags & EFI_ACPI_DMAR_DRHD_FLAGS_INCLUDE_PCI_ALL
));
+ DEBUG ((DEBUG_INFO,
+ " Size ................................................. 0x%02x\n",
+ Drhd->Size
+ ));
DEBUG ((DEBUG_INFO,
" Segment Number ....................................... 0x%04x\n",
Drhd->SegmentNumber
diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/VtdReg.c b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/VtdReg.c
index 1b354e850..8e834f4c4 100644
--- a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/VtdReg.c
+++ b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/VtdReg.c
@@ -573,7 +573,6 @@ EnableDmar (
)
{
UINTN Index;
- UINT32 Reg32;
UINTN VtdUnitBaseAddress;
BOOLEAN TEWasEnabled;
@@ -615,7 +614,7 @@ EnableDmar (
//
// Init DMAr Fault Event and Data registers
//
- Reg32 = MmioRead32 (mVtdUnitInformation[Index].VtdUnitBaseAddress + R_FEDATA_REG);
+ MmioRead32 (mVtdUnitInformation[Index].VtdUnitBaseAddress + R_FEDATA_REG);
//
// Write Buffer Flush before invalidation
--
2.26.2.windows.1
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Reviewed-by: Robert Kowalewski <robert.kowalewski@intel.com> -----Original Message----- From: Sheng, W <w.sheng@intel.com> Sent: Tuesday, October 18, 2022 8:43 AM To: devel@edk2.groups.io Cc: Ni, Ray <ray.ni@intel.com>; Chaganty, Rangasai V <rangasai.v.chaganty@intel.com>; Huang, Jenny <jenny.huang@intel.com>; Kowalewski, Robert <robert.kowalewski@intel.com> Subject: [PATCH] IntelSiliconPkg/VTd: Refine VTd core driver Refine the DRHD table print message. Remove unused variable. Hsd-es-id: 15012152545 Signed-off-by: Sheng Wei <w.sheng@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Rangasai V Chaganty <rangasai.v.chaganty@intel.com> Cc: Jenny Huang <jenny.huang@intel.com> Cc: Robert Kowalewski <robert.kowalewski@intel.com> --- .../Feature/VTd/IntelVTdDmarPei/IntelVTdDmar.c | 3 +-- .../Feature/VTd/IntelVTdDxe/DmarAcpiTable.c | 8 ++++---- .../IntelSiliconPkg/Feature/VTd/IntelVTdDxe/VtdReg.c | 3 +-- 3 files changed, 6 insertions(+), 8 deletions(-) diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDmarPei/IntelVTdDmar.c b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDmarPei/IntelVTdDmar.c index 24beccd26..af85a3d8e 100644 --- a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDmarPei/IntelVTdDmar.c +++ b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDmarPei/IntelVTdDmar.c @@ -486,7 +486,6 @@ EnableDmar ( IN UINTN RootEntryTable ) { - UINT32 Reg32; UINTN VtdUnitBaseAddress; BOOLEAN TEWasEnabled; @@ -529,7 +528,7 @@ EnableDmar ( // // Init DMAr Fault Event and Data registers // - Reg32 = MmioRead32 (VtdUnitBaseAddress + R_FEDATA_REG); + MmioRead32 (VtdUnitBaseAddress + R_FEDATA_REG); // // Write Buffer Flush before invalidation diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/DmarAcpiTable.c b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/DmarAcpiTable.c index 42e1b1449..a485f4d9a 100644 --- a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/DmarAcpiTable.c +++ b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/DmarAcpiTable.c @@ -536,14 +536,14 @@ DumpDmarDrhd ( " Flags ................................................ 0x%02x\n", Drhd->Flags )); - DEBUG ((DEBUG_INFO, - " Size ................................................. 0x%02x\n", - Drhd->Size - )); DEBUG ((DEBUG_INFO, " INCLUDE_PCI_ALL .................................... 0x%02x\n", Drhd->Flags & EFI_ACPI_DMAR_DRHD_FLAGS_INCLUDE_PCI_ALL )); + DEBUG ((DEBUG_INFO, + " Size ................................................. 0x%02x\n", + Drhd->Size + )); DEBUG ((DEBUG_INFO, " Segment Number ....................................... 0x%04x\n", Drhd->SegmentNumber diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/VtdReg.c b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/VtdReg.c index 1b354e850..8e834f4c4 100644 --- a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/VtdReg.c +++ b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/VtdReg.c @@ -573,7 +573,6 @@ EnableDmar ( ) { UINTN Index; - UINT32 Reg32; UINTN VtdUnitBaseAddress; BOOLEAN TEWasEnabled; @@ -615,7 +614,7 @@ EnableDmar ( // // Init DMAr Fault Event and Data registers // - Reg32 = MmioRead32 (mVtdUnitInformation[Index].VtdUnitBaseAddress + R_FEDATA_REG); + MmioRead32 (mVtdUnitInformation[Index].VtdUnitBaseAddress + R_FEDATA_REG); // // Write Buffer Flush before invalidation -- 2.26.2.windows.1 --------------------------------------------------------------------- Intel Technology Poland sp. z o.o. ul. Slowackiego 173 | 80-298 Gdansk | Sad Rejonowy Gdansk Polnoc | VII Wydzial Gospodarczy Krajowego Rejestru Sadowego - KRS 101882 | NIP 957-07-52-316 | Kapital zakladowy 200.000 PLN. Spolka oswiadcza, ze posiada status duzego przedsiebiorcy w rozumieniu ustawy z dnia 8 marca 2013 r. o przeciwdzialaniu nadmiernym opoznieniom w transakcjach handlowych. Ta wiadomosc wraz z zalacznikami jest przeznaczona dla okreslonego adresata i moze zawierac informacje poufne. W razie przypadkowego otrzymania tej wiadomosci, prosimy o powiadomienie nadawcy oraz trwale jej usuniecie; jakiekolwiek przegladanie lub rozpowszechnianie jest zabronione. This e-mail and any attachments may contain confidential material for the sole use of the intended recipient(s). If you are not the intended recipient, please contact the sender and delete all copies; any review or distribution by others is strictly prohibited. -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#95311): https://edk2.groups.io/g/devel/message/95311 Mute This Topic: https://groups.io/mt/94403119/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=-=-=-=-=-=-=-=-=-=-=-
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