From nobody Sat May 18 16:47:04 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+95310+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+95310+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1666075398; cv=none; d=zohomail.com; s=zohoarc; b=BbC8Y3M+PQGcYbFjhrTs/iCH7FHoMk4/fR23ipB8jZzz2kdO8JjRVV/5L4QGR0lLQqnrmqVQf07NlkbpSxrrm7kdtDFh4esAihoSQ8E/WNnCmRUJabgeNHOw4jSwGw3O1i9MTNkSN4+n6qCBbzsRy1mB8ShMe49rUqueAyGQTSQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1666075398; h=Content-Transfer-Encoding:Cc:Date:From:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Sender:Subject:To; bh=EzhnYzpXFpnXhLaiBBM9qziG67UV7QyIAXjelejECqI=; b=Of71GOqK62p0PfltejhOGTSJg7ZtHBu3DC7hjp5KmEW5rVE8d5pEidCCQmkMeUcbCVavyS5hn+I6Om9mRUsYQ/3/KQNb7MDhufmK7pveiVGYUItjTp/8UYJ2oAtTxsO37S4Vq3ZGXi7z2NRnoLPzICBafWJ6xnJLg0f6nv4SHbo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+95310+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1666075398564916.6895938081138; Mon, 17 Oct 2022 23:43:18 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id tjytYY1788612xH063KCEjhT; Mon, 17 Oct 2022 23:43:18 -0700 X-Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by mx.groups.io with SMTP id smtpd.web08.4005.1666075397273709613 for ; Mon, 17 Oct 2022 23:43:17 -0700 X-IronPort-AV: E=McAfee;i="6500,9779,10503"; a="305997946" X-IronPort-AV: E=Sophos;i="5.95,193,1661842800"; d="scan'208";a="305997946" X-Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Oct 2022 23:43:16 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10503"; a="579659375" X-IronPort-AV: E=Sophos;i="5.95,193,1661842800"; d="scan'208";a="579659375" X-Received: from shwdesssddpdwei.ccr.corp.intel.com ([10.239.157.43]) by orsmga003.jf.intel.com with ESMTP; 17 Oct 2022 23:43:14 -0700 From: "Sheng Wei" To: devel@edk2.groups.io Cc: Ray Ni , Rangasai V Chaganty , Jenny Huang , Robert Kowalewski Subject: [edk2-devel] [PATCH] IntelSiliconPkg/VTd: Refine VTd core driver Date: Tue, 18 Oct 2022 14:43:11 +0800 Message-Id: <20221018064311.186-1-w.sheng@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,w.sheng@intel.com X-Gm-Message-State: fjq3EFOWPRhgRZqcWVY62zTUx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1666075398; bh=78gj32be/0G5h2p9yYoyteXmo7bjqo3m1q/4L6TT9oY=; h=Cc:Date:From:Reply-To:Subject:To; b=Ik1o5fbAO21ot+uzDiU/PMKY/K9wOX8yd97+thzuMbE4zvYgn770/vRQWEzHT3QegH5 M64Jkm0iGHDBlh5xUieEy4gRkXqBUDKZGTe+W+wx8dTiuh2XhfVz/eh99CiW2j4X6QxO7 hSLuMvuBKhUx6gmjxly1Fu9d2r2Qo/lbu48= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1666075399057100003 Content-Type: text/plain; charset="utf-8" Refine the DRHD table print message. Remove unused variable. Hsd-es-id: 15012152545 Signed-off-by: Sheng Wei Cc: Ray Ni Cc: Rangasai V Chaganty Cc: Jenny Huang Cc: Robert Kowalewski Reviewed-by: Robert Kowalewski --- .../Feature/VTd/IntelVTdDmarPei/IntelVTdDmar.c | 3 +-- .../Feature/VTd/IntelVTdDxe/DmarAcpiTable.c | 8 ++++---- .../IntelSiliconPkg/Feature/VTd/IntelVTdDxe/VtdReg.c | 3 +-- 3 files changed, 6 insertions(+), 8 deletions(-) diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDmarPei/Inte= lVTdDmar.c b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDmarPei/Inte= lVTdDmar.c index 24beccd26..af85a3d8e 100644 --- a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDmarPei/IntelVTdDma= r.c +++ b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDmarPei/IntelVTdDma= r.c @@ -486,7 +486,6 @@ EnableDmar ( IN UINTN RootEntryTable ) { - UINT32 Reg32; UINTN VtdUnitBaseAddress; BOOLEAN TEWasEnabled; =20 @@ -529,7 +528,7 @@ EnableDmar ( // // Init DMAr Fault Event and Data registers // - Reg32 =3D MmioRead32 (VtdUnitBaseAddress + R_FEDATA_REG); + MmioRead32 (VtdUnitBaseAddress + R_FEDATA_REG); =20 // // Write Buffer Flush before invalidation diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/DmarAcpi= Table.c b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/DmarAcpiTab= le.c index 42e1b1449..a485f4d9a 100644 --- a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/DmarAcpiTable.c +++ b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/DmarAcpiTable.c @@ -536,14 +536,14 @@ DumpDmarDrhd ( " Flags ................................................ 0x%02x\n", Drhd->Flags )); - DEBUG ((DEBUG_INFO, - " Size ................................................. 0x%02x\n", - Drhd->Size - )); DEBUG ((DEBUG_INFO, " INCLUDE_PCI_ALL .................................... 0x%02x\n", Drhd->Flags & EFI_ACPI_DMAR_DRHD_FLAGS_INCLUDE_PCI_ALL )); + DEBUG ((DEBUG_INFO, + " Size ................................................. 0x%02x\n", + Drhd->Size + )); DEBUG ((DEBUG_INFO, " Segment Number ....................................... 0x%04x\n", Drhd->SegmentNumber diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/VtdReg.c= b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/VtdReg.c index 1b354e850..8e834f4c4 100644 --- a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/VtdReg.c +++ b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/VtdReg.c @@ -573,7 +573,6 @@ EnableDmar ( ) { UINTN Index; - UINT32 Reg32; UINTN VtdUnitBaseAddress; BOOLEAN TEWasEnabled; =20 @@ -615,7 +614,7 @@ EnableDmar ( // // Init DMAr Fault Event and Data registers // - Reg32 =3D MmioRead32 (mVtdUnitInformation[Index].VtdUnitBaseAddress + = R_FEDATA_REG); + MmioRead32 (mVtdUnitInformation[Index].VtdUnitBaseAddress + R_FEDATA_R= EG); =20 // // Write Buffer Flush before invalidation --=20 2.26.2.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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