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The m1_pmu_events and m1_pmu_event_affinity are generated from the script [1], which consumes the plist file from Apple. And then added these events to m1_pmu_perf_map and m1_pmu_event_attrs with Apple's documentation [2]. Link: https://github.com/cyyself/m1-pmu-gen [1] Link: https://developer.apple.com/download/apple-silicon-cpu-optimization-g= uide/ [2] Signed-off-by: Yangyu Chen Acked-by: Hector Martin --- drivers/perf/apple_m1_cpu_pmu.c | 204 +++++++++++++++++++++----------- 1 file changed, 132 insertions(+), 72 deletions(-) diff --git a/drivers/perf/apple_m1_cpu_pmu.c b/drivers/perf/apple_m1_cpu_pm= u.c index f322e5ca1114..e6045314ae97 100644 --- a/drivers/perf/apple_m1_cpu_pmu.c +++ b/drivers/perf/apple_m1_cpu_pmu.c @@ -47,46 +47,79 @@ * implementations, we'll have to introduce per cpu-type tables. */ enum m1_pmu_events { - M1_PMU_PERFCTR_UNKNOWN_01 =3D 0x01, - M1_PMU_PERFCTR_CPU_CYCLES =3D 0x02, - M1_PMU_PERFCTR_INSTRUCTIONS =3D 0x8c, - M1_PMU_PERFCTR_UNKNOWN_8d =3D 0x8d, - M1_PMU_PERFCTR_UNKNOWN_8e =3D 0x8e, - M1_PMU_PERFCTR_UNKNOWN_8f =3D 0x8f, - M1_PMU_PERFCTR_UNKNOWN_90 =3D 0x90, - M1_PMU_PERFCTR_UNKNOWN_93 =3D 0x93, - M1_PMU_PERFCTR_UNKNOWN_94 =3D 0x94, - M1_PMU_PERFCTR_UNKNOWN_95 =3D 0x95, - M1_PMU_PERFCTR_UNKNOWN_96 =3D 0x96, - M1_PMU_PERFCTR_UNKNOWN_97 =3D 0x97, - M1_PMU_PERFCTR_UNKNOWN_98 =3D 0x98, - M1_PMU_PERFCTR_UNKNOWN_99 =3D 0x99, - M1_PMU_PERFCTR_UNKNOWN_9a =3D 0x9a, - M1_PMU_PERFCTR_UNKNOWN_9b =3D 0x9b, - M1_PMU_PERFCTR_UNKNOWN_9c =3D 0x9c, - M1_PMU_PERFCTR_UNKNOWN_9f =3D 0x9f, - M1_PMU_PERFCTR_UNKNOWN_bf =3D 0xbf, - M1_PMU_PERFCTR_UNKNOWN_c0 =3D 0xc0, - M1_PMU_PERFCTR_UNKNOWN_c1 =3D 0xc1, - M1_PMU_PERFCTR_UNKNOWN_c4 =3D 0xc4, - M1_PMU_PERFCTR_UNKNOWN_c5 =3D 0xc5, - M1_PMU_PERFCTR_UNKNOWN_c6 =3D 0xc6, - M1_PMU_PERFCTR_UNKNOWN_c8 =3D 0xc8, - M1_PMU_PERFCTR_UNKNOWN_ca =3D 0xca, - M1_PMU_PERFCTR_UNKNOWN_cb =3D 0xcb, - M1_PMU_PERFCTR_UNKNOWN_f5 =3D 0xf5, - M1_PMU_PERFCTR_UNKNOWN_f6 =3D 0xf6, - M1_PMU_PERFCTR_UNKNOWN_f7 =3D 0xf7, - M1_PMU_PERFCTR_UNKNOWN_f8 =3D 0xf8, - M1_PMU_PERFCTR_UNKNOWN_fd =3D 0xfd, - M1_PMU_PERFCTR_LAST =3D M1_PMU_CFG_EVENT, + M1_PMU_PERFCTR_RETIRE_UOP =3D 0x1, + M1_PMU_PERFCTR_CORE_ACTIVE_CYCLE =3D 0x2, + M1_PMU_PERFCTR_L1I_TLB_FILL =3D 0x4, + M1_PMU_PERFCTR_L1D_TLB_FILL =3D 0x5, + M1_PMU_PERFCTR_MMU_TABLE_WALK_INSTRUCTION =3D 0x7, + M1_PMU_PERFCTR_MMU_TABLE_WALK_DATA =3D 0x8, + M1_PMU_PERFCTR_L2_TLB_MISS_INSTRUCTION =3D 0xa, + M1_PMU_PERFCTR_L2_TLB_MISS_DATA =3D 0xb, + M1_PMU_PERFCTR_MMU_VIRTUAL_MEMORY_FAULT_NONSPEC =3D 0xd, + M1_PMU_PERFCTR_SCHEDULE_UOP =3D 0x52, + M1_PMU_PERFCTR_INTERRUPT_PENDING =3D 0x6c, + M1_PMU_PERFCTR_MAP_STALL_DISPATCH =3D 0x70, + M1_PMU_PERFCTR_MAP_REWIND =3D 0x75, + M1_PMU_PERFCTR_MAP_STALL =3D 0x76, + M1_PMU_PERFCTR_MAP_INT_UOP =3D 0x7c, + M1_PMU_PERFCTR_MAP_LDST_UOP =3D 0x7d, + M1_PMU_PERFCTR_MAP_SIMD_UOP =3D 0x7e, + M1_PMU_PERFCTR_FLUSH_RESTART_OTHER_NONSPEC =3D 0x84, + M1_PMU_PERFCTR_INST_ALL =3D 0x8c, + M1_PMU_PERFCTR_INST_BRANCH =3D 0x8d, + M1_PMU_PERFCTR_INST_BRANCH_CALL =3D 0x8e, + M1_PMU_PERFCTR_INST_BRANCH_RET =3D 0x8f, + M1_PMU_PERFCTR_INST_BRANCH_TAKEN =3D 0x90, + M1_PMU_PERFCTR_INST_BRANCH_INDIR =3D 0x93, + M1_PMU_PERFCTR_INST_BRANCH_COND =3D 0x94, + M1_PMU_PERFCTR_INST_INT_LD =3D 0x95, + M1_PMU_PERFCTR_INST_INT_ST =3D 0x96, + M1_PMU_PERFCTR_INST_INT_ALU =3D 0x97, + M1_PMU_PERFCTR_INST_SIMD_LD =3D 0x98, + M1_PMU_PERFCTR_INST_SIMD_ST =3D 0x99, + M1_PMU_PERFCTR_INST_SIMD_ALU =3D 0x9a, + M1_PMU_PERFCTR_INST_LDST =3D 0x9b, + M1_PMU_PERFCTR_INST_BARRIER =3D 0x9c, + M1_PMU_PERFCTR_UNKNOWN_9f =3D 0x9f, + M1_PMU_PERFCTR_L1D_TLB_ACCESS =3D 0xa0, + M1_PMU_PERFCTR_L1D_TLB_MISS =3D 0xa1, + M1_PMU_PERFCTR_L1D_CACHE_MISS_ST =3D 0xa2, + M1_PMU_PERFCTR_L1D_CACHE_MISS_LD =3D 0xa3, + M1_PMU_PERFCTR_LD_UNIT_UOP =3D 0xa6, + M1_PMU_PERFCTR_ST_UNIT_UOP =3D 0xa7, + M1_PMU_PERFCTR_L1D_CACHE_WRITEBACK =3D 0xa8, + M1_PMU_PERFCTR_LDST_X64_UOP =3D 0xb1, + M1_PMU_PERFCTR_LDST_XPG_UOP =3D 0xb2, + M1_PMU_PERFCTR_ATOMIC_OR_EXCLUSIVE_SUCC =3D 0xb3, + M1_PMU_PERFCTR_ATOMIC_OR_EXCLUSIVE_FAIL =3D 0xb4, + M1_PMU_PERFCTR_L1D_CACHE_MISS_LD_NONSPEC =3D 0xbf, + M1_PMU_PERFCTR_L1D_CACHE_MISS_ST_NONSPEC =3D 0xc0, + M1_PMU_PERFCTR_L1D_TLB_MISS_NONSPEC =3D 0xc1, + M1_PMU_PERFCTR_ST_MEMORY_ORDER_VIOLATION_NONSPEC =3D 0xc4, + M1_PMU_PERFCTR_BRANCH_COND_MISPRED_NONSPEC =3D 0xc5, + M1_PMU_PERFCTR_BRANCH_INDIR_MISPRED_NONSPEC =3D 0xc6, + M1_PMU_PERFCTR_BRANCH_RET_INDIR_MISPRED_NONSPEC =3D 0xc8, + M1_PMU_PERFCTR_BRANCH_CALL_INDIR_MISPRED_NONSPEC =3D 0xca, + M1_PMU_PERFCTR_BRANCH_MISPRED_NONSPEC =3D 0xcb, + M1_PMU_PERFCTR_L1I_TLB_MISS_DEMAND =3D 0xd4, + M1_PMU_PERFCTR_MAP_DISPATCH_BUBBLE =3D 0xd6, + M1_PMU_PERFCTR_L1I_CACHE_MISS_DEMAND =3D 0xdb, + M1_PMU_PERFCTR_FETCH_RESTART =3D 0xde, + M1_PMU_PERFCTR_ST_NT_UOP =3D 0xe5, + M1_PMU_PERFCTR_LD_NT_UOP =3D 0xe6, + M1_PMU_PERFCTR_UNKNOWN_f5 =3D 0xf5, + M1_PMU_PERFCTR_UNKNOWN_f6 =3D 0xf6, + M1_PMU_PERFCTR_UNKNOWN_f7 =3D 0xf7, + M1_PMU_PERFCTR_UNKNOWN_f8 =3D 0xf8, + M1_PMU_PERFCTR_UNKNOWN_fd =3D 0xfd, + M1_PMU_PERFCTR_LAST =3D M1_PMU_CFG_EVENT, =20 /* * From this point onwards, these are not actual HW events, * but attributes that get stored in hw->config_base. */ - M1_PMU_CFG_COUNT_USER =3D BIT(8), - M1_PMU_CFG_COUNT_KERNEL =3D BIT(9), + M1_PMU_CFG_COUNT_USER =3D BIT(8), + M1_PMU_CFG_COUNT_KERNEL =3D BIT(9), }; =20 /* @@ -96,45 +129,48 @@ enum m1_pmu_events { * counters had strange affinities. */ static const u16 m1_pmu_event_affinity[M1_PMU_PERFCTR_LAST + 1] =3D { - [0 ... M1_PMU_PERFCTR_LAST] =3D ANY_BUT_0_1, - [M1_PMU_PERFCTR_UNKNOWN_01] =3D BIT(7), - [M1_PMU_PERFCTR_CPU_CYCLES] =3D ANY_BUT_0_1 | BIT(0), - [M1_PMU_PERFCTR_INSTRUCTIONS] =3D BIT(7) | BIT(1), - [M1_PMU_PERFCTR_UNKNOWN_8d] =3D ONLY_5_6_7, - [M1_PMU_PERFCTR_UNKNOWN_8e] =3D ONLY_5_6_7, - [M1_PMU_PERFCTR_UNKNOWN_8f] =3D ONLY_5_6_7, - [M1_PMU_PERFCTR_UNKNOWN_90] =3D ONLY_5_6_7, - [M1_PMU_PERFCTR_UNKNOWN_93] =3D ONLY_5_6_7, - [M1_PMU_PERFCTR_UNKNOWN_94] =3D ONLY_5_6_7, - [M1_PMU_PERFCTR_UNKNOWN_95] =3D ONLY_5_6_7, - [M1_PMU_PERFCTR_UNKNOWN_96] =3D ONLY_5_6_7, - [M1_PMU_PERFCTR_UNKNOWN_97] =3D BIT(7), - [M1_PMU_PERFCTR_UNKNOWN_98] =3D ONLY_5_6_7, - [M1_PMU_PERFCTR_UNKNOWN_99] =3D ONLY_5_6_7, - [M1_PMU_PERFCTR_UNKNOWN_9a] =3D BIT(7), - [M1_PMU_PERFCTR_UNKNOWN_9b] =3D ONLY_5_6_7, - [M1_PMU_PERFCTR_UNKNOWN_9c] =3D ONLY_5_6_7, - [M1_PMU_PERFCTR_UNKNOWN_9f] =3D BIT(7), - [M1_PMU_PERFCTR_UNKNOWN_bf] =3D ONLY_5_6_7, - [M1_PMU_PERFCTR_UNKNOWN_c0] =3D ONLY_5_6_7, - [M1_PMU_PERFCTR_UNKNOWN_c1] =3D ONLY_5_6_7, - [M1_PMU_PERFCTR_UNKNOWN_c4] =3D ONLY_5_6_7, - [M1_PMU_PERFCTR_UNKNOWN_c5] =3D ONLY_5_6_7, - [M1_PMU_PERFCTR_UNKNOWN_c6] =3D ONLY_5_6_7, - [M1_PMU_PERFCTR_UNKNOWN_c8] =3D ONLY_5_6_7, - [M1_PMU_PERFCTR_UNKNOWN_ca] =3D ONLY_5_6_7, - [M1_PMU_PERFCTR_UNKNOWN_cb] =3D ONLY_5_6_7, - [M1_PMU_PERFCTR_UNKNOWN_f5] =3D ONLY_2_4_6, - [M1_PMU_PERFCTR_UNKNOWN_f6] =3D ONLY_2_4_6, - [M1_PMU_PERFCTR_UNKNOWN_f7] =3D ONLY_2_4_6, - [M1_PMU_PERFCTR_UNKNOWN_f8] =3D ONLY_2_TO_7, - [M1_PMU_PERFCTR_UNKNOWN_fd] =3D ONLY_2_4_6, + [0 ... M1_PMU_PERFCTR_LAST] =3D ANY_BUT_0_1, + [M1_PMU_PERFCTR_RETIRE_UOP] =3D BIT(7), + [M1_PMU_PERFCTR_CORE_ACTIVE_CYCLE] =3D ANY_BUT_0_1 | BIT(0), + [M1_PMU_PERFCTR_INST_ALL] =3D BIT(7) | BIT(1), + [M1_PMU_PERFCTR_INST_BRANCH] =3D ONLY_5_6_7, + [M1_PMU_PERFCTR_INST_BRANCH_CALL] =3D ONLY_5_6_7, + [M1_PMU_PERFCTR_INST_BRANCH_RET] =3D ONLY_5_6_7, + [M1_PMU_PERFCTR_INST_BRANCH_TAKEN] =3D ONLY_5_6_7, + [M1_PMU_PERFCTR_INST_BRANCH_INDIR] =3D ONLY_5_6_7, + [M1_PMU_PERFCTR_INST_BRANCH_COND] =3D ONLY_5_6_7, + [M1_PMU_PERFCTR_INST_INT_LD] =3D ONLY_5_6_7, + [M1_PMU_PERFCTR_INST_INT_ST] =3D BIT(7), + [M1_PMU_PERFCTR_INST_INT_ALU] =3D BIT(7), + [M1_PMU_PERFCTR_INST_SIMD_LD] =3D ONLY_5_6_7, + [M1_PMU_PERFCTR_INST_SIMD_ST] =3D ONLY_5_6_7, + [M1_PMU_PERFCTR_INST_SIMD_ALU] =3D BIT(7), + [M1_PMU_PERFCTR_INST_LDST] =3D BIT(7), + [M1_PMU_PERFCTR_INST_BARRIER] =3D ONLY_5_6_7, + [M1_PMU_PERFCTR_UNKNOWN_9f] =3D BIT(7), + [M1_PMU_PERFCTR_L1D_CACHE_MISS_LD_NONSPEC] =3D ONLY_5_6_7, + [M1_PMU_PERFCTR_L1D_CACHE_MISS_ST_NONSPEC] =3D ONLY_5_6_7, + [M1_PMU_PERFCTR_L1D_TLB_MISS_NONSPEC] =3D ONLY_5_6_7, + [M1_PMU_PERFCTR_ST_MEMORY_ORDER_VIOLATION_NONSPEC] =3D ONLY_5_6_7, + [M1_PMU_PERFCTR_BRANCH_COND_MISPRED_NONSPEC] =3D ONLY_5_6_7, + [M1_PMU_PERFCTR_BRANCH_INDIR_MISPRED_NONSPEC] =3D ONLY_5_6_7, + [M1_PMU_PERFCTR_BRANCH_RET_INDIR_MISPRED_NONSPEC] =3D ONLY_5_6_7, + [M1_PMU_PERFCTR_BRANCH_CALL_INDIR_MISPRED_NONSPEC] =3D ONLY_5_6_7, + [M1_PMU_PERFCTR_BRANCH_MISPRED_NONSPEC] =3D ONLY_5_6_7, + [M1_PMU_PERFCTR_UNKNOWN_f5] =3D ONLY_2_4_6, + [M1_PMU_PERFCTR_UNKNOWN_f6] =3D ONLY_2_4_6, + [M1_PMU_PERFCTR_UNKNOWN_f7] =3D ONLY_2_4_6, + [M1_PMU_PERFCTR_UNKNOWN_f8] =3D ONLY_2_TO_7, + [M1_PMU_PERFCTR_UNKNOWN_fd] =3D ONLY_2_4_6, }; =20 static const unsigned m1_pmu_perf_map[PERF_COUNT_HW_MAX] =3D { PERF_MAP_ALL_UNSUPPORTED, - [PERF_COUNT_HW_CPU_CYCLES] =3D M1_PMU_PERFCTR_CPU_CYCLES, - [PERF_COUNT_HW_INSTRUCTIONS] =3D M1_PMU_PERFCTR_INSTRUCTIONS, + [PERF_COUNT_HW_CPU_CYCLES] =3D M1_PMU_PERFCTR_CORE_ACTIVE_CYCLE, + [PERF_COUNT_HW_INSTRUCTIONS] =3D M1_PMU_PERFCTR_INST_ALL, + [PERF_COUNT_HW_CACHE_MISSES] =3D M1_PMU_PERFCTR_L1D_CACHE_MISS_LD_NONSPE= C, + [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] =3D M1_PMU_PERFCTR_INST_BRANCH, + [PERF_COUNT_HW_BRANCH_MISSES] =3D M1_PMU_PERFCTR_BRANCH_MISPRED_NONSPEC, /* No idea about the rest yet */ }; =20 @@ -154,8 +190,32 @@ static ssize_t m1_pmu_events_sysfs_show(struct device = *dev, PMU_EVENT_ATTR_ID(name, m1_pmu_events_sysfs_show, config) =20 static struct attribute *m1_pmu_event_attrs[] =3D { - M1_PMU_EVENT_ATTR(cycles, M1_PMU_PERFCTR_CPU_CYCLES), - M1_PMU_EVENT_ATTR(instructions, M1_PMU_PERFCTR_INSTRUCTIONS), + M1_PMU_EVENT_ATTR(cycles, M1_PMU_PERFCTR_CORE_ACTIVE_CYCLE), + M1_PMU_EVENT_ATTR(instructions, M1_PMU_PERFCTR_INST_ALL), + M1_PMU_EVENT_ATTR(retire-uops, M1_PMU_PERFCTR_RETIRE_UOP), + M1_PMU_EVENT_ATTR(inst-branch, M1_PMU_PERFCTR_INST_BRANCH), + M1_PMU_EVENT_ATTR(inst-branch-call, M1_PMU_PERFCTR_INST_BRANCH_CALL), + M1_PMU_EVENT_ATTR(inst-branch-ret, M1_PMU_PERFCTR_INST_BRANCH_RET), + M1_PMU_EVENT_ATTR(inst-branch-taken, M1_PMU_PERFCTR_INST_BRANCH_TAKEN), + M1_PMU_EVENT_ATTR(inst-branch-indir, M1_PMU_PERFCTR_INST_BRANCH_INDIR), + M1_PMU_EVENT_ATTR(inst-branch-cond, M1_PMU_PERFCTR_INST_BRANCH_COND), + M1_PMU_EVENT_ATTR(inst-int-ld, M1_PMU_PERFCTR_INST_INT_LD), + M1_PMU_EVENT_ATTR(inst-int-st, M1_PMU_PERFCTR_INST_INT_ST), + M1_PMU_EVENT_ATTR(inst-int-alu, M1_PMU_PERFCTR_INST_INT_ALU), + M1_PMU_EVENT_ATTR(inst-simd-ld, M1_PMU_PERFCTR_INST_SIMD_LD), + M1_PMU_EVENT_ATTR(inst-simd-st, M1_PMU_PERFCTR_INST_SIMD_ST), + M1_PMU_EVENT_ATTR(inst-simd-alu, M1_PMU_PERFCTR_INST_SIMD_ALU), + M1_PMU_EVENT_ATTR(inst-ldst, M1_PMU_PERFCTR_INST_LDST), + M1_PMU_EVENT_ATTR(inst-barrier, M1_PMU_PERFCTR_INST_BARRIER), + M1_PMU_EVENT_ATTR(l1d-miss-ld, M1_PMU_PERFCTR_L1D_CACHE_MISS_LD_NONSPEC), + M1_PMU_EVENT_ATTR(l1d-miss-st, M1_PMU_PERFCTR_L1D_CACHE_MISS_ST_NONSPEC), + M1_PMU_EVENT_ATTR(l1d-tlb-miss, M1_PMU_PERFCTR_L1D_TLB_MISS_NONSPEC), + M1_PMU_EVENT_ATTR(st-mem-order-violation, M1_PMU_PERFCTR_ST_MEMORY_ORDER_= VIOLATION_NONSPEC), + M1_PMU_EVENT_ATTR(branch-cond-mispred, M1_PMU_PERFCTR_BRANCH_COND_MISPRED= _NONSPEC), + M1_PMU_EVENT_ATTR(branch-indir-mispred, M1_PMU_PERFCTR_BRANCH_INDIR_MISPR= ED_NONSPEC), + M1_PMU_EVENT_ATTR(branch-ret-indir-mispred, M1_PMU_PERFCTR_BRANCH_RET_IND= IR_MISPRED_NONSPEC), + M1_PMU_EVENT_ATTR(branch-call-indir-mispred, M1_PMU_PERFCTR_BRANCH_CALL_I= NDIR_MISPRED_NONSPEC), + M1_PMU_EVENT_ATTR(branch-mispred, M1_PMU_PERFCTR_BRANCH_MISPRED_NONSPEC), NULL, }; =20 --=20 2.45.1