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([171.213.183.153]) by newxmesmtplogicsvrszb51-1.qq.com (NewEsmtp) with SMTP id BA5B2A65; Wed, 04 Mar 2026 14:46:37 +0800 X-QQ-mid: xmsmtpt1772606797tr5kaul2k Message-ID: X-QQ-XMAILINFO: NbgegmlEc3JuAsoFIV4FrEpHIfsH/Ff30Qt86QfrF16WdoK7BTKVTmHVJgrTzs U4xONf+/dGxnwNdczW0FtLrzxSIyioNPxFb9MEnyfjEhdToQjWNhioHq6EmhKOvZlPPXHO2plpN0 0mV+8gMjsT7PzDR1lec2JCDuZrUbCUt+Wvb9jKeD2KtyYMAhvbua9cRRE8zl2qfQG60n9L6CU597 9va+LDbF89omvV8S8T0ewi+R+bDb6UVTyhicHz/nOmJipj1YsD7kVi6h2PHw5kthRHh59r5YVvzy D8OuxhQgll57wGZQ35NUIQjMebaBufsaqApkSiKdJVPTRPCg55hZsms9YNOoJR4R7i3KwFUK0+WW qUIqGmuBTz7G/anCLUPEQXvzH1lOl35nrkbExLQ4RCwK7QFsT4X3Q6mZ/glZCfHcmR15wgIU3MuU 20++QUdCDgFIlqjnQsxqeBVkBLO3AABDyx+nygi4DiOgQA3qVgXdWy4rcUJ37d+efSfQjVMuM1bL 0w+lxS2Mquf8NkqC6/XzEcvQh3I5L3WK9VxzgV3jtxYIqwCmM/KgLrOfVb2Ct2r4uBRq8Zilhm1x KYcUgCuljHqoHWHbAgGw/V/uOF8DEXhJggv62IMtcuMT3sX3AfyOQqvfvCcrRzlKakYN01ey5eRa B7n7hMSF/GXdw/4q2TmpaUqqH5RD5aTMJPJ/PZSQP8pOlRYz/H9htCI1bC2SfCEJruemEn5KsyGH /q/UGxkoe7cDnqa0NiJWaqzAvTJc6czGw23lxqHf2a2/ta/5yy8XvPcHH8IIu97KyjigWjuzgn1r 8ow61XNyU/TJY4+sociR4+M6EncFvQNUcHxeJFJGLx0XwgOFQAhdi2MiAadgtdmvYyjfAJauCnXp l+aGx80O+ufblPvTe3YD9s9jh5m8M8siIZfgSgu6/hv6tgo+ia1v3MY3u1ODZjkxLp4jyRq9L6uA lha/uItp3oa3wrI4FHU1t0R9qoRlcG5peS8G9fi/LjkYdsxRfeUIWs9496xJVkw2pbNj45pqu/PM h8ZDWYleCknbxwpLx8dWLt/6laj94m8eCKWgr9BQ== X-QQ-XMRINFO: NS+P29fieYNwqS3WCnRCOn9D1NpZuCnCRA== From: LUO Haowen To: Manivannan Sadhasivam Cc: Vinod Koul , Frank Li , dmaengine@vger.kernel.org, linux-kernel@vger.kernel.org, LUO Haowen Subject: [PATCH v2] dmaengine: dw-edma: Fix multiple times setting of the CYCLE_STATE and CYCLE_BIT bits for HDMA. Date: Wed, 4 Mar 2026 14:45:09 +0800 X-OQ-MSGID: <20260304064509.342170-1-luo-hw@foxmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260304025049.324220-1-luo-hw@foxmail.com> References: <20260304025049.324220-1-luo-hw@foxmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Others have submitted this issue (https://lore.kernel.org/dmaengine/ 20240722030405.3385-1-zhengdongxiong@gxmicro.cn/),=20 but it has not been fixed yet. Therefore, more supplementary information=20 is provided here. As mentioned in the "PCS-CCS-CB-TCB" Producer-Consumer Synchronization of "DesignWare Cores PCI Express Controller Databook, version 6.00a": 1. The Consumer CYCLE_STATE (CCS) bit in the register only needs to be=20 initialized once; the value will update automatically to be=20 ~CYCLE_BIT (CB) in the next chunk. 2. The Consumer CYCLE_BIT bit in the register is loaded from the LL=20 element and tested against CCS. When CB =3D CCS, the data transfer is=20 executed. Otherwise not. The current logic sets customer (HDMA) CS and CB bits to 1 in each chunk while setting the producer (software) CB of odd chunks to 0 and even=20 chunks to 1 in the linked list. This is leading to a mismatch between=20 the producer CB and consumer CS bits. This issue can be reproduced by setting the transmission data size to exceed one chunk. By the way, in the EDMA using the same "PCS-CCS-CB-TCB" mechanism, the CS bit is only initialized once and this issue was not=20 found. Refer to=20 drivers/dma/dw-edma/dw-edma-v0-core.c:dw_edma_v0_core_start. So fix this issue by initializing the CYCLE_STATE and CYCLE_BIT bits=20 only once. Fixes: e74c39573d35 ("dmaengine: dw-edma: Add support for native HDMA") Signed-off-by: LUO Haowen Reviewed-by: Frank Li --- v2: - Add Fixes tag as suggested by maintainer drivers/dma/dw-edma/dw-hdma-v0-core.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/dma/dw-edma/dw-hdma-v0-core.c b/drivers/dma/dw-edma/dw= -hdma-v0-core.c index e3f8db4fe..ce8f7254b 100644 --- a/drivers/dma/dw-edma/dw-hdma-v0-core.c +++ b/drivers/dma/dw-edma/dw-hdma-v0-core.c @@ -252,10 +252,10 @@ static void dw_hdma_v0_core_start(struct dw_edma_chun= k *chunk, bool first) lower_32_bits(chunk->ll_region.paddr)); SET_CH_32(dw, chan->dir, chan->id, llp.msb, upper_32_bits(chunk->ll_region.paddr)); + /* Set consumer cycle */ + SET_CH_32(dw, chan->dir, chan->id, cycle_sync, + HDMA_V0_CONSUMER_CYCLE_STAT | HDMA_V0_CONSUMER_CYCLE_BIT); } - /* Set consumer cycle */ - SET_CH_32(dw, chan->dir, chan->id, cycle_sync, - HDMA_V0_CONSUMER_CYCLE_STAT | HDMA_V0_CONSUMER_CYCLE_BIT); =20 dw_hdma_v0_sync_ll_data(chunk); =20 --=20 2.34.1