From nobody Mon Feb 9 05:44:20 2026 Received: from out162-62-57-252.mail.qq.com (out162-62-57-252.mail.qq.com [162.62.57.252]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D945929E0E8 for ; Tue, 3 Feb 2026 17:21:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=162.62.57.252 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770139300; cv=none; b=Ly8qLwQEM1sDReagvlHIuUmZgNmd5Xe7EGlh9rhvlZV7au4PRgDgKQbQ/Z+JjK9+Qttgrwco84vTa+eRq0tnSwvNtJQogGCpvYKtDIaixP/MIKAT/vQ5L91UcYQ09/ASaGvhsgjN/C8IJry2+MRnr5iffu4lUaLLQtxFO7UIdJ8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770139300; c=relaxed/simple; bh=xuZSb8wrx82nyCkuqrULdZ5vRjUJ37xuFySc+t94u7Y=; h=Message-ID:From:To:Cc:Subject:Date:In-Reply-To:References: MIME-Version; b=G0jcrjVMcuPzzw6HEJUayrN+Zd+tlV7X5KNyZY2Z2lti7ScVGgyXnGS8o8Jjng6wRAq43Ea5NyvwCvso2gObKpLE0do5YLPlKM5zAn5GrnxAyJjhYmGS4afNDisCPv79Pm40wkELTjTb/+mYeWFroNQDT+zWsy1qIu42SXpu+lg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=cyyself.name; spf=pass smtp.mailfrom=cyyself.name; dkim=pass (1024-bit key) header.d=qq.com header.i=@qq.com header.b=KLzY78Ol; arc=none smtp.client-ip=162.62.57.252 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=cyyself.name Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=cyyself.name Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=qq.com header.i=@qq.com header.b="KLzY78Ol" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qq.com; s=s201512; t=1770139292; bh=dKD+9ENjLymGAeCoFjskR1sIXf8hqAVovnW21Ss0ou8=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=KLzY78OlkmaZ6lz4zglo43hZ8AUbivQg0tjtBL++8UdhXtAOd7x0Xb7l04jzPXzwQ HpBwEe8mpoNrKxlu3EvBJvaI4UgBxJH230t0TkUQOskwGImqqTiwlx8IDJhBa5gJ52 vCeBSIbI2wHvRn+5yOGm9K2D8/7EPdU5ZaLUA2PY= Received: from cyy-pc.lan ([240e:379:2263:bd00:7e4b:55e4:8771:53fb]) by newxmesmtplogicsvrszb51-0.qq.com (NewEsmtp) with SMTP id 554152F2; Wed, 04 Feb 2026 01:21:20 +0800 X-QQ-mid: xmsmtpt1770139280t2ir4wb8a Message-ID: X-QQ-XMAILINFO: OK7NBzdNss/RyEGf3lskhU51JXzQy2SjuYx3vx9OVzRZrGcl9lB8qfWLqrk8xy gnbQtXhyblbq54bu3bf/vAJB3AiByawePnPpTMBNtuCXA4FksJx8DtaNBvXqyNqjswNkrurfRT0S nDMVKsIdoU9Tlv4SnWVnr6JbRDsh7pnxmPCdnj0PjjN2nZQHmwL1BcGbMSr0F9TShklL8hIlggcS 674J09u5sjwY8+QKB27NMI88QWC/dR/2pv/JymKgaqmlW2rzEfnSm//Yt17emLuDxwZ1A+mVhflp 5FSnm0SkB4D5JqRjjL7uSPvvcstn5ces4Dp20XvGQ70TmjRV+BOQV+/noPB37uRJqENqIohaff23 /pJwGsZ9aGKVlpZYRDbP0PVRmB6bQJFJb/p9xaIPveiaNOfPZ/zfNE/QQ//PoFhRuReE8TWXyZFl T8sM3slldM6/el7C8LHxAgXr0R7wewdHENLQrBdtCFflvnFHiNt4N1OcyEPVJUpLsAb53LtMmHou h3DjwwkbJAM4nqxRu/LjyVnTH7nRomHoJmuMWh/PpFrg4oxUflA0oMnK1pd8b57kmEVJBc4gdLu5 E0U5oqZ+0+cCg0zmtIKQNvp49qDGEAvO1gPQ+vu9cNZDVPdV1izolNfKCWxkYuvSXrAlgzDZD8ou bMiAOzKia9QBK4IWerItl+A6w/IhgnQsI/PNKwAv+h0kXxWVgIDKYNrFl+M50ag7zDX7UnzPX7OE 0ftiz5Gmt6PfOr/ZBnVAWL374kZgHHePqJJqrum9tahQ8WrERQIAEop0dYsH8MvZ7zewXKKCAQ/5 CYcd45MjKY2+2QJRfeZrP81jcqwW9pkKMhMyV59c6xFmhjWlsOua6csxTAlCHAudbf4z5DXGr/wl VEaP7IihGz5W7Q6qsKUXxmckvzoiPh8Tev/XmroZoEVDSZfxntveiu8dhSgOLkmZn8ULGaWOaDlg iCPNBZubuZGEmsMbyB5Z2AS4XdzsFH+pvoByNX7rr8LKfOJZixVUfQ66z9he/INVJ1IlawGV9WRb kpQ4GLmFrX7zPstzMl+gPj1ElDN+igUkOrNx3WQUnhB1dIqWCfbNBQLi4qSOXVR1pQtZmFYJiFQh PPoa7HsbxYpzwWkFNN5iajUnxBcIRIzdASjadG/hbDX79L2BzADiaJJ+N9P6yrEL5fjmiK X-QQ-XMRINFO: MSVp+SPm3vtSI1QTLgDHQqIV1w2oNKDqfg== From: Yangyu Chen To: linux-riscv@lists.infradead.org Cc: linux-kernel@vger.kernel.org, Anup Patel , Samuel Holland , Charles Mirabile , Lucas Zampieri , Thomas Gleixner , Paul Walmsley , Palmer Dabbelt , Mason Huo , Zhang Xincheng , Charlie Jenkins , Marc Zyngier , Sia Jee Heng , Ley Foon Tan , Krzysztof Kozlowski , Rob Herring , Conor Dooley , Alexandre Ghiti , devicetree@vger.kernel.org, Jia Wang , Yangyu Chen Subject: [PATCH v3 1/2] irqchip/sifive-plic: Fix wrong nr_irqs handling Date: Wed, 4 Feb 2026 01:21:16 +0800 X-OQ-MSGID: <20260203172116.1593739-1-cyy@cyyself.name> X-Mailer: git-send-email 2.51.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Since the first irq source is 1 instead of 0, when the number of irqs is multiple of 32, the last irq group will be ignored during allocation, saving, and restoring. This lead to memory corruption when accessing enable_save beyond allocated memory after commit 14ff9e54dd14 ("irqchip/sifive-plic: Cache the interrupt enable state") which will access enable_save for all sources during plic_probe. Thus, we should allocate irq_groups based on (nr_irqs + 1) instead of nr_irqs to avoid this issue. This commit also fixes related loops to have all consumer of nr_irqs consistent. This is an long standing bug since Linux v5.6 but since the last irq source is rarely used, it may not be triggered in practice until commit 14ff9e54dd14 ("irqchip/sifive-plic: Cache the interrupt enable state"). Fixes: 466008f98435 ("irqchip/sifive-plic: Support irq domain hierarchy") Fixes: e80f0b6a2cf3 ("irqchip/irq-sifive-plic: Add syscore callbacks for hi= bernation") Fixes: 4d936f10ff80 ("irqchip/sifive-plic: Probe plic driver early for Allw= inner D1 platform") Fixes: f75e07bf5226 ("irqchip/sifive-plic: Avoid interrupt ID 0 handling du= ring suspend/resume") Fixes: 14ff9e54dd14 ("irqchip/sifive-plic: Cache the interrupt enable state= ") Fixes: 539d147ef69c ("irqchip/sifive-plic: Add support for UltraRISC DP1000= PLIC") Fixes: a045359e7245 ("irqchip/sifive-plic: Fix call to __plic_toggle() in M= -Mode code path") Signed-off-by: Yangyu Chen Reported-by: Yangyu Chen Tested-by: Yangyu Chen --- drivers/irqchip/irq-sifive-plic.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive= -plic.c index 210a57959637..4658cad0d502 100644 --- a/drivers/irqchip/irq-sifive-plic.c +++ b/drivers/irqchip/irq-sifive-plic.c @@ -262,7 +262,7 @@ static int plic_irq_suspend(void *data) priv =3D per_cpu_ptr(&plic_handlers, smp_processor_id())->priv; =20 /* irq ID 0 is reserved */ - for (unsigned int i =3D 1; i < priv->nr_irqs; i++) { + for (unsigned int i =3D 1; i <=3D priv->nr_irqs; i++) { __assign_bit(i, priv->prio_save, readl(priv->regs + PRIORITY_BASE + i * PRIORITY_PER_ID)); } @@ -280,7 +280,7 @@ static void plic_irq_resume(void *data) priv =3D per_cpu_ptr(&plic_handlers, smp_processor_id())->priv; =20 /* irq ID 0 is reserved */ - for (i =3D 1; i < priv->nr_irqs; i++) { + for (i =3D 1; i <=3D priv->nr_irqs; i++) { index =3D BIT_WORD(i); writel((priv->prio_save[index] & BIT_MASK(i)) ? 1 : 0, priv->regs + PRIORITY_BASE + i * PRIORITY_PER_ID); @@ -293,7 +293,7 @@ static void plic_irq_resume(void *data) continue; =20 raw_spin_lock_irqsave(&handler->enable_lock, flags); - for (i =3D 0; i < DIV_ROUND_UP(priv->nr_irqs, 32); i++) { + for (i =3D 0; i < DIV_ROUND_UP(priv->nr_irqs + 1, 32); i++) { reg =3D handler->enable_base + i * sizeof(u32); writel(handler->enable_save[i], reg); } @@ -351,7 +351,7 @@ static int plic_irq_domain_alloc(struct irq_domain *dom= ain, unsigned int virq, if (ret) return ret; =20 - for (i =3D 0; i < nr_irqs; i++) { + for (i =3D 1; i <=3D nr_irqs; i++) { ret =3D plic_irqdomain_map(domain, virq + i, hwirq + i); if (ret) return ret; @@ -431,7 +431,7 @@ static u32 cp100_isolate_pending_irq(int nr_irq_groups,= struct plic_handler *han =20 static irq_hw_number_t cp100_get_hwirq(struct plic_handler *handler, void = __iomem *claim) { - int nr_irq_groups =3D DIV_ROUND_UP(handler->priv->nr_irqs, 32); + int nr_irq_groups =3D DIV_ROUND_UP(handler->priv->nr_irqs + 1, 32); u32 __iomem *enable =3D handler->enable_base; irq_hw_number_t hwirq =3D 0; u32 iso_mask; @@ -652,7 +652,7 @@ static int plic_probe(struct fwnode_handle *fwnode) priv->gsi_base =3D gsi_base; priv->acpi_plic_id =3D id; =20 - priv->prio_save =3D bitmap_zalloc(nr_irqs, GFP_KERNEL); + priv->prio_save =3D bitmap_zalloc(nr_irqs + 1, GFP_KERNEL); if (!priv->prio_save) { error =3D -ENOMEM; goto fail_free_priv; @@ -686,7 +686,7 @@ static int plic_probe(struct fwnode_handle *fwnode) u32 __iomem *enable_base =3D priv->regs + CONTEXT_ENABLE_BASE + i * CONTEXT_ENABLE_SIZE; =20 - for (int j =3D 0; j <=3D nr_irqs / 32; j++) + for (int j =3D 0; j <=3D (nr_irqs + 1) / 32; j++) writel(0, enable_base + j); } continue; @@ -718,7 +718,7 @@ static int plic_probe(struct fwnode_handle *fwnode) context_id * CONTEXT_ENABLE_SIZE; handler->priv =3D priv; =20 - handler->enable_save =3D kcalloc(DIV_ROUND_UP(nr_irqs, 32), + handler->enable_save =3D kcalloc(DIV_ROUND_UP(nr_irqs + 1, 32), sizeof(*handler->enable_save), GFP_KERNEL); if (!handler->enable_save) { error =3D -ENOMEM; --=20 2.51.0 From nobody Mon Feb 9 05:44:20 2026 Received: from out162-62-57-49.mail.qq.com (out162-62-57-49.mail.qq.com [162.62.57.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 06CA227E7EB for ; Tue, 3 Feb 2026 17:22:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=162.62.57.49 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; 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charset="utf-8" In PLIC, interrupt source 0 is reserved and should not be used. Therefore, the valid interrupt sources are from 1 to riscv,ndev inclusive. This commit updates the documentation to clarify this point. Signed-off-by: Yangyu Chen Acked-by: Conor Dooley --- .../bindings/interrupt-controller/sifive,plic-1.0.0.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,= plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/si= five,plic-1.0.0.yaml index 388fc2c620c0..df9578bcac89 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.= 0.0.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.= 0.0.yaml @@ -109,6 +109,8 @@ properties: $ref: /schemas/types.yaml#/definitions/uint32 description: Specifies how many external interrupts are supported by this control= ler. + Note that source 0 is reserved in PLIC, so the valid interrupt sourc= es + are 1 to riscv,ndev inclusive. =20 clocks: true =20 --=20 2.51.0